A three monomer battery centralized balancer control algorithm

Abstract

The application discloses a three-cell battery centralized equalizer control algorithm and belongs to the field of battery energy equalization. The control algorithm performs closed-loop control on the state of charge of three battery cells, adopts a PI controller to perform closed-loop control on the state of charge of each battery, and adopts a phase-shifted PWM modulation algorithm for a modulation unit, so that the purpose of three-cell battery energy equalization is achieved by reasonably controlling the on-off of a switch tube. The control algorithm adopts closed-loop control to control the energy of the three battery cells around the average value, greatly improves the control precision, effectively avoids overcharging or overdischarging of the battery, and is beneficial to further improving the use efficiency of an energy storage system.

Description

TECHNICAL FIELD

[0001] The application discloses a three-single-cell battery centralized equalizer control algorithm, and belongs to the technical field of battery energy management systems, and is used for equalizing the energy of series-connected battery cells. BACKGROUND

[0002] In recent years, domestic BMS research and development enterprises have made great progress in battery state estimation, active balancing, functional safety and other core technical fields. How to realize a more efficient and lower-loss battery energy equalizer is still the focus of the industry.

[0003] The existing equalization circuit control algorithms mainly include the following three types: actual capacity equalization, single-cell voltage equalization and state of charge equalization. The actual capacity equalization is easy to cause overcharging of single cells, shorten the service life of the battery, and has safety hazards; the single-cell voltage equalization can reflect the internal characteristics of the battery to a certain extent, but the single-cell voltage cannot accurately reflect the internal characteristics of the battery when the number of battery uses is too large or the operation condition is too complex, and the error is large; the state of charge equalization algorithm can balance the battery energy well under the condition of accurate prediction of the state of charge of the battery, and avoid overcharging or overdischarging of the battery. SUMMARY

[0004] The application aims to solve the energy balancing problem of the three-single-cell battery centralized equalizer, and provides a three-single-cell battery centralized equalizer control algorithm.

[0005] The technical scheme for solving the above problems is that the three-single-cell battery centralized equalizer control algorithm performs closed-loop control on the state of charge of three single cells, and the control algorithm steps are as follows:

[0006] Step one, initialization, in the equalization controller, the following parameter values are set by the operator according to the system requirements:

[0007] (I) The control coefficients of the first PI controller 5 are k and k, 0 < k < 100, and 0 < k < 100. p1 i1 p1 i1

[0008] (II) The control coefficients of the second PI controller 7 are k and k, 0 < k < 100, and 0 < k < 100. p2 i2 p2 i2

[0009] (III) The control coefficients of the third PI controller 9 are k and k, 0 < k < 100, and 0 < k < 100. p3 i3 p3 i3 ​​​​​​​​​​​​

[0010] Step two, using Hall sensor to sample the voltage and current of the first single battery batl, the second single battery bat2 and the third single battery bat3;

[0011] Step three, estimating the state of charge of the first single battery batl, the second single battery bat2 and the third single battery bat3 according to the battery state of charge estimation link, obtaining SOC bat1 , SOC bat2 , SOC bat3 , and calculating SOC avg : SOC avg = (SOC bat1 + SOC bat2 + SOC bat3 ) / 3;

[0012] Step four, the first controller 1, the second controller 2 and the third controller 3 execute as follows:

[0013] (I) The first comparator 4 calculates the input value of the first PI controller 5: SOC avg -SOC bat1 ;

[0014] (II) The first PI controller 5 calculates after receiving the output of the above-mentioned first comparator 4, and outputs the corresponding control quantity U batl : k p1 (SOC avg -SOC bat1 )+k i1 ∫(SOC avg -SOC bat1 )dt;

[0015] (III) The second comparator 6 calculates the input value of the second PI controller 7: SOC avg -SOC bat2 ;

[0016] (IV) The second PI controller 7 calculates after receiving the output of the above-mentioned second comparator 6, and outputs the corresponding control quantity U bat2 : k p2 (SOC avg -SOC bat2 )+k i2 ∫(SOC avg -SOC bat2 )dt;

[0017] (V) The third comparator 8 calculates the input value of the third PI controller 9: SOC avg -SOC bat3 ;

[0018] (VI) The third PI controller 9 calculates after receiving the output of the third comparator 8, and outputs the corresponding control variable U bat3 : k p3 (SOC avg -SOC bat3 )+k i3 ∫(SOC avg -SOC bat3 )dt;

[0019] Step five, the modulation unit a10, the modulation unit b11, the modulation unit c12 and the modulation unit d13 execute the following steps:

[0020] (I) U bat1 as the reference wave of the fourth comparator 14, the zero phase shift symmetrical triangle wave U ref1 as the carrier wave of the fourth comparator 14;

[0021] (II) After the logic operation e15, the driving signal PWM1 of the first switch tube S1 is obtained: when U bat1 -U ref1 >0, PWM1 is 0; otherwise, it is 1;

[0022] (III) U bat2 as the reference wave of the fifth comparator 16, the right shift 120-degree symmetrical triangle wave U ref2 as the carrier wave of the fifth comparator 9;

[0023] (IV) After the logic operation f17, the driving signal PWM2 of the second switch tube S2 is obtained: when U bat2 -U ref2 >0, PWM2 is 0; otherwise, it is 1;

[0024] (V) U bat3 as the reference wave of the sixth comparator 18, the right shift 240-degree symmetrical triangle wave U ref3 as the carrier wave of the sixth comparator 18;

[0025] (VI) After the logic operation g19, the driving PWM3 of the third switch tube S3 is obtained: when U bat3 -U ref3 >0, PWM3 is 0; otherwise, it is 1;

[0026] (VII) SOC bat2 , min(SOC bat1 , SOC bat2 , SOC bat3 ) as the input of the seventh comparator 20, when the state of charge of the second single battery bat2 is less than the first single battery bat1, the third single battery bat3, then deltaSOC is 0; otherwise, it is 1;

[0027] deltaSOC = SOC bat2 - min(SOC bat1 , SOC bat2 , SOC bat3 );

[0028] (Eight) After the logical operation h21, the driving PWM4 of the fourth switch tube S4 is obtained, when deltaSOC = 0, PWM4 is 0, otherwise 1.

[0029] The beneficial effects of the present application: three monomer battery centralized equalizer uses four switch tubes for every three battery equalization, compared with Boost circuit, the number of switch tubes is reduced by 1 / 3; the equalization control algorithm carries out closed loop control to the state of charge of 3 battery monomers, simplifies the control timing judgment. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 It is a battery pack equalization circuit schematic diagram

[0031] In the figure: Pack-i (i is 1-4) is a three monomer battery pack, B-i (i is 1-4) is a three monomer battery equalizer, bat1 is the first monomer battery, bat2 is the second monomer battery, and bat3 is the third monomer battery.

[0032] Figure 2 It is a three monomer battery centralized equalizer circuit diagram

[0033] In the figure: S1 is the first switch tube, S2 is the second switch tube, S3 is the third switch tube, S4 is the fourth switch tube, L 12 is the first equalization inductance, L 23 is the second equalization inductance.

[0034] Figure 3 It is a three monomer battery centralized equalizer control flow chart

[0035] Figure 4 It is a control block diagram of the first controller

[0036] In the figure: 1. First controller, 4. First comparator, 5. First PI controller.

[0037] Figure 5 It is a control block diagram of the second controller

[0038] In the figure: 2. Second controller, 6. Second comparator, 7. Second PI controller.

[0039] Figure 6 It is a control block diagram of the third controller

[0040] In the figure: 3. Third controller, 8. Third comparator, 9. Third PI controller.

[0041] Figure 7 Block diagram of modulation unit a

[0042] In the figure: 10. Modulation unit a, 14. Fourth comparator, 15. Logical operation e.

[0043] Figure 8 Block diagram of modulation unit b

[0044] In the figure: 11. Modulation unit b, 16. Fifth comparator, 17. Logical operation f.

[0045] Figure 9 Block diagram of modulation unit c

[0046] In the figure: 12. Modulation unit c, 18. Sixth comparator, 19. Logical operation g.

[0047] Figure 10 Block diagram of modulation unit d

[0048] In the figure: 13. Modulation unit d, 20. Seventh comparator, 21. Logical operation h.

[0049] Figure 11 For SOC bat1 Greater than SOC bat2 , SOC bat3 Energy balance effect diagram

[0050] In the figure: -- is the SOC of the first single battery bat1, - is the SOC of the second single battery bat2, ... is the SOC of the third single battery bat3; the horizontal axis is time in seconds, and the vertical axis is the battery state of charge SOC. DETAILED DESCRIPTION

[0051] The technical solution of the present invention is described clearly and completely below in conjunction with the embodiments and drawings.

[0052] Example 1

[0053] The schematic diagram of the battery pack equalization circuit of the present invention is shown in FIG. Figure 1 , used to achieve battery pack cell energy balancing.

[0054] The circuit diagram of the three-cell centralized equalizer of the present invention is shown in FIG. Figure 2 The first switch tube S1 to the fourth switch tube S4 are all MOS tubes, and the first balancing inductor L 12 , the second balancing inductor L 23 10μH is selected for both.

[0055] A three-cell centralized equalizer control algorithm of the present invention performs closed-loop control on the state of charge of three cells. The control algorithm steps are as follows:

[0056] Step 1: Initialization: The operator sets the following parameter values ​​in the balancing controller according to system requirements:

[0057] (1) The control coefficient of the first PI controller 5 is k p1 and k i1 , k p1 、k i1 Take 30 and 1e-5 respectively;

[0058] (2) The control coefficient of the second PI controller 7 is k p2 and k i2 , k p2 、k i2 Take 30 and 1e-5 respectively;

[0059] (3) The control coefficient of the third PI controller 9 is k p3 and k i3 , k p3 、k i3 Take 30 and 1e-5 respectively;

[0060] Step 2: Use Hall sensors to sample the voltage and current of the first single cell bat1, the second single cell bat2, and the third single cell bat3;

[0061] Step 3: Estimate the state of charge of the first single cell bat1, the second single cell bat2, and the third single cell bat3 according to the battery state of charge estimation link to obtain SOC bat1 , SOC bat2 , SOC bat3 , SOC avg The initial values ​​of the SOC of the first single battery bat1, the second single battery bat2, and the third single battery bat3 are 0.885, 0.83, and 0.85 respectively. avg is 0.855;

[0062] Step 4: The first controller 1, the second controller 2, and the third controller 3 execute the following steps:

[0063] (1) The first comparator 4 calculates the input value of the first PI controller 5, the initial value of which is -0.03;

[0064] (2) The first PI controller 5 performs calculations after receiving the output of the first comparator 4 and outputs the corresponding control quantity U bat1 , the control cycle is 10ms, after the first control cycle, U bat1is -0.9;

[0065] (3) The second comparator 6 calculates the input value of the second PI controller 7, the initial value of which is 0.0255;

[0066] (IV) The second PI controller 7 performs calculations after receiving the output of the second comparator 6 and outputs the corresponding control quantity U bat2 , the control cycle is 10ms, after the first control cycle, U bat2 is 0.765;

[0067] (5) The third comparator 8 calculates the input value of the third PI controller 9, the initial value of which is 0.005;

[0068] (VI) The third PI controller 9 performs calculations after receiving the output of the third comparator (8) and outputs the corresponding control quantity. The control cycle is 10ms. After the first control cycle, U bat3 is 0.015;

[0069] Step 5: Modulation unit a10, modulation unit b11, modulation unit c12, and modulation unit d13 perform the following steps:

[0070] (1) U bat1 As the reference wave of the fourth comparator 14, the symmetrical triangle wave U with zero phase shift ref1 as a carrier of the fourth comparator 14;

[0071] (2) After the logic operation e15, the driving signal PWM1 of the first switch tube S1 is obtained: U batl is -0.9, PWM1 is 1;

[0072] (3) U bat2 As the reference wave of the fifth comparator 16, the symmetrical triangle wave U ref2 As the carrier of the fifth comparator 9;

[0073] (IV) After the logic operation f17, the driving signal PWM2 of the second switch tube S2 is obtained: bat2 is 0.765, PWM2 is 0;

[0074] (5)U bat3 As the reference wave of the sixth comparator 18, the symmetrical triangle wave U ref3 as a carrier of the sixth comparator (18);

[0075] (6) After the logic operation g19, the driving PWM3 of the third switch tube S3 is obtained: U bat3 is 0.015, PWM3 is 0;

[0076] (seven) SOC bat2 , min(SOC bat1 , SOC bat2 , SOC bat3 ) as the input of the seventh comparator 20, the state of charge of the second single battery bat2 is less than the first single battery bat1, the third single battery bat3, deltaSOC = 0;

[0077] (eight) After the logic operation h21, the fourth switch tube S4 drive PWM4 is obtained, PWM4 is 0.

[0078] The modulation unit a, modulation unit b, modulation unit c and modulation unit d block diagram are respectively shown as Figures 7-10 . Figure 7 The modulation unit a block diagram, U ref1 is a 100Hz triangle wave, through the comparator and logic operation unit to obtain the first switch tube S1 drive signal; Figure 8 The modulation unit b block diagram, U ref2 is a 100Hz triangle wave, phase lag U ref1 120 degrees, through the comparator and logic operation unit to obtain the second switch tube S2 drive signal; Figure 9 The modulation unit c block diagram, U ref2 is a 100Hz triangle wave, phase lag U ref1 240 degrees, through the comparator and logic operation unit to obtain the third switch tube S3 drive signal; Figure 10 The modulation unit d block diagram, through the judgment of the middle of the battery is the smallest energy to determine the fourth switch tube S4 drive signal, the second single battery bat2 is the smallest energy, the fourth switch tube S4 drive signal PWM4 is 0.

[0079] The energy balance effect diagram of three single batteries is shown as Figure 11 , after the energy balance, the energy difference of three single batteries is less than 1e-4.

Claims

1. A three-cell centralized equalizer control algorithm, characterized in that: The control algorithm performs closed-loop control on the state of charge of the three single cells. The control algorithm steps are as follows: Step 1: Initialization: The operator sets the following parameter values ​​in the balancing controller according to system requirements: (1) The control coefficient of the first PI controller (5) is k p1 and k i1 , 0<k p1 <100,0<k i1 <100; (2) The control coefficient of the second PI controller (7) is k p2 and k i2 , 0<k p2 <100,0<k i2 <100; (3) The control coefficient of the third PI controller (9) is k p3 and k i3 , 0<k p3 <100,0<k i3 <100; Step 2: Use Hall sensors to sample the voltage and current of the first single battery bat1, the second single battery bat2, and the third single battery bat3; Step 3: Estimate the state of charge of the first single battery bat1, the second single battery bat2, and the third single battery bat3 according to the battery state of charge estimation link to obtain SOC bat1 , SOC bat2 , SOC bat3 , and calculate SOC avg :SOC avg =(SOC bat1 +SOC bat2 +SOC bat3 ) / 3; Step 4: The first controller (1), the second controller (2) and the third controller (3) execute the following steps: (1) The first comparator (4) calculates the input value of the first PI controller (5): SOC avg -SOC bat1 ; (2) The first PI controller (5) performs calculation after receiving the output of the first comparator (4) and outputs the corresponding control quantity U bat1 :k p1 (SOC avg -SOC bat1 )+k i1 ∫(SOC avg -SOC bat1 )dt; (3) The second comparator (6) calculates the input value of the second PI controller (7): SOC avg -SOC bat2 ; (IV) The second PI controller (7) performs calculation after receiving the output of the second comparator (6) and outputs the corresponding control quantity U bat2 :k p2 (SOC avg -SOC bat2 )+k i2 ∫(SOC avg -SOC bat2 )dt; (5) The third comparator (8) calculates the input value of the third PI controller (9): SOC avg -SOC bat3 ; (6) The third PI controller (9) performs calculation after receiving the output of the third comparator (8) and outputs the corresponding control quantity U bat3 :k p3 (SOC avg -SOC bat3 )+k i3 ∫(SOC avg -SOC bat3 )dt; Step 5: Modulation unit a (10), modulation unit b (11), modulation unit c (12), and modulation unit d (13) perform the following steps: (1) U bat1 As the reference wave of the fourth comparator (14), the symmetrical triangle wave U with zero phase shift ref1 as a carrier of a fourth comparator (14); (2) After the logic operation e(15), the driving signal PWM1 of the first switch tube (S1) is obtained: when U bat1 -U ref1 >0, PWM1 is 0; otherwise it is 1; (3) U bat2 As the reference wave of the fifth comparator (16), the symmetrical triangle wave U ref2 as a carrier of the fifth comparator (9); (IV) After the logic operation f(17), the driving signal PWM2 of the second switch tube (S2) is obtained: bat2 -U ref2 >0, PWM2 is 0; otherwise it is 1; (5)U bat3 As the reference wave of the sixth comparator (18), the symmetrical triangle wave U ref3 as a carrier of the sixth comparator (18); (VI) After the logic operation g(19), the driving PWM3 of the third switch tube (S3) is obtained: when U bat3 -U ref3 >0, PWM3 is 0; otherwise it is 1; (7) SOC bat2 、min(SOC bat1 , SOC bat2 , SOC bat3 ) as the input of the seventh comparator (20), when the state of charge of the second single battery bat2 is less than that of the first single battery bat1 and the third single battery bat3, deltaSOC is 0; Otherwise, 1; deltaSOC=SOC bat2 -min(SOC bat1 ,SOC bat2 ,SOC bat3 ); (VIII) After the logic operation h (21), the driving PWM4 of the fourth switch tube (S4) is obtained. When deltaSOC=0, PWM4 is 0; otherwise, it is 1.

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