Driving circuit and power supply chip

Abstract

The application provides a driving circuit and a power supply chip, and relates to the technical field of electronic circuits.The driving circuit comprises a control circuit and a driving module connected with the control circuit, wherein the driving module comprises multiple-stage driving units arranged in parallel;the output end of each-stage driving unit is connected with the gate of a first switch tube; the control circuit is used for acquiring a monitoring signal of the power supply chip, performing logical processing based on the monitoring signal, driving the multiple-stage driving units, and controlling the conduction state of the first switch tube; the driving circuit and the power supply chip can realize fine control of the first switch tube in combination with the load and the like during the control of the conduction state of the first switch tube, are self-adaptive to the load, avoid the burning of the chip caused by the simultaneous conduction of the first switch tube and a second switch tube, and prevent the chip from being damaged, thereby improving the safety of the circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a driving circuit and a power supply chip. Background Technology

[0002] In high-voltage DC-DC power conversion chips, in order to reduce area costs, the upper transistor is usually an N-type MOSFET. In addition, in order to drive the upper transistor, the power supply for the upper transistor is often an external charge pump. The driving unit for the lower transistor is separate from that of the upper transistor. Therefore, in some cases, the upper and lower transistors may be turned on at the same time. In severe cases, this can burn out the chip and cause irreversible damage.

[0003] There is currently no effective solution to the problem of chip burnout and damage. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a driving circuit and a power chip to alleviate the above-mentioned technical problems.

[0005] In a first aspect, embodiments of the present invention provide a driving circuit applied to a power supply chip. The power supply chip includes a first switching transistor and a second switching transistor, which are connected in series, and a first connection node is formed on the series path of the first and second switching transistors. The driving circuit is connected to the gate of the first switching transistor and is used to drive the first switching transistor. The driving circuit includes a control circuit and a driving module connected to the control circuit. The driving module includes multiple driving units arranged in parallel. The output terminal of each driving unit is connected to the gate of the first switching transistor. The control circuit is used to acquire monitoring signals of the power supply chip, perform logic processing based on the monitoring signals to drive the driving module, and thereby control the conduction state of the first switching transistor. The monitoring signals include a load monitoring signal, a Miller plateau monitoring signal, and an SW potential monitoring signal.

[0006] In conjunction with the first aspect, the present invention provides a first possible implementation of the first aspect, wherein the driving unit includes a first driving unit, a second driving unit, and a third driving unit arranged in parallel; wherein the driving terminals of the first driving unit and the third driving unit are connected to the control circuit; the second driving unit is configured with a driving transistor group, the driving transistor group being used to maintain the entire driving process of the second driving unit.

[0007] In conjunction with the first possible implementation of the first aspect, this embodiment of the invention provides a second possible implementation of the first aspect, wherein the first driving unit includes a first driving MOS transistor; the gate of the first driving MOS transistor is connected to the control circuit; the source of the first driving MOS transistor is connected to the first connection node; and the drain of the first driving MOS transistor is connected to the gate of the first switching transistor.

[0008] In conjunction with the second possible implementation of the first aspect, this embodiment of the invention provides a third possible implementation of the first aspect, wherein the control circuit includes a Miller platform monitoring circuit; the input terminal of the Miller platform monitoring circuit is used to acquire a start signal, and drive the first driving MOS transistor based on the start signal and the monitored Miller platform monitoring signal.

[0009] In conjunction with the first possible implementation of the first aspect, this embodiment of the invention provides a fourth possible implementation of the first aspect, wherein the third driving unit includes a second driving MOS transistor; the gate of the second driving MOS transistor is connected to the control circuit; the source of the second driving MOS transistor is connected to the first connection node; and the drain of the second driving MOS transistor is connected to the gate of the first switching transistor.

[0010] In conjunction with the fourth possible implementation of the first aspect, this embodiment of the invention provides a fifth possible implementation of the first aspect, wherein the control circuit includes a first threshold monitoring circuit and a second threshold monitoring circuit; wherein the output terminals of the first threshold monitoring circuit and the second threshold monitoring circuit are connected to the gate of the second driving MOS transistor via an OR gate; the first threshold monitoring circuit is used to monitor the SW potential of the first connection node, and when the SW potential is lower than a preset threshold voltage, it sends a drive signal to the gate of the second driving MOS transistor; the second threshold monitoring circuit is used to monitor a load monitoring signal, and sends a drive signal to the gate of the second driving MOS transistor based on the load monitoring signal.

[0011] In conjunction with the first possible implementation of the first aspect, this embodiment of the invention provides a sixth possible implementation of the first aspect, wherein the second driving unit includes a third driving MOS transistor; the driving transistor group includes a first inverter and a second inverter connected in series; wherein the third driving MOS transistor constitutes a part of the second inverter.

[0012] In conjunction with the sixth possible implementation of the first aspect, this embodiment of the invention provides a seventh possible implementation of the first aspect, wherein the above-mentioned driving transistor group further includes a fourth driving MOS transistor, and the fourth driving MOS transistor and another part of the second inverter constitute a current mirror.

[0013] Secondly, embodiments of the present invention also provide a power chip, the power chip including a first switching transistor and a second switching transistor, the first switching transistor and the second switching transistor being connected in series, and a first connection node being formed on the series path of the first switching transistor and the second switching transistor; the first switching transistor is configured with the driving circuit described in the first aspect; the output terminal of the driving circuit is connected to the gate of the first switching transistor; the second switching transistor is configured with a second driving circuit, and the output terminal of the second driving circuit is connected to the gate of the second switching transistor.

[0014] In conjunction with the second aspect, the embodiments of the present invention provide a first possible implementation of the second aspect, wherein both the first switching transistor and the second switching transistor are configured with parasitic diodes.

[0015] The embodiments of the present invention bring the following beneficial effects:

[0016] The driving circuit and power chip provided in this embodiment of the invention are as follows: the driving circuit is connected to the gate of a first switching transistor and is used to drive the first switching transistor; the driving circuit includes a control circuit and a driving module connected to the control circuit, the driving module further including multiple driving units arranged in parallel; the output terminal of each driving unit is connected to the gate of the first switching transistor; the control circuit is used to acquire monitoring signals from the power chip, perform logic processing based on the monitoring signals to drive the multiple driving units, thereby controlling the conduction state of the first switching transistor; and the monitoring signals include load monitoring signals, Miller plateau monitoring signals, and SW potential monitoring signals, so that in the process of controlling the conduction state of the first switching transistor, the first switching transistor can be precisely controlled in combination with load and other conditions, and the load conditions can be adapted to avoid the chip burning and damage caused by the simultaneous conduction of the first and second switching transistors, thereby improving the safety of the circuit.

[0017] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a power supply chip provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the working waveform of a power chip provided in an embodiment of the present invention;

[0022] Figure 3 A circuit diagram of a driving circuit provided in an embodiment of the present invention;

[0023] Figure 4 A circuit diagram of a driving circuit provided in an embodiment of the present invention;

[0024] Figure 5 A timing diagram provided for an embodiment of the present invention;

[0025] Figure 6 Another timing diagram provided for an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] In the field of power supply chips, such as DC-DC power conversion chips, to reduce area costs, the upper transistor is usually an N-type MOSFET. Furthermore, the driving power supply for the upper transistor is typically a floating source of an external charge pump capacitor. For example, a 100nF capacitor is placed between the BOOT and SW points. This capacitor charges during the lower transistor's conduction cycle and serves as the driving power supply for the upper transistor during its conduction cycle. Moreover, the power supplies for driving the lower transistor and the upper transistor are separate. During the minimum conduction time or during startup when the output voltage is at the preset voltage, the upper transistor's power supply voltage cannot be replenished in time, resulting in a lower voltage value than the lower transistor's. The time it takes for the SW point to drop from high to low is determined by the upper transistor's turn-off, the load, and the lower transistor's conduction. For instance, when the load is heavy, the SW point will be discharged by the load capacitor after the upper transistor turns off. Furthermore, the discharge time varies with the load. When the load current is relatively small, the SW point cannot discharge within the dead time period, so the pull-down is achieved by the conduction of the lower transistor. Considering efficiency factors, the conduction speed of the lower transistor is generally set to be relatively fast, so the potential drop rate of the SW point is also relatively fast. For example, when the power supply of the upper transistor is only 2.5V and the power supply of the lower transistor is 5V, the pull-down capability of the upper transistor is relatively weak. Therefore, during the rapid drop of the potential of the SW point, the voltage difference between the gate HG of the upper transistor and the SW point will be coupled out. When the coupled voltage exceeds the threshold voltage Vth of the upper transistor, there is a risk that both the upper and lower transistors will conduct simultaneously. At this time, there is a direct path between the input of the power chip and ground VIN-GND. If this current exceeds the withstand capacity of the upper and lower transistors, it will directly burn out the chip and damage it.

[0028] Based on this, the driving circuit and power chip provided in this embodiment of the invention can effectively alleviate the above-mentioned technical problems.

[0029] To facilitate understanding of this embodiment, a driving circuit disclosed in this embodiment of the invention will first be described in detail.

[0030] In one possible implementation, the present invention provides a driving circuit. Specifically, the driving circuit in the present invention is applied to a power chip, such as a DC-DC power conversion chip, etc. Specifically, the power signal includes a first switch and a second switch, the first switch and the second switch are connected in series, and a first connection node is formed on the series path of the first switch and the second switch.

[0031] In this embodiment of the invention, the driving circuit is connected to the gate of the first switching transistor and is used to drive the first switching transistor; furthermore, the second switching transistor is equipped with a second driving circuit, the output terminal of which is connected to the gate of the second switching transistor, and the second driving circuit is used to drive the second switching transistor.

[0032] For ease of understanding, Figure 1A schematic diagram of a power supply chip is shown. In this embodiment of the invention, a DC-DC power conversion chip is used as an example for illustration.

[0033] Specifically, such as Figure 1 As shown, the power chip includes a first switching transistor HS and a second switching transistor LS, which are connected in series. The first connection node on the series path of the first and second switching transistors is called point SW, and the potential at this point is called the SW potential.

[0034] in, Figure 1 The first switching transistor in the circuit is also called the upper power transistor or the upper transistor, and the second switching transistor is also called the lower power transistor or the lower transistor. Furthermore, in this embodiment of the invention, the first and second switching transistors are N-type MOS transistors as an example for explanation. The aforementioned driving circuit and second driving circuit in this embodiment of the invention are set in... Figure 1 The Drive control circuit is used to drive the first and second switching transistors.

[0035] Specifically, Figure 1 The diagram also shows an inductor L1, with the source of the first switch HS and the drain of the second switch LS connected to each other and to the first terminal of the inductor L1, forming the first connection node SW described above in this embodiment. A drive control circuit, Driver, is connected to the gates of the first switch HS and the second switch LS, and is used to drive the switching timing of the first switch HS and the second switch LS. Further... Figure 1 In the power chip shown, both the first and second switching transistors are equipped with parasitic diodes, i.e. Figure 1 The diodes D1 and D2 in the diagram are parasitic diodes, also known as body diodes.

[0036] based on Figure 1 The power chip shown is actually a synchronous buck switching power supply DC-DC power conversion chip.

[0037] When the synchronous buck switching power supply DC-DC converter is packaged inside the chip, a first parasitic inductance and a second parasitic inductance are generated. The first parasitic inductance includes the parasitic inductance Lvin generated by the chip's VIN pin package and the parasitic inductance Lvinpcb generated by the PCB board. Correspondingly, the second parasitic inductance includes the parasitic inductance Lgnd generated by the chip's GND pin package and the parasitic inductance Lgndpcb generated by the PCB board.

[0038] It should be understood that Figure 1 Only a partial circuit diagram of the power chip is shown. The circuit diagrams of other parts of the power chip can be set according to the actual use situation, and the embodiments of the present invention do not impose any restrictions on this.

[0039] In specific implementation, based on Figure 1 The power supply chip shown has the following waveform diagram for its periodic operation: Figure 2 As shown, the start-up signals HSON and LSON of the upper transistor HS and the lower transistor LS, the potential waveform changes at point SW, the current IL changes on inductor L1, and the input VIN of the power supply chip are shown respectively.

[0040] To prevent the upper and lower transistors from punching through, a dead time is required. During the dead time, the body diode D1 of the lower transistor will freewheel inductor current. After the dead time ends, the first switching transistor HS turns on, and the inductor current is provided by the VIN capacitor. At this time, a sudden current will be generated, causing a voltage surge across VIN. The surge voltage V = L * di / dt, L = Lvinpcb + Lvin. As can be seen from the expression, when the package and PCB are fixed, the parasitic inductance Lvinpcb + Lvin is fixed; that is, the value of the first parasitic inductance is fixed. The switching speed of the upper transistor HS determines the slope di / dt of the inductor current change, and also determines the amplitude of the voltage surge. If the amplitude of the voltage surge is too high, it will cause overvoltage damage to the power transistor. Therefore, there is a trade-off between the switching speed and the safe range of the power transistor.

[0041] In this embodiment of the invention, the driving circuit of this embodiment is used to drive the upper transistor, thereby achieving the above balance.

[0042] Specifically, Figure 3 A circuit diagram of a driving circuit is shown, such as... Figure 3 As shown, the driving circuit in this embodiment of the invention includes: a control circuit 10, and a driving module 20 connected to the control circuit 10. The driving module 20 includes multiple driving units 201 arranged in parallel; the output terminal of each driving unit 201 is connected to the gate of the first switching transistor HS.

[0043] The control circuit is used to acquire the monitoring signal of the power chip, perform logic processing based on the monitoring signal to drive the drive module, and then control the conduction state of the first switch transistor; wherein, the monitoring signal in the embodiment of the present invention includes: load monitoring signal, Miller platform monitoring signal and SW potential monitoring signal.

[0044] The driving circuit provided in this embodiment of the invention is connected to the gate of a first switching transistor and is used to drive the first switching transistor. The driving circuit includes a control circuit and a driving module connected to the control circuit. The driving module further includes multiple driving units arranged in parallel. The output terminal of each driving unit is connected to the gate of the first switching transistor. The control circuit acquires monitoring signals from the power chip, performs logic processing based on the monitoring signals to drive the multiple driving units, thereby controlling the conduction state of the first switching transistor. The monitoring signals include load monitoring signals, Miller plateau monitoring signals, and SW potential monitoring signals. This allows for precise control of the first switching transistor in conjunction with load conditions during the control of its conduction state, and adapts to load conditions, preventing chip burnout and damage caused by simultaneous conduction of the first and second switching transistors, thus improving circuit safety.

[0045] In practical use, the multi-stage driving unit in this embodiment of the invention includes a first driving unit, a second driving unit, and a third driving unit arranged in parallel; that is, in this embodiment of the invention, the first driving unit, the second driving unit, and the third driving unit realize three-stage driving of the first switching transistor.

[0046] The first and third drive units are connected to the control circuit; the second drive unit is equipped with a drive transistor group, which is used to maintain the entire drive process of the second drive unit.

[0047] For ease of understanding, Figure 3 On this basis, Figure 4 A circuit diagram of a driving circuit is shown, wherein, Figure 4 The diagram shows a first switch HS and a second switch LS, body diodes D1 and D2 of the first switch HS and the second switch LS, a drive circuit for the first switch HS and a second drive circuit for the second switch LS.

[0048] Specifically, such as Figure 4 As shown, the first driving unit in this embodiment of the invention includes a first driving MOS transistor M1, the gate of which is connected to a control circuit; the source of which is connected to a first connection node SW; and the drain of which is connected to the gate of a first switching transistor.

[0049] Furthermore, in order to drive the first driving MOS transistor, the control circuit in this embodiment of the invention includes a Miller plateau monitoring circuit; the input terminal of the Miller plateau monitoring circuit is used to acquire a start signal, and the first driving MOS transistor is driven based on the start signal and the monitored Miller plateau monitoring signal.

[0050] Furthermore, such as Figure 4 As shown, the third driving unit in this embodiment of the invention includes a second driving MOS transistor M2; the gate of the second driving MOS transistor M2 is connected to the control circuit; the source of the second driving MOS transistor M2 is connected to the first connection node; and the drain of the second driving MOS transistor M2 is connected to the gate of the first switching transistor.

[0051] Furthermore, the control circuit also includes a drive control section corresponding to the second driving MOS transistor M2. This drive control section includes a first threshold monitoring circuit and a second threshold monitoring circuit. The output terminals of the first threshold monitoring circuit and the second threshold monitoring circuit are connected to the gate of the second driving MOS transistor M2 through an OR gate. The first threshold monitoring circuit is used to monitor the SW potential of the first connection node. When the SW potential is lower than a preset threshold voltage, a drive signal is sent to the gate of the second driving MOS transistor. The second threshold monitoring circuit is used to monitor the load monitoring signal and send a drive signal to the gate of the second driving MOS transistor based on the load monitoring signal.

[0052] Furthermore, such as Figure 4 As shown, the second driving unit in this embodiment of the invention includes a third driving MOS transistor M3; and the driving transistor group includes a first inverter and a second inverter connected in series; wherein, the third driving MOS transistor M3 can also be part of the second inverter. Furthermore, the driving transistor group configured in the second driving unit also includes a fourth driving MOS transistor M4, which, together with another part of the second inverter, forms a current mirror.

[0053] Specifically, Figure 4 In the diagram, the dashed lines 31 and 32 represent the first and second inverters, respectively. Each inverter consists of two MOSFETs connected in series. For specific connection details, see [link to diagram]. Figure 4 As shown.

[0054] based on Figure 4 The driving circuit shown, Figure 5 A timing diagram is also shown. To maximize efficiency when controlling the turn-off process of the first switch, a three-stage drive can be used. The first stage of drive ends when the voltage difference between the gate HG potential of the first switch HS and the SW potential drops to near the threshold voltage Vth of the first switch HS. The second stage of drive is mainly used to control the speed at which the SW potential drops to the ground GND potential. The third stage of drive turns on only when the SW potential has completely dropped to ground. When the current of the highest load increases, such as 6A or 12A, and the parasitic inductance of the power supply chip is relatively large, the switching speed of the second stage of drive determines the speed at which the SW potential drops. Therefore, the drive strength of the second stage of drive needs to be strictly controlled under heavy load conditions.

[0055] in, Figure 5In it, HG2SW represents the potential difference from the gate HG potential of the first switching transistor HS to the potential of SW, and, the potential difference from the gate LG potential of the second switching transistor LS to the ground GND is represented by LG2gnd. From Figure 5 As can be seen from the timing diagram shown in Figure 5 , the enable signal of the third-stage drive is SW < Vth (or VCC), that is, the potential of SW is less than the threshold voltage of the first switching transistor HS, and the threshold voltage of this first switching transistor HS can be represented by VCC. Further, Figure 6 Another timing diagram is also shown, which specifically shows the change process of the load monitoring signal from light load to heavy load, and, Figure 6 The load monitoring signal LOAD_DET is also shown in it, as Figure 6 shown. In the case of light load, the potential of SW drops slowly. During the dead time, a complete drop to the ground GND cannot be achieved. At this time, if you want to complete the drop of the potential of SW to the ground, you need to rely on the conduction of the lower transistor to achieve the pull-down; because the potential of SW fails to complete the drop to the ground during the second-stage drive process, the enable signal of the third-stage drive cannot play a role; at this time, if the power supply VIN of the first switching transistor HS is at a relatively low moment, the potential difference from the gate HG of the first switching transistor HS to the SW point will be coupled and opened during the drop of the potential of SW, resulting in the phenomenon of simultaneous breakdown of the upper and lower transistors.

[0056] Based on the three-stage drive method in the embodiment of the present invention, in the case of per-cycle load current detection, when the load monitoring signal indicates that the load current is too small to support the drop of the potential of SW before the dead time, a light load signal will be generated to represent the load level; at this time, the potential difference from the gate HG of the upper transistor to the SW point is monitored at the same time. When the potential difference from the gate HG of the upper transistor to the SW point drops to a certain value, such as 10% of the power supply voltage, a corresponding light load monitoring signal will be generated. When the light load signal and the light load monitoring signal are monitored at the same time, the third-stage enable signal will be triggered, that is, the third-stage drive is performed.

[0057] Therefore, based on Figure 4 the drive circuit shown in Figure 4 , the drive of the first switching transistor, that is, the upper transistor, is actually divided into three-stage drive, that is Figure 4 the 1st, 2nd, and 3rd in Figure 4 . The first-stage drive l st can be turned on when the start signal comes and stops until the Miller plateau is detected at the falling edge of the potential difference from the gate HG of the upper transistor to the SW point; the second-stage drive 2nd will be maintained throughout the entire drive process due to the existence of the drive transistor group; the start of the third-stage drive can be enabled by two branches: the first branch is the SW < Vth threshold monitoring, which is preferentially effective in the case of heavy load; the other branch is the threshold monitoring of the potential difference from the gate HG of the upper transistor to the SW point < Vth, which is controlled by the load monitoring signal Light-load, that is, when the load is lighter, the monitoring path of the potential difference from the gate HG of the upper transistor to the SW point is started to start the third-stage drive.

[0058] The load monitoring signal is implemented by the corresponding load detection circuit. The specific load detection circuit can be set according to the actual load connection situation, and the embodiments of the present invention do not limit it.

[0059] further, Figure 4 In addition to the aforementioned three-stage driving circuit, it also includes a second driving circuit for driving the second switching transistor, that is, Figure 4 In the second driving circuit, the circuit including the VCC section is connected to the gate of the second switching transistor. The specific implementation of the second driving circuit can be set according to the actual use situation, and the embodiments of the present invention do not limit it.

[0060] further, Figure 4 The control circuit shown includes a Miller platform monitoring circuit, a first threshold monitoring circuit, and a second threshold monitoring circuit. It should be understood that... Figure 4 The control circuit shown is only a part of the functional circuit used in the embodiments of the present invention. In other embodiments, the control circuit may also include other functional circuits, such as comparators, flip-flops, and filter circuits, etc., so as to realize the control function of the power chip. The specific function of the control circuit can be set according to the actual use situation, and the embodiments of the present invention do not limit it.

[0061] Furthermore, based on the above embodiments, this invention also provides a power supply chip, which can be referenced... Figure 1 The schematic diagram of the power chip shown includes a first switching transistor and a second switching transistor, which are connected in series, and a first connection node is formed on the series path of the first switching transistor and the second switching transistor.

[0062] The first switching transistor is equipped with the aforementioned driving circuit; the output terminal of the driving circuit is connected to the gate of the first switching transistor; the second switching transistor is equipped with a second driving circuit, the output terminal of which is connected to the gate of the second switching transistor. Furthermore, both the first and second switching transistors are equipped with parasitic diodes.

[0063] The power chip provided in this embodiment of the invention has the same technical features as the driving circuit provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0064] The computer program product of the driving circuit and power chip provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation, please refer to the method embodiments, which will not be repeated here.

[0065] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the power chip described above can be referred to the corresponding process in the foregoing embodiments, and will not be repeated here.

[0066] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0067] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0068] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0069] Finally, it should be noted that the above embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A driving circuit, characterized in that, The power chip is used in a power supply chip, which includes a first switching transistor and a second switching transistor, the first switching transistor and the second switching transistor are connected in series, and a first connection node is formed on the series path of the first switching transistor and the second switching transistor. The driving circuit is connected to the gate of the first switching transistor and is used to drive the first switching transistor. The driving circuit includes: a control circuit, and a driving module connected to the control circuit. The driving module includes multiple driving units arranged in parallel. The output terminal of each driving unit is connected to the gate of the first switching transistor. The control circuit is used to acquire the monitoring signal of the power chip, perform logic processing based on the monitoring signal to drive the drive module, and thereby control the conduction state of the first switch; wherein, the monitoring signal includes: load monitoring signal, Miller platform monitoring signal and SW potential monitoring signal.

2. The driving circuit according to claim 1, characterized in that, The drive unit includes a first drive unit, a second drive unit, and a third drive unit arranged in parallel. The driving terminals of the first driving unit and the third driving unit are connected to the control circuit. The second drive unit is equipped with a drive transistor group, which is used to maintain the entire drive process of the second drive unit.

3. The driving circuit according to claim 2, characterized in that, The first driving unit includes a first driving MOS transistor; The gate of the first driving MOS transistor is connected to the control circuit; The source of the first driving MOS transistor is connected to the first connection node; The drain of the first driving MOS transistor is connected to the gate of the first switching transistor.

4. The driving circuit according to claim 3, characterized in that, The control circuit includes a Miller platform monitoring circuit; The input terminal of the Miller platform monitoring circuit is used to acquire a start signal, and the first driving MOS transistor is driven based on the start signal and the monitored Miller platform monitoring signal.

5. The driving circuit according to claim 2, characterized in that, The third driving unit includes a second driving MOS transistor; The gate of the second driving MOS transistor is connected to the control circuit; The source of the second driving MOS transistor is connected to the first connection node; The drain of the second driving MOS transistor is connected to the gate of the first switching transistor.

6. The driving circuit according to claim 5, characterized in that, The control circuit includes a first threshold monitoring circuit and a second threshold monitoring circuit; The output terminals of the first threshold monitoring circuit and the second threshold monitoring circuit are connected to the gate of the second driving MOS transistor via an OR gate. The first threshold monitoring circuit is used to monitor the SW potential of the first connection node. When the SW potential is lower than the preset threshold voltage, a drive signal is sent to the gate of the second driving MOS transistor. The second threshold monitoring circuit is used to monitor the load monitoring signal and send a drive signal to the gate of the second driving MOS transistor based on the load monitoring signal.

7. The driving circuit according to claim 2, characterized in that, The second driving unit includes a third driving MOS transistor; The drive transistor group includes a first inverter and a second inverter connected in series; The third driving MOS transistor forms part of the second inverter.

8. The driving circuit according to claim 7, characterized in that, The driving transistor group also includes a fourth driving MOS transistor, which, together with another part of the second inverter, forms a current mirror.

9. A power supply chip, characterized in that, The power chip includes a first switch and a second switch, which are connected in series, and a first connection node is formed on the series path of the first switch and the second switch. The first switching transistor is configured with a driving circuit as described in any one of claims 1 to 8; the output terminal of the driving circuit is connected to the gate of the first switching transistor. The second switch is equipped with a second driving circuit, and the output of the second driving circuit is connected to the gate of the second switch.

10. The power chip according to claim 9, characterized in that, Both the first and second switching transistors are equipped with parasitic diodes.

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