Voltage ripple suppression method and loop

Abstract

The application discloses a voltage ripple suppression method and a loop. The voltage ripple suppression method comprises the following steps: obtaining an output voltage of a resonance circuit or a resonance topology circuit; obtaining a voltage control signal according to the output voltage; obtaining a preset frequency jitter signal; adding the voltage control signal and the preset frequency jitter signal to obtain a control frequency of a PWM; obtaining a phase shift value of the PWM according to the preset frequency jitter signal and the output voltage; and generating the PWM to drive a switch tube according to the control frequency of the PWM and the phase shift value of the PWM, so as to suppress the output voltage ripple of the resonance circuit or the resonance topology circuit. The voltage ripple suppression method can effectively suppress the output voltage ripple when the resonance circuit is added with frequency jitter.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to a voltage ripple suppression method and a loop. BACKGROUND

[0002] The conventional LLC (resonant circuit) generally works in a frequency modulation state, that is, the size of the output voltage is controlled by adjusting the switching frequency of the switching tube. After stable operation, the switching frequency is stable, and since the frequency of the LLC is relatively high, the interference caused by the frequency when testing EMI (Electromagnetic Interference) will affect the test results. If the frequency jitter is added, the output voltage of the LLC will jitter, making the output voltage ripple larger, which does not meet the circuit indicators such as the service life of the battery. SUMMARY

[0003] Therefore, the embodiments of the present application provide a voltage ripple suppression method and a loop to solve the problem of excessive output voltage ripple when frequency jitter is added to the resonant circuit.

[0004] In a first aspect, the embodiments of the present application provide a voltage ripple suppression method applied to a resonant circuit or a resonant topology circuit, and the method comprises the following steps.

[0005] Obtaining an output voltage of the resonant circuit or the resonant topology circuit;

[0006] Obtaining a voltage control signal according to the output voltage;

[0007] Obtaining a preset frequency jitter signal;

[0008] Adding the voltage control signal and the preset frequency jitter signal to obtain a control frequency of a PWM (Pulse Width Modulation);

[0009] Obtaining a phase shift value of the PWM according to the preset frequency jitter signal and the output voltage;

[0010] Generating the PWM to drive a switching tube according to the control frequency of the PWM and the phase shift value of the PWM, so as to suppress the output voltage ripple of the resonant circuit or the resonant topology circuit.

[0011] The aspects and any possible implementation ways described above further provide an implementation way, wherein the voltage control signal is obtained according to the output voltage, and the implementation way comprises the following steps.

[0012] Obtaining a voltage setting instruction issued by an upper computer;

[0013] Obtaining a voltage reference value according to the voltage setting instruction;

[0014] subtracting the output voltage from the voltage reference value to obtain a voltage error value;

[0015] inputting the voltage error value into a voltage loop controller to obtain the voltage control signal.

[0016] Aspects and any possible implementation thereof as described above further provide an implementation, wherein the obtaining the preset dithering signal comprises:

[0017] obtaining a preset dithering period;

[0018] obtaining a dithering amplitude;

[0019] obtaining the preset dithering signal according to the preset dithering period and the dithering amplitude.

[0020] Aspects and any possible implementation thereof as described above further provide an implementation, wherein the obtaining the phase shift value of the PWM according to the preset dithering signal and the output voltage comprises:

[0021] obtaining the phase shift value of the PWM according to the preset dithering period and the voltage error value.

[0022] Aspects and any possible implementation thereof as described above further provide an implementation, wherein the obtaining the phase shift value of the PWM according to the preset dithering period and the voltage error value comprises:

[0023] integrating the voltage error value on the preset dithering period by using an integrator to obtain an integral value;

[0024] multiplying the integral value by a dithering loop control coefficient to obtain the phase shift value of the PWM.

[0025] In a second aspect, the embodiments of the present application provide a voltage ripple suppression loop, which is applied to a resonant circuit or a resonant topology circuit, and the voltage ripple suppression loop comprises:

[0026] a first data processor configured to obtain an output voltage of the resonant circuit or the resonant topology circuit;

[0027] a voltage loop controller configured to obtain a voltage control signal according to the output voltage;

[0028] a dithering generator configured to obtain a preset dithering signal;

[0029] a second data processor configured to add the voltage control signal and the dithering signal to obtain a control frequency of a PWM;

[0030] a dithering ripple suppression loop configured to obtain a phase shift value of the PWM according to the preset dithering signal and the output voltage.

[0031] a PWM generation module configured to generate the PWM driving to the switch tube according to the control frequency of the PWM and the phase shift value of the PWM, so as to suppress the output voltage ripple of the resonant circuit or the resonant topology circuit.

[0032] According to the aspect and any possible implementation manner as described above, further provided is an implementation manner, and the first data processor is further configured to:

[0033] obtain a voltage setting instruction issued by a host computer;

[0034] obtain a voltage reference value according to the voltage setting instruction;

[0035] subtract the output voltage from the voltage reference value to obtain a voltage error value;

[0036] input the voltage error value into a voltage loop controller to obtain the voltage control signal through the voltage loop controller.

[0037] According to the aspect and any possible implementation manner as described above, further provided is an implementation manner, and the frequency jitter generator is further configured to:

[0038] obtain a preset frequency jitter period;

[0039] obtain a frequency jitter amplitude;

[0040] obtain the preset frequency jitter signal according to the preset frequency jitter period and the frequency jitter amplitude.

[0041] According to the aspect and any possible implementation manner as described above, further provided is an implementation manner, and the frequency jitter ripple suppression loop is further configured to:

[0042] obtain the phase shift value of the PWM according to the preset frequency jitter period and the voltage error value.

[0043] According to the aspect and any possible implementation manner as described above, further provided is an implementation manner, and the frequency jitter ripple suppression loop is further configured to:

[0044] integrate the voltage error value on the preset frequency jitter period by using an integrator to obtain an integral value;

[0045] multiply the integral value by a frequency jitter loop control coefficient to obtain the phase shift value of the PWM.

[0046] In the embodiment of the present application, first, the output voltage of the resonant circuit or resonant topology circuit is acquired, and the voltage control signal is obtained according to the output voltage, so that the resonant circuit or resonant topology circuit can output the expected voltage, and the circuit can be kept in the output constant voltage mode; then the preset frequency jitter signal is acquired, and the control frequency of the PWM is obtained by adding the preset frequency jitter signal and the voltage control signal, so as to optimize the control signal of the PWM by adding the frequency jitter signal of a specific frequency, so that the electromagnetic interference caused by the frequency of the resonant circuit or resonant topology circuit is reduced; then the phase shift value of the PWM is obtained according to the preset frequency jitter signal and the output voltage, so as to control the energy of the output voltage by using the phase shift value; finally, the control of the on or off of the switching tube is generated by the PWM drive according to the control frequency of the PWM and the phase shift value of the PWM, the energy of the output voltage is controlled by using the phase shift value of the PWM, so as to suppress the output voltage ripple. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0048] Figure 1 is a flow chart of a voltage ripple suppression method in the embodiment of the present application;

[0049] Figure 2 is a schematic diagram of a voltage ripple suppression loop in the embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to better understand the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the drawings.

[0051] It should be clear that the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0052] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0053] It should be understood that the term "and / or" as used herein merely describes associated objects in a same field, and means that three relationships can exist, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " herein generally means that the front and rear associated objects have an "or" relationship.

[0054] It should be understood that although the terms first, second, third, etc. can be used in embodiments of the present application to describe preset ranges, etc., these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from each other. For example, the first preset range can also be referred to as the second preset range, and similarly, the second preset range can also be referred to as the first preset range without departing from the scope of the embodiments of the present application.

[0055] Depending on the context, the word "if" as used herein can be interpreted to mean "when" or "while" or "in response to determining" or "in response to detecting". Similarly, the phrase "if determined" or "if detecting (a stated condition or event)" can be interpreted to mean "when determined" or "in response to determining" or "when detecting (a stated condition or event)" or "in response to detecting (a stated condition or event)", depending on the context.

[0056] Since the LLC works at a high frequency, the interference generated by the frequency when testing EMI can affect the test results. Among them, when the frequency range is controlled within the preset jitter range by adding jitter, the interference generated by the frequency when testing EMI can be effectively reduced. However, if the jitter is added, the output voltage of the LLC will be jittered, and the output voltage ripple will be larger, so the circuit will not meet the index requirements. The method of adding jitter is not suitable for application in the resonant circuit and its topology circuit at present.

[0057] The output voltage ripple refers to the power frequency AC component contained in the output DC voltage. That is, the DC voltage is originally a fixed value, but in actual scenarios, the DC voltage is often obtained by rectifying and filtering the AC voltage. Due to incomplete filtering, there will be residual AC components, and even if a battery is used for power supply, the ripple will be generated due to the fluctuation of the load.

[0058] In the present application, in view of the problem that the method of adding jitter on the resonant circuit and its topology circuit will cause the output voltage ripple of the circuit to be too large, a voltage ripple suppression method is proposed. As shown in Figure 1 Figure 1 is a flowchart of a voltage ripple suppression method in embodiments of the present application. The voltage ripple suppression method is applied to a resonant circuit or a resonant topology circuit, and specifically includes the following steps:

[0059] ​S10: Obtain an output voltage of the resonant circuit or the resonant topology circuit.

[0060] In an alternating current circuit with resistance R, inductance L and capacitance C elements, the voltage across the circuit is generally different from the phase of the current. If the parameters of the circuit elements (L or C) or the power frequency are adjusted, they can be the same phase, and the entire circuit appears to be purely resistive. The circuit reaches this state is called resonance, and the circuit that can reach the resonance state is called a resonant circuit. In the resonance state, the total impedance of the circuit reaches an extreme value or approximately reaches an extreme value. The resonant circuit can also have a circuit topology based on its circuit, called a resonant topology circuit, such as a CLLC topology based on LLC, with an additional capacitor on the secondary side, allowing bidirectional power transmission. And the secondary side of the CLLL topology increases an inductance on the basis of the CLLC, which can make the circuit structure symmetrical. In this application, the resonant circuit and the circuit topology based on it can use this voltage ripple suppression method.

[0061] In an embodiment, the output voltage of the resonant circuit or the resonant topology circuit is obtained, and the voltage reference value of the output voltage of the resonant circuit or the resonant topology circuit is controlled according to the output voltage, so that the output voltage is constant after each actual output. The output of the circuit is realized by feedback according to the difference between the voltage reference value of the output voltage.

[0062] S20: Obtain a voltage control signal according to the output voltage.

[0063] The voltage control signal refers to a signal for closed-loop loop control of the output voltage, which can be realized by adjusting the pulse width modulation (PWM) method. By adjusting the PWM, the output voltage of the resonant circuit or the resonant topology circuit changes.

[0064] S30: Obtain a preset frequency jitter signal.

[0065] The preset frequency jitter signal refers to a frequency signal within a preset jitter range. For example, the switching frequency of the resonant circuit or the resonant topology circuit is F (Hz), and the jitter range can be set to ±5 Hz. The frequency jitter signal of F±5 (Hz) is added to reduce the electromagnetic interference generated by the circuit at F frequency, which can improve the accuracy of the test electromagnetic interference.

[0066] S40: Add the voltage control signal and the preset frequency jitter signal to obtain the control frequency of the PWM.

[0067] In an embodiment, the voltage control signal is a control signal derived by a closed loop, which represents the switching frequency of the circuit when outputting the voltage. When the preset dithering signal is added, the voltage control signal and the preset dithering signal are added together as the actual switching frequency of the circuit, which is the control frequency of the PWM.

[0068] S50: obtaining the phase shift value of the PWM according to the preset dithering signal and the output voltage.

[0069] In an embodiment, the addition of the preset dithering signal causes the output voltage of the circuit to generate ripples, and a voltage error value is generated in the process of controlling the output voltage by the voltage closed loop. In this application, the voltage error value generated by the output voltage is regarded as the inevitable result of adding the dithering signal, and the energy of the voltage error value in the time domain is approximately equal to the energy of the output voltage ripple. In this embodiment, the phase shift value of the PWM is obtained according to the preset dithering signal and the output voltage, and the energy control of the output voltage ripple is realized by the phase shift value of the PWM, for example, the length of time when the output voltage is 0 in the time domain is increased to suppress the output voltage ripple.

[0070] S60: generating the PWM drive to the switch tube according to the control frequency of the PWM and the phase shift value of the PWM, so as to suppress the output voltage ripple of the resonant circuit or the resonant topology circuit.

[0071] In an embodiment, the control frequency of the PWM is the control frequency in the ideal case (assuming that no output voltage ripple is generated), and the phase shift value of the PWM is the phase shift value for controlling the energy of the output voltage in the actual case where the output voltage ripple is generated. After the combination of the two, the output voltage ripple can be suppressed to a large extent, and the energy of the output voltage ripple in the time domain is suppressed and not reflected in the output voltage.

[0072] Further, in step S20, i.e. the step of obtaining the voltage control signal according to the output voltage, the following steps are specifically included:

[0073] S21: obtaining the voltage setting instruction issued by the upper computer.

[0074] In the voltage closed loop, the circuit will accept the voltage setting instruction sent by the upper computer, so as to calculate the voltage error value according to the voltage setting instruction and realize the constant voltage output of the circuit.

[0075] S22: obtaining the voltage reference value according to the voltage setting instruction.

[0076] In an embodiment, after the circuit receives the voltage setting instruction, the corresponding voltage reference value can be obtained according to the instruction, and the voltage reference value is the expected output voltage of the circuit.

[0077] S23: subtract the output voltage from the voltage reference value to obtain a voltage error value.

[0078] In an embodiment, the actual voltage output by the circuit each time can be different from the voltage reference value. In order to make the output voltage follow the voltage reference value next time, a voltage error value is obtained by using a difference calculation method, and the voltage error value is used as feedback of the voltage closed loop to control the PWM signal.

[0079] S24: input the voltage error value into the voltage loop controller to obtain a voltage control signal.

[0080] The voltage loop controller can be a PI controller, and the voltage control signal is obtained after the calculation of the PI controller.

[0081] Further, in step S30, i.e. the step of obtaining a preset dithering frequency signal, the following steps are included:

[0082] S31: obtain a preset dithering frequency period.

[0083] In an embodiment, in order to reduce the interference caused by the frequency of the resonant circuit and the related topology circuit, a plurality of frequencies can be set within the dithering range of the switching frequency of the circuit when it is stable. Specifically, the preset dithering frequency period can be set.

[0084] S32: obtain a dithering frequency amplitude.

[0085] In an embodiment, the dithering frequency amplitude can be set according to the output voltage.

[0086] S33: obtain a preset dithering frequency signal according to the preset dithering frequency period and the dithering frequency amplitude.

[0087] It can be understood that a waveform signal needs to be determined by a period (or frequency) and an amplitude. In this application, the preset dithering frequency signal is obtained by using a trigonometric function such as sine or cosine according to the preset dithering frequency period and the dithering frequency amplitude.

[0088] Further, in step S50, i.e. the step of obtaining a phase shift value of the PWM according to the preset dithering frequency signal and the output voltage, the following steps are included:

[0089] Obtain the phase shift value of the PWM according to the preset dithering frequency period and the voltage error value.

[0090] Further, in the step of obtaining the phase shift value of the PWM according to the preset dithering frequency period and the voltage error value, the following steps are included:

[0091] S51: integrate the voltage error value on the preset dithering frequency period by using an integrator to obtain an integral value.

[0092] In an embodiment, the integral of the voltage error value in the time domain is an embodiment of the energy. The energy actually embodies the energy of the output voltage ripple, and by integrating the voltage error value in the preset dithering frequency period, the voltage ripple energy generated after adding the dithering signal can be approximately obtained.

[0093] S52: multiplying the integral value by a dithering loop control coefficient to obtain a phase shift value of the PWM.

[0094] In an embodiment, after obtaining the integral value, the integral value is multiplied by a dithering loop control coefficient to determine the phase shift value of the PWM. The dithering loop control coefficient is set in advance according to the actual parameters of the circuit and will affect the actual voltage ripple energy generated after adding the dithering signal. In the present application, the integral value is multiplied by the dithering loop control coefficient to determine the accurate voltage ripple energy, and the phase shift value of the PWM is obtained accordingly. The phase shift value of the PWM can control the output voltage, so that the output voltage corresponding to a specific phase of the PWM output waveform is 0, thereby achieving the purpose of suppressing the voltage ripple energy. In the present application, the PWM drive for the switch tube can be generated according to the control frequency of the PWM and the phase shift value of the PWM. The conduction and cutoff of the switch tube are controlled through the phase shift value of the PWM, so that the output voltage corresponding to the preset dithering frequency period in the output voltage stage is 0, so as to suppress the output voltage ripple of the resonant circuit or the resonant topology circuit.

[0095] Figure 2 FIG. 1 is a schematic diagram of a voltage ripple suppression loop in an embodiment of the present application. Figure 2 The resonant topology circuit also includes a resonant topology circuit, and the output voltage of the resonant topology circuit is taken as the input of the first data processor.

[0096] Specifically, the resonant topology circuit is a bridge bidirectional converter, which includes left and right two full-bridge circuits, and each full-bridge circuit includes four switch tubes. Among them, Uin represents the input voltage, Lr and Lm are the inductance of the left full-bridge circuit, Cr is the capacitance of the left full-bridge circuit, ir represents the current flowing through Lr, im represents the current flowing through Lm, Cf represents the capacitance of the right full-bridge circuit, R represents the load resistance, io represents the current flowing through the load resistance, and vo represents the voltage of R, that is, the output voltage of the resonant topology circuit.

[0097] The input voltage is input into the voltage ripple suppression loop. The ripple suppression loop includes a first data processor, a voltage loop controller, a dithering generator, a second data processor, a dithering ripple suppression loop, and a PWM generation module. Specifically, the execution logic of the voltage ripple suppression loop is as follows:

[0098] Step one: obtaining the output voltage vo and the voltage reference value Uoref.

[0099] Step two: calculate the voltage error value according to Uerr=Uoref-vo, and calculate the loop output value fUctrl through the loop controller.

[0100] Step three: generate the dithering signal Af according to the preset dithering period Tf and the dithering amplitude value Af.

[0101] Step four: add the dithering signal Af and the loop output value fUctrl to obtain the control frequency f of the PWM.

[0102] Step five: the dithering ripple suppression loop calculates the phase shift value phase of the PWM through the integrator according to the preset dithering period Tf and the voltage error value Uerr obtained from the output voltage vo.

[0103] Step six: the PWM generation module generates the PWM drive for the switching tube according to the control frequency f of the PWM and the phase shift value phase of the PWM.

[0104] Further, Figure 2 In the present application, the phase shift value phase obtained by calculation can determine the time when the switching tubes at the upper left corner and the upper right corner of the left full-bridge circuit are turned on, so that the voltage value in this time period becomes 0. This actually suppresses the energy of the ripple part in the output voltage, so that the output voltage ripple is not reflected in the output voltage, thereby achieving the purpose of suppressing the voltage output ripple.

[0105] In the embodiment of the present application, first, the output voltage of the resonant circuit or resonant topology circuit is obtained, and a voltage control signal is obtained according to the output voltage, so that the resonant circuit or resonant topology circuit can output the desired voltage, so that the circuit can be kept in the output constant voltage mode; then a preset dithering signal is obtained, and the control frequency of the PWM is obtained by adding the preset dithering signal and the voltage control signal, so as to optimize the control signal of the PWM by adding the dithering signal of a specific frequency, so as to reduce the electromagnetic interference caused by the frequency of the resonant circuit or resonant topology circuit; then the phase shift value of the PWM is obtained according to the preset dithering signal and the output voltage, so as to control the energy of the output voltage by using the phase shift value; finally, the PWM drive is comprehensively generated according to the control frequency of the PWM and the phase shift value of the PWM to control the conduction or cutoff of the switching tube, and the energy of the output voltage is controlled by using the phase shift value of the PWM, so as to suppress the output voltage ripple.

[0106] The application also provides a voltage ripple suppression loop applied to a resonant circuit or a resonant topology circuit, the voltage ripple suppression loop comprising:

[0107] a first data processor configured to acquire an output voltage of the resonant circuit or the resonant topology circuit;

[0108] a voltage loop controller configured to obtain a voltage control signal according to the output voltage;

[0109] a frequency jitter generator configured to acquire a preset frequency jitter signal;

[0110] a second data processor configured to add the voltage control signal and the frequency jitter signal to obtain a control frequency of a PWM;

[0111] a frequency jitter ripple suppression loop configured to obtain a phase shift value of the PWM according to the preset frequency jitter signal and the output voltage;

[0112] a PWM generation module configured to generate a PWM drive for a switch tube according to the control frequency of the PWM and the phase shift value of the PWM, so as to suppress the output voltage ripple of the resonant circuit or the resonant topology circuit.

[0113] In the application, the preset frequency jitter signal refers to a frequency signal in a preset jitter range. For example, the switching frequency of the resonant circuit or the resonant topology circuit is F (Hz), the jitter range is set as ±5 Hz, and a frequency jitter signal of F±5 (Hz) is added, so as to reduce the electromagnetic interference generated by the circuit at the frequency F, and improve the accuracy of the test electromagnetic interference.

[0114] In an embodiment, the addition of the preset frequency jitter signal causes the output voltage of the circuit to generate a ripple, and a voltage error value is generated in the process of controlling the output voltage through the voltage closed loop. In the application, the voltage error value is regarded as an inevitable result caused by the addition of the frequency jitter signal, and the energy of the voltage error value in the time domain is approximately equal to the energy of the output voltage ripple. In the embodiment, the phase shift value of the PWM is obtained according to the preset frequency jitter signal and the output voltage, and the energy of the output voltage ripple is controlled through the phase shift value of the PWM, for example, the length of time when the output voltage is 0 in the time domain is increased to suppress the output voltage ripple.

[0115] In an embodiment, the control frequency of the PWM is the control frequency in an ideal case (assuming that the output voltage ripple is not generated frequently), and the phase shift value of the PWM is the phase shift value for controlling the energy of the output voltage in an actual case where the output voltage ripple is generated frequently. The combination of the two can greatly suppress the output voltage ripple, suppress the energy of the output voltage ripple in the time domain, and not reflect the output voltage ripple in the output voltage.

[0116] Further, the first data processor is further configured to:

[0117] acquire a voltage setting instruction issued by the host computer.

[0118] acquire a voltage reference value according to the voltage setting instruction.

[0119] subtract the output voltage from the voltage reference value to obtain a voltage error value.

[0120] input the voltage error value into the voltage loop controller to obtain a voltage control signal through the voltage loop controller.

[0121] Further, the frequency jitter generator is further configured to:

[0122] acquire a preset frequency jitter period.

[0123] acquire a frequency jitter amplitude.

[0124] acquire a preset frequency jitter signal according to the preset frequency jitter period and the frequency jitter amplitude.

[0125] Further, the frequency jitter ripple suppression loop is further configured to:

[0126] acquire a phase shift value of the PWM according to the preset frequency jitter period and the voltage error value.

[0127] Further, the frequency jitter ripple suppression loop is further configured to:

[0128] integrate the voltage error value on the preset frequency jitter period by using an integrator to obtain an integral value.

[0129] In an embodiment, the integral of the voltage error value in the time domain is an embodiment of energy. The energy actually embodies the energy of the output voltage ripple. By integrating the voltage error value on the preset frequency jitter period, the voltage ripple energy generated after the frequency jitter signal is added can be approximately obtained.

[0130] multiply the integral value by a frequency jitter loop control coefficient to obtain the phase shift value of the PWM.

[0131] In an embodiment, after obtaining the integral value, multiplying the integral value with a frequency jitter loop control coefficient can determine the phase shift value of the PWM. The frequency jitter loop control coefficient is set in advance according to the actual parameters of the circuit, and will affect the actual voltage ripple energy generated after the frequency jitter signal is added. In the present application, the integral value is multiplied with the frequency jitter loop control coefficient to determine the accurate voltage ripple energy, so as to obtain the phase shift value of the PWM accordingly. The phase shift value of the PWM can control the output voltage, so that the output voltage corresponding to a specific phase of the PWM output waveform is 0, thereby achieving the purpose of suppressing the voltage ripple energy. In the present application, the calculated phase shift value can be used to generate a PWM drive for the switching tube according to the control frequency of the PWM and the phase shift value of the PWM. The on and off of the switching tube is controlled by the phase shift value of the PWM, so that the output voltage corresponding to the preset frequency jitter period of the output voltage stage is 0, thereby suppressing the output voltage ripple of the resonant circuit or the resonant topology circuit.

[0132] In the present application, the calculated phase shift value phase can determine the on time of the switching tubes at the upper left corner and the upper right corner of the left full-bridge circuit, so that the voltage value in this time period becomes 0. This actually suppresses the energy of the ripple part of the output voltage, so that the output voltage ripple is not reflected in the output voltage, thereby achieving the purpose of suppressing the voltage output ripple.

[0133] In the embodiment of the present application, first, the output voltage of the resonant circuit or the resonant topology circuit is obtained, and the voltage control signal is obtained according to the output voltage, so that the resonant circuit or the resonant topology circuit can output the desired voltage, so that the circuit can maintain in the output constant voltage mode. Then, the preset frequency jitter signal is obtained, and the control frequency of the PWM is obtained by adding the preset frequency jitter signal and the voltage control signal, so as to optimize the control signal of the PWM by adding the frequency jitter signal of a specific frequency, so as to reduce the electromagnetic interference generated by the frequency of the resonant circuit or the resonant topology circuit. Then, the phase shift value of the PWM is obtained according to the preset frequency jitter signal and the output voltage, so as to control the energy of the output voltage by using the phase shift value. Finally, the PWM drive is generated according to the control frequency of the PWM and the phase shift value of the PWM to control the on and off of the switching tube, and the energy of the output voltage is controlled by using the phase shift value of the PWM, thereby suppressing the output voltage ripple.

[0134] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0135] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0136] The above examples are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A voltage ripple suppression method, characterized by, The method is applied to a resonant circuit or a resonant topology circuit, and comprises the following steps: an output voltage of the resonant circuit or the resonant topology circuit is obtained; a voltage control signal is obtained according to the output voltage; a preset frequency jitter signal is obtained; the control frequency of a PWM is obtained by adding the voltage control signal and the preset frequency jitter signal; a phase shift value of the PWM is obtained according to the preset frequency jitter signal and the output voltage; the PWM is generated according to the control frequency of the PWM and the phase shift value of the PWM to drive a switch tube, so as to suppress the output voltage ripple of the resonant circuit or the resonant topology circuit.

2. The method of claim 1, wherein, The voltage control signal is obtained according to the output voltage, and the method comprises the following steps: a voltage setting instruction issued by a host computer is obtained; a voltage reference value is obtained according to the voltage setting instruction; a voltage error value is obtained by subtracting the output voltage from the voltage reference value; the voltage error value is input into a voltage loop controller to obtain the voltage control signal.

3. The method of claim 2, wherein, The preset frequency jitter signal is obtained, and the method comprises the following steps: a preset frequency jitter period is obtained; a frequency jitter amplitude is obtained; the preset frequency jitter signal is obtained according to the preset frequency jitter period and the frequency jitter amplitude.

4. The method of claim 3, wherein, The phase shift value of the PWM is obtained according to the preset frequency jitter signal and the output voltage, and the method comprises the following steps: the phase shift value of the PWM is obtained according to the preset frequency jitter period and the voltage error value.

5. The method of claim 4, wherein, The phase shift value of the PWM is obtained according to the preset frequency jitter period and the voltage error value, and the method comprises the following steps: the voltage error value on the preset frequency jitter period is integrated by using an integrator to obtain an integral value; the integral value is multiplied by a frequency jitter loop control coefficient to obtain the phase shift value of the PWM.

6. A voltage ripple rejection loop, characterized by, The voltage ripple suppression loop is applied to a resonant circuit or a resonant topology circuit, and comprises the following steps: a first data processor is configured to obtain an output voltage of the resonant circuit or the resonant topology circuit; a voltage loop controller is configured to obtain a voltage control signal according to the output voltage; a frequency jitter generator is configured to obtain a preset frequency jitter signal; a second data processor is configured to obtain the control frequency of a PWM by adding the voltage control signal and the frequency jitter signal; a frequency jitter ripple suppression loop is configured to obtain a phase shift value of the PWM according to the preset frequency jitter signal and the output voltage; a PWM generation module is configured to generate the PWM to drive a switch tube according to the control frequency of the PWM and the phase shift value of the PWM, so as to suppress the output voltage ripple of the resonant circuit or the resonant topology circuit.

7. The voltage ripple rejection loop of claim 6, wherein, The first data processor is further configured to: obtain a voltage setting instruction issued by a host computer; obtain a voltage reference value according to the voltage setting instruction; obtain a voltage error value by subtracting the output voltage from the voltage reference value; input the voltage error value into a voltage loop controller to obtain the voltage control signal through the voltage loop controller.

8. The voltage ripple rejection loop of claim 7, wherein, The frequency jitter generator is further configured to: obtain a preset frequency jitter period; obtain a frequency jitter amplitude; obtain the preset frequency jitter signal according to the preset frequency jitter period and the frequency jitter amplitude.

9. The voltage ripple rejection loop of claim 8, wherein, The frequency jitter ripple suppression loop is further configured to: The phase shift value of the PWM is obtained according to the preset dithering frequency period and the voltage error value.

10. The voltage ripple rejection loop of claim 9, wherein, The dithering frequency ripple suppression loop is also used for: The voltage error value on the preset dithering frequency period is integrated by using an integrator to obtain an integral value. The integral value is multiplied by a dithering loop control coefficient to obtain the phase shift value of the PWM.

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