A multi-mode power factor correction circuit and control method thereof

Abstract

A power factor control circuit is disclosed, which is used to control a power factor correction circuit. In a single cycle of an input rectified voltage, combined with the load condition of the power factor correction circuit, it is determined whether the power factor correction circuit operates in one or more of a continuous current mode, a critical current mode, and a discontinuous current mode, thereby reducing the loss of the power factor correction circuit and achieving better working efficiency.

Description

Technical Field

[0001] The embodiments of the present invention relate to an electronic circuit, and in particular to a power factor correction circuit and a control method thereof. Background Art

[0002] Power factor correction (PFC) circuits are widely used in power conversion systems to correct the phase of current, improve the power factor of the circuit, and reduce system losses.

[0003] Generally speaking, the rectified voltage with a sine waveform is obtained after rectification, and is input to the PFC circuit as the power supply voltage. In order to achieve PFC control, the input current Iin needs to follow the waveform of the rectified voltage, and the phases of the two need to be consistent. Figure 1 As shown, the waveform of the average current Iavg of the input current Iin is controlled to be a sinusoidal waveform to follow the waveform and phase of the rectified voltage, thereby improving the power factor of the circuit.

[0004] In the prior art, in order to improve circuit efficiency, PFC circuits usually have three operating modes, continuous current mode (CCM), boundary current mode (BCM) and discontinuous current mode (DCM). The operating mode of the PFC circuit depends on the load state of the circuit. Generally speaking, under heavy load conditions, the PFC circuit operates in continuous current mode; under light load conditions, the PFC circuit operates in discontinuous current mode; under a load state between heavy load and light load, the PFC circuit operates in critical current mode. The input current waveforms in continuous current mode, critical current mode and discontinuous current mode are as follows: Figure 1 shown. Summary of the invention

[0005] The present invention provides a power factor correction circuit, which combines different working modes according to load conditions within a single working cycle of an input rectified voltage, thereby further reducing switching losses and achieving better working efficiency.

[0006] According to an embodiment of the present invention, a power factor control circuit is proposed for controlling a power factor correction circuit, the power factor control circuit comprising: a control reference circuit, receiving a first current reference, a second current reference and an input average current, and outputting a peak current signal, a valley current signal and a turn-on delay signal based on the first current reference, the second current reference and the input average current; and a switch control circuit, receiving a current detection signal, a peak current signal, a valley current signal and a turn-on delay signal, and outputting a switch control signal to control a main power switch of the power factor correction circuit based on the current detection signal, the peak current signal, the valley current signal and the turn-on delay signal, wherein the current detection signal represents the current flowing through the energy storage element of the power factor correction circuit; wherein the input average current represents the power factor correction current. The input current of the circuit, and: when the input average current is greater than the first current reference, the power factor correction circuit operates in a continuous current mode, the main power switch is turned off when the current detection signal increases to a peak current signal, and is turned on when the current detection signal decreases to a valley current signal; when the input average current is less than the first current reference and greater than the second current reference, the power factor correction circuit operates in a critical current mode, the main power switch is turned off when the current detection signal increases to a peak current signal, and is turned on when the current detection signal decreases to zero; and when the input average current is less than the second current reference, the power factor correction circuit operates in a discontinuous current mode, the main power switch is turned off when the current detection signal increases to a peak current signal, and is turned off after the current detection signal decreases to zero and a time length represented by the conduction delay signal has elapsed.

[0007] According to an embodiment of the present invention, a power factor correction circuit is also proposed, including the aforementioned power factor control circuit, and also including a switching conversion circuit, the switching conversion circuit including: an energy storage element coupled between the input end and the switch end of the switching conversion circuit; a main power switch coupled between the switch end and the ground end; and a slave power switch coupled between the switch end and the output end of the switching conversion circuit; wherein the input end of the switching conversion circuit receives a DC input voltage, and the output end of the switching conversion circuit provides an output voltage.

[0008] According to an embodiment of the present invention, a power factor correction circuit is further proposed, comprising the aforementioned power factor control circuit and a switching conversion circuit, wherein the switching conversion circuit has a PFC topology structure.

[0009] According to an embodiment of the present invention, a power factor control method is also proposed for controlling a power factor correction circuit, the power factor control method comprising: controlling the main power switch of the power factor correction circuit to turn off based on a comparison result of a current detection signal and a peak current signal; controlling the main power switch of the power factor correction circuit to turn on based on a comparison result of the current detection signal and a valley current signal, and a turn-on delay signal; wherein the input average current represents the input current of the power factor correction circuit, and: when the input average current is greater than a first current reference, the power factor correction circuit operates in a continuous current mode, the main power switch is turned off when the current detection signal increases to a peak current signal, and the main power switch is turned on when the current detection signal increases to a peak current signal. The power factor correction circuit operates in a critical current mode, wherein the main power switch is turned off when the current detection signal increases to a peak current signal, and is turned on when the current detection signal decreases to zero; and when the input average current is less than the second current reference, the power factor correction circuit operates in a discontinuous current mode, wherein the main power switch is turned off when the current detection signal increases to a peak current signal, and is turned on after the current detection signal decreases to zero and for a period of time represented by the turn-on delay signal; wherein the current detection signal represents the current flowing through the energy storage element of the power factor correction circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to better understand the present invention, the present invention will be described in detail according to the following drawings:

[0011] Figure 1 The waveform of the input current Iin when the PFC circuit operates in different current modes is shown;

[0012] Figure 2 FIG. 2 shows a circuit structure diagram of a power factor correction circuit 20 according to an embodiment of the present invention;

[0013] Figure 3 FIG. 2 is a schematic diagram showing a waveform of an input current Iin when a power factor correction circuit 20 according to an embodiment of the present invention works under a heavy load condition;

[0014] Figure 4 FIG. 2 is a schematic diagram showing a waveform of an input current Iin when a power factor correction circuit 20 according to an embodiment of the present invention operates under a medium load condition;

[0015] Figure 5 FIG. 2 is a schematic diagram showing a waveform of an input current Iin when a power factor correction circuit 20 according to an embodiment of the present invention operates under light load conditions;

[0016] Figure 6A schematic flow chart of a power factor control method 60 for controlling a power factor correction circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0017] The specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to those of ordinary skill in the art that these specific details do not have to be used to implement the present invention. In other examples, in order to avoid confusing the present invention, known circuits, materials or methods are not specifically described.

[0018] Throughout the specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily all refer to the same embodiment or example. In addition, particular features, structures, or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it will be appreciated by those of ordinary skill in the art that the figures provided herein are for illustrative purposes and that the figures are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0019] Figure 2 FIG. 2 shows a schematic diagram of the circuit structure of a power factor correction circuit 20 according to an embodiment of the present invention. The power factor correction circuit 20 includes a rectifier circuit 201, a switch conversion circuit 203, and a power factor control circuit 204. The rectifier circuit 201 rectifies the AC voltage Vac provided by the AC power source 200 into a steamed wave, and then obtains an input rectified voltage Vin through filtering by an input capacitor Cin, and uses the input rectified voltage Vin to power the switch conversion circuit 203. The switch conversion circuit 203 includes the following: Figure 2 The inductor L1, the first switch Q1 and the second switch D1 are connected in a BOOST topology to convert the input rectified voltage Vin into a load voltage ( Figure 2The power factor control circuit 204 receives the input rectified voltage Vin, the current detection signal Vcs representing the input current Iin, and the output voltage Vout, and outputs the switch control signal G1 based on the input rectified voltage Vin, the current detection signal Vcs, and the output voltage Vout, for controlling the switch conversion circuit 203. In one embodiment, the power factor control circuit 204 is integrated into a chip. In some embodiments, the power factor control circuit 204 can also be integrated into the same chip with one or all of the first switch Q1 and the second switch D1.

[0020] exist Figure 2 In the embodiment, the AC power source 200 may be any AC power source including a grid power source. The rectifier circuit 201 may include any existing rectifier circuit, such as a full-bridge rectifier circuit and a half-bridge rectifier circuit.

[0021] exist Figure 2 In the embodiment, the switch conversion circuit 203 includes: an inductor L1 coupled between the input rectified voltage Vin and the switch terminal SW, a first switch Q1 coupled between the switch terminal SW and the reference ground GND, and a second switch D1 coupled between the switch terminal SW and the output voltage Vout. The first switch Q1 is controlled by the switch control signal G1 and is switched on and off alternately with the second switch D1. The specific working process of the switch conversion circuit 203 is: when the first switch Q1 is turned on, the AC power supply 200, the inductor L1 and the first switch Q1 form a loop, the current flowing through the inductor L1, that is, the input current Iin increases, and the output capacitor Cout supplies energy to the load and maintains the output voltage Vout. When the first switch Q1 is turned off, the AC power supply 200, the inductor L1, the second switch D1, the output capacitor Cout and the load form a loop, the current flowing through the inductor L1 decreases, and the output capacitor Cout is charged to maintain the output voltage Vout. By utilizing the energy storage function of the inductor L1 and the output capacitor Cout and controlling the on-off duty cycle of the first switch Q1 , an output voltage Vout having a specific value can be obtained.

[0022] exist Figure 2 In an embodiment, the switch conversion circuit 203 further includes a current detection resistor Rcs, coupled between the first switch Q1 and the input capacitor Cin, participating in the loop of the input current Iin. The input current Iin flows through the current detection resistor Rcs, generating a current detection signal Vcs thereon.

[0023] The present invention Figure 2 In the embodiment, the switch conversion circuit 203 is only illustrated by the BOOST topology. Other topologies, such as BUCK, BUCK-BOOST, FLYBACK, etc., can also be used in the switch conversion circuit of the present invention. Figure 2 In the BOOST topology in the embodiment, the first switch Q1 is called the main power switch, the second switch D1 is called the slave power switch, and the inductor L1 is the energy storage element. It should be understood that when the topology of the switch conversion circuit changes, the positions of each power switch and the energy storage element will also change accordingly. For example, in the FLYBACK topology, the primary switch is usually called the main power switch, the secondary switch is the AC power switch, and the energy storage element is the transformer. Generally speaking, when the main power switch is turned on and the slave power switch is turned off, the energy storage element of the switch conversion circuit starts to store energy; when the main power switch is turned off and the slave power switch is turned on, the energy storage element of the switch conversion circuit starts to release energy.

[0024] exist Figure 2 In the embodiment, the power factor control circuit 204 includes a feedback circuit 2041 , an input current reference circuit 2042 , a control reference circuit 2043 and a switch control circuit 2040 .

[0025] The feedback circuit 2041 receives the output voltage Vout, and outputs a feedback control signal Vcomp based on the output voltage Vout. In one embodiment, the feedback circuit 2041 includes an error amplifier circuit, which compares the output voltage Vout with an output voltage reference signal, and outputs a feedback control signal Vcomp based on the difference between the two. Any existing circuit for generating a feedback control signal related to the output voltage Vout can be used in the present invention. It should be understood that in some embodiments, when the output voltage Vout is greater than the input voltage range of the feedback circuit 2041, the output voltage Vout can be divided by a voltage divider circuit and then provided to the feedback circuit 2041.

[0026] exist Figure 2 In the embodiment, the input current reference circuit 2042 receives the input rectified voltage Vin and the feedback control signal Vcomp, and provides the input average current Iavg based on the input rectified voltage Vin and the feedback control signal Vcomp. The input average current Iavg follows the waveform of the input rectified voltage Vin, and its value is controlled by the feedback control signal Vcomp and the input rectified voltage Vin at the same time. The specific relationship is shown in formula (1):

[0027]

[0028] Wherein Iavg(t) represents the real-time value of the input average current Iavg, Vin(t) represents the real-time value of the input rectified voltage Vin, and Vinpk represents the peak value of the input rectified voltage Vin. It can be seen from formula (1) that when the input rectified voltage Vin is fixed, that is, when the AC voltage Vac is determined, the value of the input average current Iavg is related to the feedback control signal Vcomp. The value of the feedback control signal Vcomp reflects the size of the load, so the value of the input average current Iavg will also be affected by the load. Specifically: when the value of the output voltage Vout represented by the feedback control signal Vcomp increases, the value of the input average current Iavg decreases, and when the value of the output voltage Vout represented by the feedback control signal Vcomp decreases, the value of the input average current Iavg increases. The current reference circuit 2042 can be implemented using existing circuits in the art.

[0029] exist Figure 2 In the embodiment, the control reference circuit 2043 receives the input average current Iavg, the first current reference Iref1 and the second current reference Iref2, and outputs the mode control signal MD, the peak current signal Ipeak, the valley current signal Ivalley and the turn-on delay signal Td based on the comparison between the input average current Iavg and the first current reference Iref1 and the second current reference Iref2. The mode control signal MD is used to indicate the working mode of the power factor correction circuit 20, i.e., CCM, BCM or DCM.

[0030] exist Figure 2 In the embodiment, the switch control circuit 2040 includes a conduction control circuit 2044 , a peak comparator 2045 , a valley comparator 2046 and a driving circuit 2047 .

[0031] The peak comparator 2045 receives the current detection signal Vcs and the peak current signal Ipeak, and outputs the turn-off control signal Coff based on the comparison result of the two. The valley comparator 2046 receives the current detection signal Vcs and the valley current signal Ivalley, and outputs the valley control signal Cva based on the comparison result of the two. The conduction control circuit 2044 receives the valley control signal Cva, the mode control signal MD and the conduction delay signal Td, and outputs the conduction control signal Con based on the valley control signal Cva, the mode control signal MD and the conduction delay signal Td. In CCM and BCM, the value of the conduction delay signal Td is 0. When the current detection signal Vcs drops to the valley current signal Ivalley, the conduction control signal Con controls the first switch Q1 to be turned on. In DCM, after the current detection signal Vcs drops to the valley current signal Ivalley and after the time length represented by the delay signal Td, the conduction control signal Con controls the first switch Q1 to be turned on.

[0032] The driving circuit 2047 receives a shutdown control signal Coff and a conduction control signal Con, and outputs a switch control signal G1 based on the shutdown control signal Coff and the conduction control signal Con. When the shutdown control signal Coff indicates that the current detection signal Vcs reaches the peak current signal Ipeak, the switch control signal G1 controls the first switch Q1 to turn off. In CCM and BCM, when the current detection signal Vcs drops to the valley current signal Ivalley, the switch control signal G1 controls the first switch Q1 to turn on. In DCM, after the current detection signal Vcs drops to the valley current signal Ivalley and after a time length represented by the delay signal Td, the switch control signal G1 controls the first switch Q1 to turn on. The switch control signal G1 controls the first switch Q1 to turn on. In one embodiment, the driving circuit 2047 includes an RS trigger and a driving amplifier circuit. The shutdown control signal Coff controls the reset end of the RS trigger, the conduction control signal Con controls the set end of the RS trigger, and the RS trigger outputs the switch control signal G1. The switch control signal G1 controls the on and off of the first switch Q1 after its driving capability is enhanced by the driving amplifier circuit.

[0033] In the embodiment of the present invention, the working mode of the power factor correction circuit 20 , the values ​​of the peak current signal Ipeak, the valley current signal Ivalley and the turn-on delay signal Td are related to the load size of the power factor correction circuit 20 .

[0034] Figure 3 FIG. 2 is a schematic diagram showing a waveform of the input current Iin when the power factor correction circuit 20 according to an embodiment of the present invention is operated under heavy load conditions. Under heavy load conditions, the maximum value of the input average current Iavg is greater than the first current reference Iref1. For the sake of clarity, Figure 3 Only the waveform of the input current Iin of a single cycle is shown. Figure 3 When the value of the input average current Iavg is greater than the first current reference Iref1, the mode control signal MD indicates that the power factor correction circuit 20 operates in CCM. When the input average current Iavg is less than the second current reference Iref2, the mode control signal MD indicates that the power factor correction circuit 20 operates in DCM. When the input average current Iavg is between the first current reference Iref1 and the second current reference Iref2, the mode control signal MD indicates that the power factor correction circuit 20 operates in BCM. The values ​​of the first current reference Iref1 and the second current reference Iref2 can be set by a person of ordinary skill in the art according to the parameters and requirements of the specific application circuit.

[0035] exist Figure 3In the embodiment, when the power factor correction circuit 20 operates in CCM, the ripple of the input current Iin is fixed. The value of the peak current signal Ipeak is: Ipeak=Iavg+Iref1. The value of the valley current signal Ivalley is: Ivalley=Iavg-Iref1. When the first switch Q1 is turned on, the power supply is connected to the inductor L1, the inductor L1 is charged, and the input current Iin rises. When the input current Iin rises to the peak current signal Ipeak, the peak comparator 2045 outputs the shutdown control signal Coff, resets the drive circuit 2047, and makes it output the switch control signal G1 to turn off the first switch Q1. At this time, the input current Iin continues to flow through the second switch D1, and at the same time charges the output capacitor Cout, and the input current Iin decreases. When the input current Iin drops to the valley current signal Ivalley, the valley comparator 2046 outputs the conduction control signal Con to turn on the first switch Q1, and the input current Iin rises again, a new switching cycle begins, and the above process repeats.

[0036] exist Figure 3 In the embodiment, when the power factor correction circuit 20 operates in BCM, the valley current signal Ivalley is 0, and the peak current signal Ipeak is twice the input average current Iavg, that is, Ipeak=2×Iavg. When the first switch Q1 is turned on, the power supply is connected to the inductor, the inductor L1 is charged, and the input current Iin rises. When the input current Iin rises to the peak current signal Ipeak, the peak comparator 2045 outputs the shutdown control signal Coff, resets the drive circuit 2047, and makes its output switch control signal G1 turn off the first switch Q1. At this time, the input current Iin continues to flow through the second switch D1, and at the same time charges the output capacitor Cout, and the input current Iin decreases. When the input current Iin drops to 0, the valley comparator 2046 outputs the conduction control signal Con to turn on the first switch Q1, and the input current Iin rises again, a new switching cycle begins, and the above process repeats.

[0037] exist Figure 3 In the embodiment, DCM includes two modes, namely variable frequency discontinuous current mode VF-DCM and fixed frequency discontinuous current mode CF-DCM.

[0038] When the power factor correction circuit 20 operates in VF-DCM, the valley current signal Ivalley is 0, the value of the peak current signal Ipeak is twice the second current reference Iref2, that is, Ipeak=2×Iref2, and the value of the on-delay signal Td is:

[0039]

[0040] The on-time Ton is the time when the first switch Q1 is on and the second switch D1 is off, and the off-time Toff is the time when the first switch Q1 is off and the second switch D1 is on. In one embodiment, the power factor control circuit 204 respectively times the on-time of the first switch Q1 and the second switch D1 in each switching cycle, and stores it in a register to obtain the on-time Ton and the off-time Toff. In one embodiment, the power factor control circuit 204 includes a timing circuit, which respectively times the duration of the logic level of the on-control signal Con and the off-control signal Coff corresponding to the switching state of the first switch Q1 and the second switch D1.

[0041] When the first switch Q1 is turned on, the power supply is connected to the inductor, the inductor L1 is charged, and the input current Iin rises. When the input current Iin rises to the peak current signal Ipeak, the peak comparator 2045 outputs the turn-off control signal Coff, resets the drive circuit 2047, and makes it output the switch control signal G1 to turn off the first switch Q1. At this time, the input current Iin continues to flow through the second switch D1, and at the same time charges the output capacitor Cout, and the input current Iin decreases. When the input current Iin decreases to 0, after the duration of the turn-on delay signal Td, the turn-on control circuit 2044 outputs the turn-on control signal Con to turn on the first switch Q1, and the input current Iin rises again, a new switching cycle begins, and the above process repeats.

[0042] In VF-DCM, when the load of the power factor correction circuit 20 decreases, its operating frequency decreases accordingly. When its operating frequency decreases to the minimum switching frequency fmin, the power factor correction circuit 20 enters CF-DCM, and the operating frequency of the power factor correction circuit 20 is fixed at the minimum switching frequency fmin, that is, the switching frequency of the first switch Q1 is fixed at the minimum switching frequency fmin. In CF-DCM, the value of the peak current signal Ipeak is:

[0043]

[0044] The value of the conduction delay signal Td is:

[0045]

[0046] The value of the minimum switching frequency fmin can be set according to the needs of the application. For example, the minimum switching frequency fmin can be set higher than the maximum value of the audio frequency to prevent the operating frequency of the power factor correction circuit 20 from falling into the audio range and generating noise. The minimum switching frequency fmin can also be set according to the needs of a specific application.

[0047] Compared with VF-DCM, the value of the peak current signal Ipeak and the turn-on delay signal Td under CF-DCM are related to the minimum switching frequency fmin, and the specific working process is similar, that is, when the first switch Q1 is turned on, the input current Iin rises, and when the input current Iin rises to the peak current signal Ipeak, the peak comparator 2045 outputs the turn-off control signal Coff, resets the drive circuit 2047, and makes it output the switch control signal G1 to turn off the first switch Q1. At this time, the input current Iin continues to flow through the second switch D1, and the output capacitor Cout is charged at the same time, and the input current Iin decreases. When the input current Iin drops to 0, after the duration of the turn-on delay signal Td, the turn-on control circuit 2044 outputs the turn-on control signal Con to turn on the first switch Q1, and the input current Iin rises again, and a new switching cycle begins.

[0048] It should be understood that the values ​​of the peak current signal Ipeak and the valley current signal Ivalley are only for illustrative purposes. In other embodiments of the present invention, the values ​​of the peak current signal Ipeak and the valley current signal Ivalley may be different. For example, in some embodiments, the switching frequency of the main power switch is fixed, and the values ​​of the peak current signal Ipeak and the valley current signal Ivalley may be determined based on the fixed switching frequency and the input average current.

[0049] Figure 4 FIG. 2 is a schematic diagram showing a waveform of the input current Iin when the power factor correction circuit 20 according to an embodiment of the present invention operates under medium load conditions. Under medium load conditions, the maximum value of the input average current Iavg is less than the first current reference Iref1 and greater than the second current reference Iref2. Figure 4 When the value of the input average current Iavg is less than the first current reference Iref1 and greater than the second current reference Iref2, the power factor correction circuit 20 operates in BCM. When the value of the input average current Iavg is less than the second current reference Iref2, the power factor correction circuit 20 operates in DCM.

[0050] exist Figure 4 In the embodiment, when the power factor correction circuit 20 works in BCM and DCM, the values ​​of the valley current signal Ivalley, the peak current signal Ipeak and the conduction delay signal Td, and the working process thereof are the same as Figure 3 The situation in the embodiments is the same and will not be expanded here for the sake of simplicity.

[0051] Figure 5The waveform diagram of the input current Iin when the power factor correction circuit 20 according to an embodiment of the present invention operates under light load conditions is shown. Under light load conditions, the maximum value of the input average current Iavg is less than the second current reference Iref2, and the power factor correction circuit 20 operates in DCM.

[0052] exist Figure 5 In the embodiment, DCM also includes two modes, namely, variable frequency discontinuous current mode VF-DCM and fixed frequency discontinuous current mode CF-DCM. Under VF-DCM, when the power factor correction circuit 20 works in VF-DCM and CF-DCM, the values ​​of its valley current signal Ivalley, peak current signal Ipeak and conduction delay signal Td, and its working process are the same as Figure 3 The situation in the embodiments is the same and will not be expanded here for the sake of simplicity.

[0053] In the embodiment of the present invention, the control reference circuit 2043 for providing the valley current signal Ivalley, the peak current signal Ipeak and the on-delay signal Td can be implemented by a digital circuit. That is, a digital description language is used to describe the relationship between the valley current signal Ivalley, the peak current signal Ipeak and the on-delay signal Td and the first current reference Iref1, the second current reference Iref2, the input average current Iavg and the set minimum switching frequency fmin, and a digital circuit is automatically generated to implement the control reference circuit 2043.

[0054] In an embodiment of the present invention, the conduction control circuit 2044 receives a valley control signal Cva, a mode control signal MD, and a conduction delay signal Td. When the mode control signal MD indicates that the power factor correction circuit 20 operates in CCM or BCM, the conduction control circuit 2044 provides the valley control signal Cva to the output end as the conduction control signal Con. When the mode control signal MD indicates that the power factor correction circuit 20 operates in DCM, the conduction control circuit 2044 starts timing when the current detection signal Vcs represented by the valley control signal Cva drops to the valley current signal Ivalley, that is, 0. When the timing duration reaches the duration represented by the conduction delay signal Td, the conduction control circuit 2044 outputs the conduction control signal Con for turning on the first switch Q1. In one embodiment, the conduction control circuit 2044 can be implemented using a digital circuit. That is, a digital description language can be used to describe the function and working process of the conduction control circuit 2044, and a digital circuit can be automatically generated.

[0055] Depend on Figure 3 , Figure 4 and Figure 5It can be seen from the embodiment that within a single cycle of the input rectified voltage Vin, the operating mode of the power factor correction circuit 20 is related to the magnitude of the input average current Iavg. When the maximum value of the input average current Iavg is greater than the first current reference Iref1, the operating modes of the power factor correction circuit 20 include CCM, BCM and DCM. When the maximum value of the input average current Iavg is between the first current reference Iref1 and the second current reference Iref2, the operating modes of the power factor correction circuit 20 include BCM and DCM. When the maximum value of the input average current Iavg is less than the second current reference Iref2, the operating mode of the power factor correction circuit 20 includes DCM. Figure 3 , Figure 4 , Figure 5 In the embodiment of the present invention, DCM also includes variable frequency discontinuous current mode VF-DCM and fixed frequency discontinuous current mode CF-DCM. In other embodiments of the present invention, DCM may also include only VF-DCM or only CF-DCM.

[0056] In one embodiment, the mode control signal MD may represent different operating modes in different level forms, for example, the mode control signal MD may represent CCM in a high level, DCM in a low level, and BCM in a high impedance state. In other embodiments, the mode control signal MD may be a digital signal with multiple digits, for example, 00 may represent CCM, 11 may represent DCM, 01 may represent BCM, etc. It should be understood that the mode control signal MD may use any appropriate signal form to represent different operating modes.

[0057] The present invention Figure 2 In the embodiment, the first switch Q1 is a controllable switch, and the second switch D1 is a diode. It should be understood that the first switch Q1 may include an applicable controllable switch such as MOSFET, and the second switch may include an applicable controllable switch such as MOSFET in addition to a diode. When the second switch adopts a controllable switch, the switch control signal G1 may also be used to control the second switch.

[0058] In one embodiment, the values ​​of the first current reference Iref1, the second current reference Iref2 and the minimum switching frequency fmin can be set by writing registers. In some embodiments, the values ​​of the first current reference Iref1, the second current reference Iref2 and the minimum switching frequency fmin can also be set by external devices such as resistors and capacitors connected to the chip.

[0059] Figure 6 FIG. 6 is a flow chart of a power factor control method 60 for controlling a power factor correction circuit according to an embodiment of the present invention. The power factor correction circuit includes: Figure 2The switching conversion circuit 203 with BOOST topology shown in the figure also includes switching conversion circuits with other topologies. The power factor control method 60 includes:

[0060] Step 601, based on the comparison result of the input average current Iavg, the first current reference Iref1 and the second current reference Iref2, the operation mode of the power factor correction circuit is controlled, wherein: when the input average current Iavg is greater than the first current reference Iref1, the power factor correction circuit operates in the continuous current mode; when the input average current Iavg is less than the first current reference Iref1 and greater than the second current reference Iref2, the power factor correction circuit operates in the critical current mode; and when the input average current Iavg is less than the second current reference Iref2, the power factor correction circuit operates in the discontinuous current mode; and

[0061] Step 602, based on the comparison result of the current detection signal Vcs and the peak current signal Ipeak, the valley current signal Ivalley and the conduction delay signal, the main power switch of the power factor correction circuit is controlled, wherein: when the current detection signal Vcs increases to the peak current signal Ipeak, the main power switch is turned off; when the current detection signal Vcs decreases to the valley current signal Ivalley, if the power factor correction circuit works in the continuous current mode and the critical current mode, the main power switch is turned on; when the current detection signal Vcs decreases to the valley current signal Ivalley, if the power factor correction circuit works in the discontinuous current mode, the main power switch is turned on after the time represented by the conduction delay signal Td. The current detection signal Vcs represents the input current of the power factor correction circuit.

[0062] In one embodiment, in the continuous current mode, the difference between the peak current signal and the valley current signal is constant.

[0063] In one embodiment, in the continuous current mode, the value of the peak current signal is the sum of the first current reference and the input average current, and the value of the valley current signal is the difference between the first current reference and the input average current.

[0064] In one embodiment, in the critical current mode, the value of the peak current signal is twice the input average current.

[0065] In one embodiment, in the critical current mode, the valley current signal is zero, and the peak current signal is twice the input average current.

[0066] In one embodiment, in the discontinuous current mode, the difference between the peak current signal and the valley current signal is constant.

[0067] In one embodiment, in the discontinuous current mode, the valley current signal is zero, the peak current signal is twice the second current reference, and the value of the on-delay signal Td is as shown in formula (2).

[0068] In one embodiment, in the discontinuous current mode, the switching frequency of the main power switch is maintained at a constant minimum switching frequency, the valley current signal is zero, the value of the peak current signal is as shown in formula (3), and the value of the on-delay signal is as shown in formula (4).

[0069] In one embodiment, the discontinuous current mode includes: a variable frequency discontinuous current mode, the peak current signal is twice the second current reference, and the value of the conduction delay signal Td is as shown in formula (2); and a fixed frequency discontinuous current mode, the switching frequency of the main power switch is maintained at a constant minimum switching frequency, the valley current signal is zero, the value of the peak current signal is as shown in formula (3), and the value of the conduction delay signal is as shown in formula (4).

[0070] In one embodiment, the power factor correction method also includes: outputting a feedback control signal based on the output voltage of the power factor correction circuit to characterize the load of the power factor control circuit; and providing an input average current based on the feedback control signal and the input rectified voltage; wherein the input rectified voltage is the voltage after the AC voltage is rectified by the rectifier circuit; the input average current is proportional to the product of the feedback control signal and the real-time value of the input rectified voltage, and inversely proportional to the square of the peak value of the input rectified voltage.

[0071] It should be understood that the circuit and working process provided in the present invention are only for illustrative purposes, and any circuit that can realize the function and working process of the circuit of the present invention does not deviate from the spirit or essence of the present invention.

[0072] Although the present invention has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in a variety of forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A power factor control circuit for controlling a power factor correction circuit, the power factor control circuit comprising: A control reference circuit receives a first current reference, a second current reference and an input average current, and outputs a peak current signal, a valley current signal and a turn-on delay signal based on the first current reference, the second current reference and the input average current; as well as a switch control circuit, receiving a current detection signal, a peak current signal, a valley current signal and a turn-on delay signal, and outputting a switch control signal to control a main power switch of a power factor correction circuit based on the current detection signal, the peak current signal, the valley current signal and the turn-on delay signal, wherein the current detection signal represents a current flowing through an energy storage element of the power factor correction circuit; Wherein, the input average current represents the input current of the power factor correction circuit, and: When the input average current is greater than the first current reference, the power factor correction circuit operates in a continuous current mode, and the main power switch is turned off when the current detection signal increases to a peak current signal, and is turned on when the current detection signal decreases to a valley current signal; When the input average current is less than the first current reference and greater than the second current reference, the power factor correction circuit operates in a critical current mode, and the main power switch is turned off when the current detection signal increases to a peak current signal, and is turned on when the current detection signal decreases to zero; as well as When the input average current is less than the second current reference, the power factor correction circuit operates in the discontinuous current mode, and the main power switch is turned off when the current detection signal increases to the peak current signal, and is turned off after the current detection signal decreases to zero and the time represented by the conduction delay signal has passed.

2. The power factor control circuit according to claim 1, wherein: The control reference circuit further outputs a mode control signal representing the working mode of the power factor correction circuit, and the switch control circuit includes: A peak comparator receives a current detection signal and a peak current signal, and outputs a shutdown control signal to control the main power switch to shut down based on a comparison between the current detection signal and the peak current signal; a valley comparator receiving the current detection signal and the valley current signal, and outputting a valley control signal based on a comparison between the current detection signal and the valley current signal; and The conduction control circuit receives a valley control signal, a mode control signal and a conduction delay signal, and outputs a conduction control signal to control the main power switch of the power factor correction circuit to turn off based on the valley control signal, the mode control signal and the conduction delay signal.

3. The power factor control circuit of claim 1, wherein in a continuous current mode, a difference between the peak current signal and the valley current signal is constant.

4. The power factor control circuit as claimed in claim 3, wherein in the continuous current mode, the value of the peak current signal is the sum of the first current reference and the input average current, and the value of the valley current signal is the difference between the first current reference and the input average current. 5 . The power factor control circuit as claimed in claim 1 , wherein in a critical current mode, a value of the peak current signal is twice the input average current. 6 . The power factor control circuit as claimed in claim 5 , wherein in a critical current mode, the valley current signal is zero, and the peak current signal is twice the input average current. 7 . The power factor control circuit as claimed in claim 1 , wherein in the discontinuous current mode, the difference between the peak current signal and the valley current signal is constant. 8 . The power factor control circuit as claimed in claim 7 , wherein in the discontinuous current mode, the valley current signal is zero, and the peak current signal is twice the second current reference. 9 . The power factor control circuit of claim 1 , wherein in the discontinuous current mode, the switching frequency of the main power switch is maintained at a constant minimum switching frequency, and the valley current signal is zero.

10. The power factor control circuit according to claim 1, wherein: The discontinuous current mode includes: In variable frequency discontinuous current mode, the valley current signal is zero, and the peak current signal is twice the second current reference; and In the constant frequency discontinuous current mode, the switching frequency of the main power switch is maintained at a constant minimum switching frequency, and the valley current signal is zero.

11. The power factor control circuit according to claim 1, further comprising: The feedback circuit receives the output voltage of the power factor correction circuit and outputs a feedback control signal to represent the load of the power factor control circuit based on the output voltage.

12. The power factor control circuit according to claim 11, further comprising: An input current reference circuit receives a feedback control signal and an input rectified voltage, and provides an input average current based on the feedback control signal and the input rectified voltage; in, The input rectified voltage is the voltage after the AC voltage is rectified by the rectifier circuit; The input average current is proportional to the product of the feedback control signal and the real-time value of the input rectified voltage, and inversely proportional to the square of the peak value of the input rectified voltage.

13. A power factor correction circuit, comprising the power factor control circuit according to any one of claims 1 to 12, and further comprising a switch conversion circuit, wherein the switch conversion circuit comprises: An energy storage element coupled between an input terminal and a switch terminal of the switch conversion circuit; A main power switch coupled between the switch terminal and the ground terminal; as well as A slave power switch coupled between the switch terminal and an output terminal of the switch conversion circuit; The input end of the switch conversion circuit receives a DC input voltage, and the output end of the switch conversion circuit provides an output voltage.

14. The power factor control circuit as claimed in claim 13 further includes a bridge rectifier circuit coupled between the AC power supply and the input end of the switching conversion circuit, which rectifies the AC voltage provided by the AC power supply and converts it into a rectified input voltage to provide to the switching conversion circuit.

15. A power factor correction circuit, comprising the power factor control circuit according to any one of claims 1 to 12, and further comprising a switch conversion circuit, wherein the switch conversion circuit has a PFC topology structure.

16. A power factor control method for controlling a power factor correction circuit, the power factor control method comprising: Controlling the main power switch of the power factor correction circuit to turn off based on the comparison result of the current detection signal and the peak current signal; Based on the comparison result of the current detection signal and the valley current signal, and the on-delay signal, the main power switch of the power factor correction circuit is controlled to be turned on; Wherein, the input average current represents the input current of the power factor correction circuit, and: When the input average current is greater than the first current reference, the power factor correction circuit operates in a continuous current mode, and the main power switch is turned off when the current detection signal increases to a peak current signal, and is turned on when the current detection signal decreases to a valley current signal; When the input average current is less than the first current reference and greater than the second current reference, the power factor correction circuit operates in a critical current mode, and the main power switch is turned off when the current detection signal increases to a peak current signal, and is turned on when the current detection signal decreases to zero; and When the input average current is less than the second current reference, the power factor correction circuit operates in the discontinuous current mode, and the main power switch is turned off when the current detection signal increases to the peak current signal, and is turned off after the current detection signal decreases to zero and the time represented by the conduction delay signal has passed; The current detection signal represents the current flowing through the energy storage element of the power factor correction circuit. 17 . The power factor control method of claim 16 , wherein in a continuous current mode, a difference between the peak current signal and the valley current signal is constant.

18. The power factor control method according to claim 17, wherein in the continuous current mode, the value of the peak current signal is the sum of the first current reference and the input average current, and the value of the valley current signal is the difference between the first current reference and the input average current.

19. The power factor control method according to claim 16, wherein in a critical current mode, a value of the peak current signal is twice the input average current. 20 . The power factor control method of claim 19 , wherein in a critical current mode, the valley current signal is zero, and the peak current signal is twice the input average current.

21. The power factor control method of claim 16, wherein in the discontinuous current mode, the difference between the peak current signal and the valley current signal is constant.

22. The power factor control method according to claim 21, wherein in the discontinuous current mode, the valley current signal is zero, and the peak current signal is twice the second current reference. 23 . The power factor control method of claim 16 , wherein in the discontinuous current mode, the switching frequency of the main power switch is maintained at a constant minimum switching frequency, and the valley current signal is zero.

24. The power factor control method according to claim 16, wherein: The discontinuous current mode includes: In variable frequency discontinuous current mode, the valley current signal is zero, and the peak current signal is twice the second current reference; and In the constant frequency discontinuous current mode, the switching frequency of the main power switch is maintained at a constant minimum switching frequency, and the valley current signal is zero.

25. The power factor control method according to claim 16, further comprising: Outputting a feedback control signal based on the output voltage of the power factor correction circuit to represent the load of the power factor control circuit; as well as providing an input average current based on a feedback control signal and an input rectified voltage; in, The input rectified voltage is the voltage after the AC voltage is rectified by the rectifier circuit; The input average current is proportional to the product of the feedback control signal and the real-time value of the input rectified voltage, and inversely proportional to the square of the peak value of the input rectified voltage.

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