Detection circuit, electronic circuit, and detection method for detecting clock signal amplitude

Abstract

A detection circuit, electronic circuit, and detection method for detecting the amplitude of a clock signal are disclosed. The detection circuit includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer selects one of a first signal and a second signal as a selection signal based on a comparison signal. The digital-to-analog converter outputs a reference voltage based on the selection signal. The comparator compares the clock signal and the reference voltage to generate a comparison signal. The counter counts the reference clock signal to generate an overflow signal and resets the overflow signal based on the comparison signal. The overflow signal represents the amplitude of the clock signal.

Description

Technical Field

[0001] This invention relates to a detection circuit, electronic circuit, and detection method, and particularly to a detection circuit, electronic circuit, and detection method for detecting the amplitude of a clock signal. Background Technology

[0002] The proper functioning of a crystal oscillator is often crucial for a microcontroller. However, crystal oscillators can sometimes malfunction due to environmental changes or inherent defects in the crystal or circuitry itself, causing the entire oscillator to fail and consequently rendering the microcontroller inoperable or completely inoperable. Therefore, it is necessary to detect the amplitude of the clock signal generated by the crystal oscillator to ensure the microprocessor functions correctly. Summary of the Invention

[0003] This invention provides a detection circuit for the peak-to-peak amplitude of a clock signal to detect whether the peak-to-peak amplitude of the clock signal is sufficiently large. The invention also provides an electronic circuit and detection method for detecting whether the peak-to-peak amplitude of the clock signal is sufficiently large. Furthermore, when it is determined that the peak-to-peak amplitude of the clock signal is insufficient, the gain of the amplifier in the oscillation circuit is increased to increase the peak-to-peak amplitude of the clock signal. The invention further provides an alert based on the gain of the amplifier in the oscillation circuit, notifying the user to replace the quartz crystal as soon as possible to maintain normal system operation.

[0004] In view of this, the present invention proposes a detection circuit for detecting the amplitude of a clock signal. The detection circuit includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer, based on a comparison signal, outputs a selection signal from one of a first signal and a second signal. The digital-to-analog converter outputs a reference voltage based on the selection signal. The comparator compares the clock signal and the reference voltage to generate the comparison signal. The counter counts a reference clock signal to generate an overflow signal and resets the overflow signal based on the comparison signal, wherein the overflow signal represents the amplitude of the clock signal.

[0005] According to an embodiment of the present invention, the digital-to-analog converter receives an external voltage, and the digital-to-analog converter generates a first reference voltage based on the first signal and the external voltage, wherein the digital-to-analog converter generates a second reference voltage based on the second signal and the external voltage, wherein the first reference voltage is less than the second reference voltage.

[0006] According to an embodiment of the present invention, when the peak-to-peak amplitude of the clock signal exceeds the range of the first reference voltage and the second reference voltage, the comparison signal switches between a first voltage level and a second voltage level, and the counter periodically resets the overflow signal according to the comparison signal.

[0007] According to an embodiment of the present invention, when the peak-to-peak amplitude of the clock signal is within the range of the first reference voltage and the second reference voltage, the comparison signal is a second voltage level, and the counter counts the reference clock signal to generate the overflow signal.

[0008] According to one embodiment of the present invention, the detection circuit further includes a delay circuit and a mutually exclusive OR gate. The delay circuit generates a delayed comparison signal based on the comparison signal and a delay time, wherein the delayed comparison signal is delayed by the delay time compared to the comparison signal. The mutually exclusive OR gate includes a first logic input, a second logic input, and a logic output. The first logic input receives the comparison signal, the second logic input receives the delayed comparison signal, and the logic output generates a reset signal. The counter resets the overflow signal based on the reset signal.

[0009] According to one embodiment of the present invention, when the comparison signal changes from a first voltage level to a second voltage level or from the second voltage level to the first voltage level, the reset signal generated by the mutually exclusive OR gate resets the overflow signal. When the comparison signal is the first voltage level or the second voltage level, the reset signal generated by the mutually exclusive OR gate does not reset the overflow signal.

[0010] According to an embodiment of the present invention, the comparator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the input voltage. The second input terminal receives the reference voltage. When the input voltage is greater than the reference voltage, the output terminal outputs a first voltage level as the comparison signal; wherein when the input voltage is not greater than the reference voltage, the output terminal outputs a second voltage level as the comparison signal.

[0011] According to one embodiment of the present invention, when the output terminal outputs the first voltage level, the multiplexer outputs the first signal to the digital-to-analog converter, wherein when the output terminal outputs the second voltage level, the multiplexer outputs the second signal to the digital-to-analog converter.

[0012] The present invention also proposes an electronic circuit including a detection circuit, an oscillation circuit, and a controller. The detection circuit includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer, based on a comparison signal, outputs a selection signal from one of a first signal and a second signal. The digital-to-analog converter outputs a reference voltage based on the selection signal. The comparator compares a clock signal and the reference voltage to generate the comparison signal. The counter counts a reference clock signal to generate an overflow signal and resets the overflow signal based on the comparison signal. The oscillation circuit generates the clock signal and includes an amplifier and a quartz crystal. The amplifier amplifies a signal at a first node by a gain and generates the clock signal at a second node, and generates the gain based on a gain signal. The quartz crystal is coupled between the first node and the second node. The controller generates the gain signal based on the overflow signal.

[0013] According to one embodiment of the present invention, when the overflow signal is a first voltage level, the controller maintains the gain using the gain signal, wherein when the overflow signal is a second voltage level, the controller increases the gain using the gain signal.

[0014] According to one embodiment of the present invention, the digital-to-analog converter receives an external voltage, and generates a first reference voltage based on the first signal and the external voltage. The digital-to-analog converter also generates a second reference voltage based on the second signal and the external voltage, wherein the first reference voltage is less than the second reference voltage.

[0015] According to one embodiment of the present invention, when the peak-to-peak amplitude of the clock signal exceeds the range of the first reference voltage and the second reference voltage, the comparison signal switches between a first voltage level and a second voltage level, and the counter periodically resets the overflow signal according to the comparison signal. When the peak-to-peak amplitude of the clock signal is within the range of the first reference voltage and the second reference voltage, the comparison signal is the second voltage level, and the counter counts the reference clock signal to generate the overflow signal.

[0016] According to an embodiment of the present invention, the detection circuit further includes a delay circuit and a mutually exclusive OR gate. The delay circuit generates a delayed comparison signal based on the comparison signal and a delay time, wherein the delayed comparison signal is delayed by the delay time compared to the comparison signal. The mutually exclusive OR gate includes a first logic input, a second logic input, and a logic output, wherein the first logic input receives the comparison signal, the second logic input receives the delayed comparison signal, and the logic output generates a reset signal, wherein the counter resets the overflow signal based on the reset signal.

[0017] According to one embodiment of the present invention, when the comparison signal changes from a first voltage level to a second voltage level or from the second voltage level to the first voltage level, the reset signal generated by the mutually exclusive OR gate resets the overflow signal. When the comparison signal is the first voltage level or the second voltage level, the reset signal generated by the mutually exclusive OR gate does not reset the overflow signal.

[0018] According to an embodiment of the present invention, the comparator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the input voltage. The second input terminal receives the reference voltage. When the input voltage is greater than the reference voltage, the output terminal outputs a first voltage level as the comparison signal; wherein when the input voltage is not greater than the reference voltage, the output terminal outputs a second voltage level as the comparison signal.

[0019] According to one embodiment of the present invention, when the output terminal outputs the first voltage level, the multiplexer outputs the first signal to the digital-to-analog converter, wherein when the output terminal outputs the second voltage level, the multiplexer outputs the second signal to the digital-to-analog converter.

[0020] According to one embodiment of the present invention, the amplifier has a maximum gain, wherein when the gain is between a first percentage and a second percentage of the maximum gain, the controller issues a first warning. When the gain exceeds the second percentage of the maximum gain, the controller issues a second warning. When the gain is less than the first percentage of the maximum gain, the controller does not issue either the first or the second warning. If the second percentage is greater than the first percentage, the first warning is different from the second warning.

[0021] The present invention also proposes a detection method for detecting a clock signal generated by an oscillating circuit, wherein the oscillating circuit includes an amplifier having a gain. The detection method includes comparing the clock signal with a first reference voltage and a second reference voltage to generate a comparison signal; using a counter to count a reference clock signal to generate an overflow signal; resetting the overflow signal based on the comparison signal; and adjusting the gain based on the overflow signal.

[0022] According to an embodiment of the present invention, the detection method further includes, when the clock signal oscillates within the range of the first reference voltage and the second reference voltage, using the counter to count the overflow signal of the reference clock signal to generate a first voltage level; when the clock signal oscillates outside the range of the first reference voltage and the second reference voltage, using the comparison signal to reset the overflow signal to a second voltage level; when the overflow signal is the first voltage level, increasing the gain; and when the overflow signal is the second voltage level, maintaining the gain.

[0023] According to an embodiment of the present invention, the gain has a maximum gain. The detection method further includes issuing a first warning when the gain is between a first ratio and a second ratio of the maximum gain; issuing a second warning when the gain exceeds the second ratio of the maximum gain; and not issuing the first warning or the second warning when the gain is less than the first ratio of the maximum gain, wherein the second ratio is greater than the first ratio, and the first warning is different from the second warning. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a detection circuit according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the hysteresis curve of the comparator circuit according to an embodiment of the present invention;

[0026] Figure 3 This is a circuit diagram of a digital-to-analog converter according to an embodiment of the present invention;

[0027] Figure 4 This is a circuit diagram of a digital-to-analog converter according to another embodiment of the present invention;

[0028] Figure 5 This is a waveform diagram of the clock signal according to an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of an electronic circuit according to an embodiment of the present invention; and

[0030] Figure 7 This is a flowchart of a detection method according to an embodiment of the present invention.

[0031] Explanation of icon numbers:

[0032] 100, 610: Detection circuit

[0033] 110: Multiplexer

[0034] 120, 300, 400: Digital-to-Analog Converters

[0035] 130: Comparator

[0036] 140: Delay Circuit

[0037] 150: Mutual Exclusion OR Gate

[0038] 160: Counter

[0039] 200: Hysteresis Curve

[0040] 310: Unity-gain amplifier

[0041] 600: Electronic Circuits

[0042] 620: Oscillator Circuit

[0043] 621: Amplifier

[0044] 622: Quartz Crystal

[0045] 630: Controller

[0046] SCMP: Comparison Signal

[0047] VTL<N:0> First signal

[0048] VTH<N:0> Second signal

[0049] SEL<N:0> SEL<3:0>, SEL<2:0>: Selection signals

[0050] SELB<2:0>: Inverting selection signal

[0051] VEXT: External Voltage

[0052] VREF: Reference Voltage

[0053] CLK: Clock signal

[0054] CLKREF: Reference clock signal

[0055] CLK1: First clock signal

[0056] CLK2: Second clock signal

[0057] INP: First Input Terminal

[0058] INN: Second Input Terminal

[0059] OUT: Output terminal

[0060] CK: Clock terminal

[0061] RST: Reset End

[0062] OFL: Overflow terminal

[0063] LIN1: First logic input

[0064] LIN2: Second logic input

[0065] LOUT: Logic output terminal

[0066] VTH: High threshold voltage

[0067] VTL: Low Threshold Voltage

[0068] D: Delay time

[0069] SCMPD: Delayed Comparison Signal

[0070] SRST: Reset signal

[0071] VDD: Supply voltage

[0072] GND: Ground terminal

[0073] P1: First Path

[0074] P2: Second Path

[0075] H: Hysteresis

[0076] R1: First resistor

[0077] R2: Second resistor

[0078] R3: Third resistor

[0079] R4: Fourth resistor

[0080] R5: Fifth resistor

[0081] R6: Sixth resistor

[0082] R7: Seventh resistor

[0083] R8: Eighth resistor

[0084] R9: Ninth resistor

[0085] R10: Tenth resistor

[0086] R11: Eleventh resistor

[0087] R12: Twelfth resistor

[0088] R13: Thirteenth resistor

[0089] R14: The fourteenth resistor

[0090] R15: Fifteenth resistor

[0091] R16: Sixteenth resistor

[0092] R17: Seventeenth resistor

[0093] CREF: Reference capacitor

[0094] SGN: Gain Signal

[0095] SOFL: Overflow signal

[0096] G: Gain

[0097] C1: First capacitor

[0098] C2: Second capacitor

[0099] N1: First node

[0100] N2: Second node

[0101] S710~S780: Procedure Flow Detailed Implementation

[0102] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the invention and should not be considered as a limitation thereof. The scope of the invention should be defined by the claims.

[0103] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various devices, components, regions, layers, and / or portions, these devices, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different devices, components, regions, layers, and / or portions. Therefore, a first device, component, region, layer, and / or portion discussed below may be referred to as a second device, component, region, layer, and / or portion without departing from the teachings of some embodiments of the present invention.

[0104] It is worth noting that the following description provides multiple embodiments or examples for practicing different features of the present invention. The specific device examples and arrangements described below are only intended to briefly illustrate the spirit of the invention and are not intended to limit the scope of the invention. Furthermore, the same device symbols or terms may be repeated in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear description and is not intended to limit the relationship between the various embodiments and / or configurations discussed below. Moreover, descriptions in the following description of a feature being connected to, coupled to, and / or formed on another feature may actually encompass multiple different embodiments, including direct contact between the features, or additional features formed between the features, such that the features are not in direct contact.

[0105] Figure 1 This is a schematic diagram of a detection circuit according to an embodiment of the present invention. (As shown...) Figure 1 As shown, the detection circuit 100 includes a multiplexer 110, a digital-to-analog converter 120, and a comparator 130. The multiplexer 110 converts the first signal VTL according to the voltage level of the comparison signal SCMP.<N:0> and the second signal VTH<N:0> One output is the selection signal SEL<N:0> According to one embodiment of the present invention, the first signal VTL<N:0> Second signal VTH<N:0> and selection signal SEL<N:0> These are digital signals. In other words, the first signal VTL<N:0> Second signal VTH<N:0> and selection signal SEL<N:0> Both are (N+1) bit digital signals, where N is any positive integer.

[0106] The digital-to-analog converter 120 selects the signal SEL.<N:0> And the external voltage VEXT, outputting a reference voltage VREF. Comparator 130 is used to compare the clock signal CLK and the reference voltage VREF to generate a comparison signal SCMP. Figure 1 As shown, comparator 130 includes a first input terminal INP, a second input terminal INN, and an output terminal OUT. The first input terminal INP receives the clock signal CLK, the second input terminal INN receives the reference voltage VREF, and the output terminal OUT outputs the comparison signal SCMP.

[0107] According to an embodiment of the present invention, when the clock signal CLK is greater than the reference voltage VREF, the comparison signal SCMP output by the output terminal OUT is at a first voltage level, such that the multiplexer 110 adjusts the first signal VTL according to the comparison signal SCMP at the first voltage level.<N:0> The output is the selection signal SEL.<N:0> The digital-to-analog converter 120 operates based on the external voltage VEXT and the first signal VTL.<N:0> This generates the reference voltage VREF, which serves as the low threshold voltage VTL.

[0108] According to another embodiment of the present invention, when the clock signal CLK is not greater than the reference voltage VREF, the comparison signal SCMP output by the output terminal OUT is at the second voltage level, so that the multiplexer 110, based on the comparison signal SCMP at the second voltage level, sets the second signal VTH...<N:0> The output is the selection signal SEL.<N:0> The digital-to-analog converter 120 operates based on the external voltage VEXT and the second signal VTH.<N:0> This generates the reference voltage VREF, which serves as the high threshold voltage VTH.

[0109] According to one embodiment of the present invention, the first voltage level is a high voltage level, the second voltage level is a low voltage level, and the high threshold voltage VTH is greater than the low threshold voltage VTL. According to one embodiment of the present invention, the first signal VTL can be adjusted...<N:0> and the second signal VTH<N:0> This achieves the purpose of adjusting the hysteresis of the detection circuit 100.

[0110] Figure 2 This is a schematic diagram of the hysteresis curve of the comparator circuit according to an embodiment of the present invention. Figure 2 As shown, the vertical axis of the hysteresis curve 200 represents the comparison signal SCMP, where the highest level of the comparison signal SCMP is the supply voltage VDD and the lowest level is the ground terminal GND. The horizontal axis of the hysteresis curve 200 represents the reference voltage VREF, where the supply voltage VDD and the ground terminal GND power the comparator 130.

[0111] According to an embodiment of the present invention, when Figure 1 When the comparator 130 outputs a low voltage level comparison signal SCMP (i.e., ground GND or the second voltage level), the multiplexer 110 adjusts the second signal VTH according to the comparison signal SCMP.<N:0> The reference voltage VREF generated by the digital-to-analog converter 120 is provided to the digital-to-analog converter 120 such that it is the high threshold voltage VTH. Therefore, when the clock signal CLK exceeds the high threshold voltage VTH, the comparator signal SCMP moves along... Figure 2 The first path P1 transitions from a low voltage level (i.e., ground terminal GND or second voltage level) to a high voltage level (i.e., supply voltage VDD or first voltage level).

[0112] According to another embodiment of the present invention, when Figure 1 When the comparator 130 outputs a comparison signal SCMP at a high voltage level (i.e., the supply voltage VDD or the first voltage level), the multiplexer 110 adjusts the first signal VTL according to the comparison signal SCMP.<N:0> The reference voltage VREF generated by the digital-to-analog converter 120 is provided to the digital-to-analog converter 120 such that it is the low threshold voltage VTL. Therefore, when the clock signal CLK is lower than the low threshold voltage VTL, the comparator signal SCMP moves along... Figure 2 The second path P2 transitions from a high voltage level (i.e., the supply voltage VDD or the first voltage level) to a low voltage level (i.e., the ground terminal GND or the second voltage level).

[0113] In other words, such as Figure 2 As shown, the threshold voltage at which the comparison signal SCMP transitions from a high voltage level (i.e., the supply voltage VDD or the first voltage level) to a low voltage level (i.e., the ground terminal GND or the second voltage level) is different from the threshold voltage at which the comparison signal SCMP transitions from a low voltage level (i.e., the ground terminal GND or the second voltage level) to a high voltage level (i.e., the supply voltage VDD or the first voltage level), and the difference between the high threshold voltage VTH and the low threshold voltage VTL is defined as the hysteresis H.

[0114] Figure 3 This is a circuit diagram of a digital-to-analog converter according to an embodiment of the present invention, wherein the digital-to-analog converter 300 corresponds to... Figure 1 The digital-to-analog converter 120. Furthermore... Figure 3 The digital-to-analog converter 300 is explained using only 4 bits and is not limited to this in any way. For example... Figure 3 As shown, the digital-to-analog converter 300 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a unity-gain amplifier 310.

[0115] like Figure 3 As shown, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 have the same first resistance value, and the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 have the same second resistance value, wherein the first resistance value is twice the second resistance value. The 4-bit selection signal SEL<3:0> is used to switch the second resistor R2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 between the external voltage VEXT and the ground terminal GND, respectively, and to generate a reference voltage VREF between the fifth resistor R5 and the eighth resistor R8.

[0116] The positive terminal of the unity-gain amplifier 310 receives the reference voltage VREF, and the negative input and output terminals of the unity-gain amplifier 310 are electrically connected to form a unity-gain amplifier. In other words, the output terminal of the unity-gain amplifier 310 outputs the reference voltage VREF, and the unity-gain amplifier 310 is used to improve the current drive capability of the reference voltage VREF.

[0117] According to an embodiment of the present invention, the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are switched between the external voltage VEXT and the ground terminal GND by the selection signal SEL<3:0>, and different voltage division ratios are generated between the fifth resistor R5 and the eighth resistor R8, and a reference voltage VREF is generated in conjunction with the external voltage VEXT.

[0118] Figure 4 This is a circuit diagram of a digital-to-analog converter according to another embodiment of the present invention, wherein the digital-to-analog converter 400 corresponds to... Figure 1 The digital-to-analog converter 120. Furthermore... Figure 4 The digital-to-analog converter 400 is explained using only 3 bits and is not limited to this in any way. For example... Figure 4 As shown, the digital-to-analog converter 400 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, and a seventeenth resistor R17 connected in series between the external voltage VEXT and the ground terminal GND, and has the same resistance value, in order to divide the voltage difference between the external voltage VEXT and the ground terminal GND into nine equal parts.

[0119] The selection signals SEL<2:0> and SELB<2:0> are used to select an appropriate voltage output as the reference voltage VREF, where the inverting selection signal SELB<2:0> is the inverse of the selection signal SEL<2:0>. Furthermore, the digital-to-analog converter 400 includes a reference capacitor CREF, which is electrically connected between the reference voltage VREF and the ground terminal GND to stabilize the reference voltage VREF. In other words, the digital-to-analog converter 400 selects different voltage division ratios based on different selection signals SEL<2:0> and SELB<2:0>, and generates different reference voltages VREF in conjunction with the external voltage VEXT, where the reference voltage VREF is the product of the external voltage VEXT and the selected voltage division ratio.

[0120] refer to Figure 1 The detection circuit 100 further includes a delay circuit 140, a mutex OR gate 150, and a counter 160. The delay circuit 140 is used to generate a delay time D, and generates a delayed comparison signal SCMPD based on the comparison signal SCMP and the delay time D. According to an embodiment of the present invention, the delayed comparison signal SCMPD is delayed by the delay time D compared to the comparison signal SCMP.

[0121] The OR gate 150 includes a first logic input terminal LIN1, a second logic input terminal LIN2, and a logic output terminal LOUT. The first logic input terminal LIN1 receives a comparison signal SCMP, the second logic input terminal LIN2 receives a delayed comparison signal SCMPD, and the logic output terminal LOUT generates a reset signal SRST.

[0122] According to one embodiment of the present invention, when the comparison signal SCMP transitions from a high voltage level to a low voltage level or from a low voltage level to a high voltage level, the delay circuit 140 provides a delay time D, causing the delayed comparison signal SCMPD to change later than the comparison signal SCMP. Therefore, the mutex OR gate 150 receives the comparison signal SCMP at a high voltage level and the delayed comparison signal SCMPD at a low voltage level, respectively, and outputs a reset signal SRST at a high voltage level.

[0123] According to another embodiment of the present invention, when the comparison signal SCMP is maintained at a high voltage level or a low voltage level, although the delay circuit 140 provides a delay time D, the delayed comparison signal SCMPD and the comparison signal SCMP are also at a high voltage level or a low voltage level. Therefore, the mutex OR gate 150 receives the comparison signal SCMP and the delayed comparison signal SCMPD, which are both at a high voltage level or a low voltage level, while the output reset signal SRST is at a low voltage level.

[0124] Counter 160 includes a clock input CK, a reset input RST, and an overflow input OFL. The clock input CK receives a reference clock signal CLKREF, the reset input RST receives a reset signal SRST, and the overflow input OFL generates an overflow signal SOFL. Counter 160 is used to count the number of pulses of the reference clock signal CLKREF to generate the overflow signal SOFL, and the counter resets the overflow signal SOFL according to the reset signal SRST. According to one embodiment of the present invention, the overflow signal SOFL generated by counter 160 counting the number of pulses of the reference clock signal CLKREF is at a high voltage level, and the overflow signal SOFL reset by the reset signal SRST is at a low voltage level. According to one embodiment of the present invention, the reference clock signal CLKREF is provided externally.

[0125] Figure 5 This is a waveform diagram of the clock signal according to an embodiment of the present invention. Figure 5 As shown, the peak-to-peak amplitude of the first clock signal CLK1 is within the range of the high threshold voltage VTH and the low threshold voltage VTL, while the peak-to-peak amplitude of the second clock signal CLK2 exceeds the range of the high threshold voltage VTH and the low threshold voltage VTL.

[0126] According to an embodiment of the present invention, when Figure 1 The clock signal CLK is for Figure 5 When the first clock signal CLK1 is received, the comparison signal SCMP remains at a high or low voltage level, and the reset signal SRST output by the OR gate 150 is at a low voltage level, causing the overflow signal SOFL generated by the counter 160 counting the number of pulses of the reference clock CLKREF to be at a high voltage level.

[0127] According to another embodiment of the present invention, when Figure 1 The clock signal CLK is Figure 5 When the second clock signal CLK2 is received, the comparator signal SCMP switches between high and low voltage levels, and the reset signal SRST output by the mutex gate 150 is at a high voltage level, causing the overflow signal SOFL reset by the counter 160 according to the reset signal SRST to be at a low voltage level. Furthermore, because the comparator signal SCMP switches between high and low voltage levels, the reset signal SRST also switches between high and low voltage levels.

[0128] In summary, the relationship between the peak-to-peak amplitude of the clock signal CLK and the high threshold voltage VTH and low threshold voltage VTL can be determined by the overflow signal SOFL, thereby determining whether the peak-to-peak amplitude of the clock signal CLK is sufficiently large. The low threshold voltage VTL and the high threshold voltage VTH can be determined by the first signal VTL.<N:0> and the second signal VTH<N:0> Adjustments will be made.

[0129] Figure 6 This is a schematic diagram of an electronic circuit according to an embodiment of the present invention. (As shown...) Figure 6 As shown, the electronic circuit 600 includes a detection circuit 610, an oscillation circuit 620, and a controller 630, wherein the detection circuit 610 corresponds to... Figure 1 The detection circuit 100 will not be described again here.

[0130] The oscillation circuit 620 includes an amplifier 621, a quartz crystal 622, a first capacitor C1, and a second capacitor C2. The amplifier 621 amplifies the signal at the first node N1 by a gain G, and then generates a clock signal CLK at the second node N2. The amplifier 621 also generates a gain G based on the gain signal SGN.

[0131] Quartz crystal 622 is electrically connected between the first node N1 and the second node N2, first capacitor C1 is electrically connected between the first node N1 and ground GND, and second capacitor C2 is electrically connected between the second node N2 and ground GND. In other words, oscillation circuit 620 generates clock signal CLK at the second node N2, and uses the gain G of amplifier 621 to increase or decrease the peak-to-peak amplitude of clock signal CLK.

[0132] The controller 630 receives an overflow signal SOFL and a comparison signal SCMP, and determines whether the peak-to-peak amplitude of the clock signal CLK is sufficiently large based on the overflow signal SOFL. Furthermore, the controller 630 adjusts the gain G of amplifier 621 via the gain signal SGN, thereby adjusting the peak-to-peak amplitude of the clock signal CLK. According to one embodiment of the present invention, the controller 630 can adjust the peak-to-peak amplitude of the clock signal CLK via the first signal VTL.<N:0> and the second signal VTH<N:0> Adjust the low threshold voltage VTL and the high threshold voltage VTH respectively.

[0133] According to an embodiment of the present invention, when the clock signal CLK is... Figure 5 When the first clock signal CLK1 is received, the comparison signal SCMP is at a high or low voltage level, causing the reset signal SRST output by the OR gate 150 to be at a low voltage level. Therefore, the overflow signal SOFL generated by the counter 160 counting the pulses of the reference clock signal CLKREF is at a high voltage level. When the controller 630 determines, based on the high-voltage overflow signal SOFL, that the peak-to-peak amplitude of the clock signal CLK is insufficient and that the peak-to-peak amplitude of the clock signal CLK is within the range of the high threshold voltage VTH and the low threshold voltage VTL, the controller 630 uses the gain signal SGN to increase the gain G of the amplifier 621.

[0134] According to another embodiment of the present invention, when the clock signal CLK is Figure 5 When the second clock signal CLK2 is received, the comparison signal SCMP switches between high and low voltage levels, causing the reset signal SRST output by the OR gate 150 to also switch between high and low voltage levels, thereby periodically resetting the overflow signal SOFL of the counter 160 to a low voltage level. When the controller 630 determines, based on the low voltage overflow signal SOFL, that the peak-to-peak amplitude of the clock signal CLK is large enough and exceeds the range of the high threshold voltage VTH and the low threshold voltage VTL, the controller 630 maintains the gain G of the amplifier 621, causing the oscillation circuit 620 to continuously output a clock signal CLK with the same peak-to-peak amplitude.

[0135] The above explanation uses the example of the overflow signal SOFL being reset to a low voltage level and the counter 160 overflowing while the overflow signal SOFL is at a high voltage level, and is not intended to limit the explanation in any way. In other words, the counter 160 can reset the overflow signal SOFL to a high voltage level according to the reset signal SRST, and the overflow signal SOFL is at a low voltage level when the counter 160 overflows while counting the number of pulses of the reference clock signal CLKREF.

[0136] like Figure 6As shown, amplifier 621 has a maximum gain G. According to one embodiment of the invention, when gain G is between a first percentage and a second percentage of the maximum gain, controller 630 issues a first warning. According to another embodiment of the invention, when gain G exceeds a second percentage of the maximum gain, controller G issues a second warning. According to yet another embodiment of the invention, when gain G is less than a first percentage of the maximum gain, controller 630 does not issue any warning. According to various embodiments of the invention, the second percentage is greater than the first percentage, and the first warning differs from the second warning.

[0137] For example, when the gain G of amplifier 621 is less than 50% of the maximum gain, controller 630 does not issue any warning. When the gain G of amplifier 621 is greater than 50% of the maximum gain but less than 75% of the maximum gain, controller 630 issues a slight warning to inform the user that the oscillator circuit 620 is showing signs of aging. When the gain of amplifier 621 is greater than 75% of the maximum gain but less than 90% of the maximum gain, controller 630 issues a moderate warning to warn the user that the oscillator circuit 620 is severely aged and should be replaced with the quartz crystal 622 as soon as possible, and that the system should be monitored for proper operation. When the gain of amplifier 621 is greater than 90% of the maximum gain, controller 630 issues a strong warning to warn the user that the oscillator circuit 620 may stop operating at any time and the quartz crystal 622 should be replaced immediately. The above examples are for illustrative purposes only and are not intended to limit the application in any way.

[0138] According to one embodiment of the present invention, the detection circuit 610, the amplifier 621 of the oscillation circuit 620, and the controller 630 are located in a microprocessor. In other words, the detection circuit 610, the amplifier 621 of the oscillation circuit 620, and the controller 630 are located in the same package or on the same chip, and are externally connected to a quartz crystal 622, a first capacitor C1, and a second capacitor C2 through the first node N1 and the second node N2.

[0139] Figure 7 This is a flowchart of a detection method according to an embodiment of the present invention. The following is specifically for... Figure 7 The flowchart description will be paired with Figure 6 The electronic circuit 600 will be described in detail.

[0140] like Figure 7 As shown, firstly, comparator 130 is used to compare the clock signal CLK with the first reference voltage (corresponding to...). Figure 6 The low threshold voltage (VTL) and the second reference voltage (corresponding to the low threshold voltage V ... Figure 6The high threshold voltage VTH is used to generate a comparison signal SCMP (step S710). Next, the number of pulses of the reference clock signal CLKREF is counted using counter 160 to generate an overflow signal SOFL (step S720), and / or the overflow signal SOFL is reset according to the comparison signal SCMP (step S730). Figure 6 As shown, the delay circuit 140 and the mutual exclusion gate 150 generate a reset signal SRST based on the comparison signal SCMP, thereby resetting the overflow signal SOFL.

[0141] Subsequently, the controller 630 determines the voltage level of the overflow signal SOFL (step S740). According to one embodiment of the present invention, when the overflow signal SOFL generated by the counter 160 counting the number of pulses of the reference clock signal CLKREF is at a high voltage level (corresponding to the first voltage level), the counter 160 resets the overflow signal SOFL to a low voltage level (corresponding to the second voltage level) according to the reset signal SRST. According to another embodiment of the present invention, when the overflow signal SOFL generated by the counter 160 counting the number of pulses of the reference clock signal CLKREF is at a low voltage level (corresponding to the first voltage level), the counter 160 resets the overflow signal SOFL to a high voltage level (corresponding to the second voltage level) according to the reset signal SRST.

[0142] After step S740, when the overflow signal SOFL is at the first voltage level, it indicates that the counter 160 has overflowed and the peak-to-peak amplitude of the clock signal CLK is within the range of the first reference voltage and the second reference voltage. Therefore, the controller 630 increases the gain G of the amplifier 621 (step S750). When the overflow signal SOFL is at the second voltage level, it indicates that the peak-to-peak amplitude of the clock signal CLK exceeds the range of the first reference voltage and the second reference voltage. Therefore, the controller 630 maintains the gain G of the amplifier 621 (step S760) to maintain the peak-to-peak amplitude of the clock signal CLK.

[0143] After steps S750 and S760, the controller 630 determines whether the gain G of the amplifier 621 exceeds a predetermined proportion of the maximum gain (step S770). When it is determined that the gain G exceeds the predetermined proportion of the maximum gain, the controller 630 issues a warning (step S780) to alert the user.

[0144] For example, when the gain G of amplifier 621 is less than 50% of the maximum gain, controller 630 does not issue any warning. When the gain G of amplifier 621 is greater than 50% of the maximum gain but less than 75% of the maximum gain, controller 630 issues a slight warning to inform the user that the oscillator circuit 620 is showing signs of aging. When the gain of amplifier 621 is greater than 75% of the maximum gain but less than 90% of the maximum gain, controller 630 issues a moderate warning to warn the user that the oscillator circuit 620 is severely aged and should be replaced with the quartz crystal 622 as soon as possible, and that the system should be monitored for proper operation. When the gain of amplifier 621 is greater than 90% of the maximum gain, controller 630 issues a strong warning to warn the user that the oscillator circuit 620 may stop operating at any time and the quartz crystal 622 should be replaced immediately. The above examples are for illustrative purposes only and are not intended to limit the application in any way.

[0145] This invention provides a detection circuit for the peak-to-peak amplitude of a clock signal to detect whether the peak-to-peak amplitude of the clock signal is sufficiently large. The invention also provides an electronic circuit and detection method for detecting whether the peak-to-peak amplitude of the clock signal is sufficiently large. Furthermore, when it is determined that the peak-to-peak amplitude of the clock signal is insufficient, the gain of the amplifier in the oscillation circuit is increased to increase the peak-to-peak amplitude of the clock signal. This invention further provides a warning based on the gain of the amplifier in the oscillation circuit, notifying the user to replace the quartz crystal as soon as possible to maintain normal system operation.

[0146] While the embodiments and advantages of the present invention have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the present invention. Furthermore, the scope of protection of the present invention is not limited to the manufacturing processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand, from the disclosure of some embodiments of the present invention, current or future developed manufacturing processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, they can be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-described manufacturing processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present invention also includes combinations of various claim claims and embodiments.

Claims

1. A detection circuit for detecting the amplitude of a clock signal, characterized in that, Used to detect a clock signal, including: A multiplexer, based on a comparison signal, converts one output of a first signal and a second signal into a selection signal; A digital-to-analog converter outputs a reference voltage based on the selection signal mentioned above; A comparator compares the aforementioned clock signal and the aforementioned reference voltage to generate the aforementioned comparison signal; and A counter counts a reference clock signal to generate an overflow signal, and resets the overflow signal according to the comparison signal, wherein the overflow signal represents the amplitude of the clock signal.

2. The detection circuit as described in claim 1, characterized in that, The aforementioned digital-to-analog converter receives an external voltage, and generates a first reference voltage based on the first signal and the external voltage. The aforementioned digital-to-analog converter also generates a second reference voltage based on the second signal and the external voltage, wherein the first reference voltage is less than the second reference voltage.

3. The detection circuit as described in claim 2, characterized in that, When the peak-to-peak amplitude of the clock signal exceeds the range of the first reference voltage and the second reference voltage, the comparison signal switches between a first voltage level and a second voltage level, and the counter periodically resets the overflow signal according to the comparison signal.

4. The detection circuit as described in claim 2, characterized in that, When the peak-to-peak amplitude of the clock signal is within the range of the first reference voltage and the second reference voltage, the comparison signal is a second voltage level, and the counter counts the reference clock signal to generate the overflow signal.

5. The detection circuit as described in claim 1, characterized in that, Also includes: A delay circuit generates a delayed comparison signal based on the aforementioned comparison signal and a delay time, wherein the delayed comparison signal is delayed by the aforementioned delay time compared to the aforementioned comparison signal; and A mutex OR gate includes a first logic input, a second logic input, and a logic output. The first logic input receives the comparison signal, the second logic input receives the delayed comparison signal, and the logic output generates a reset signal. The counter resets the overflow signal based on the reset signal.

6. The detection circuit as described in claim 1, characterized in that, The comparators mentioned above include: The first input terminal receives the aforementioned clock signal; A second input terminal receives the aforementioned reference voltage; and One output terminal outputs a first voltage level as the comparison signal when the clock signal is greater than the reference voltage, and outputs a second voltage level as the comparison signal when the clock signal is not greater than the reference voltage.

7. An electronic circuit for detecting the amplitude of a clock signal, characterized in that, include: A detection circuit, including: A multiplexer, based on a comparison signal, outputs one of a first signal and a second signal as a selection signal; A digital-to-analog converter outputs a reference voltage based on the selection signal mentioned above; A comparator compares a clock signal with the aforementioned reference voltage to generate the aforementioned comparison signal; and A counter counts a reference clock signal to generate an overflow signal, and resets the overflow signal according to the comparison signal mentioned above. An oscillation circuit generates the aforementioned clock signal and includes: An amplifier amplifies a signal at a first node by a gain and generates the aforementioned clock signal at a second node, and generates the aforementioned gain based on a gain signal; and A quartz crystal, coupled between the first node and the second node; and A controller generates the gain signal based on the overflow signal.

8. The electronic circuit as described in claim 7, characterized in that, When the overflow signal is a first voltage level, the controller maintains the gain according to the gain signal; when the overflow signal is a second voltage level, the controller increases the gain according to the gain signal.

9. The electronic circuit as described in claim 8, characterized in that, The aforementioned digital-to-analog converter receives an external voltage, and generates a first reference voltage based on the first signal and the external voltage. The aforementioned digital-to-analog converter also generates a second reference voltage based on the second signal and the external voltage, wherein the first reference voltage is less than the second reference voltage.

10. The electronic circuit as described in claim 9, characterized in that, When the peak-to-peak amplitude of the clock signal exceeds the range of the first reference voltage and the second reference voltage, the comparison signal switches between a first voltage level and a second voltage level. The counter periodically resets the overflow signal according to the comparison signal. When the peak-to-peak amplitude of the clock signal is within the range of the first reference voltage and the second reference voltage, the comparison signal is the second voltage level, and the counter counts the reference clock signal to generate the overflow signal.

11. The electronic circuit as described in claim 7, characterized in that, The above detection circuit also includes: A delay circuit generates a delayed comparison signal based on the aforementioned comparison signal and a delay time, wherein the delayed comparison signal is delayed by the aforementioned delay time compared to the aforementioned comparison signal; and A mutex OR gate includes a first logic input, a second logic input, and a logic output. The first logic input receives the comparison signal, the second logic input receives the delayed comparison signal, and the logic output generates a reset signal. The counter resets the overflow signal based on the reset signal.

12. The electronic circuit as described in claim 7, characterized in that, The comparators mentioned above include: The first input terminal receives the aforementioned clock signal; A second input terminal receives the aforementioned reference voltage; and One output terminal outputs a first voltage level as the comparison signal when the clock signal is greater than the reference voltage, and outputs a second voltage level as the comparison signal when the clock signal is not greater than the reference voltage.

13. The electronic circuit as described in claim 7, characterized in that, The amplifier has a maximum gain. When the gain is between a first ratio and a second ratio of the maximum gain, the controller issues a first warning. When the gain exceeds the second ratio of the maximum gain, the controller issues a second warning. When the gain is less than the first ratio of the maximum gain, the controller does not issue either the first or the second warning. The second ratio is greater than the first ratio. The first warning is different from the second warning.

14. A method for detecting the amplitude of a clock signal, characterized in that, This is used to detect a clock signal generated by an oscillating circuit, wherein the oscillating circuit includes an amplifier having a gain, including: The clock signal is compared with a first reference voltage and a second reference voltage to generate a comparison signal; A counter is used to count a reference clock signal to generate an overflow signal; Based on the above comparison signal, reset the above overflow signal; and Adjust the gain based on the overflow signal mentioned above; The aforementioned detection methods also include: When the clock signal oscillates within the range of the first reference voltage and the second reference voltage, the overflow signal of the reference clock signal is generated by counting the reference clock signal using the counter. When the clock signal oscillates outside the range of the first reference voltage and the second reference voltage, the overflow signal is reset to a second voltage level using the comparison signal. When the overflow signal is at the first voltage level, increase the gain; and When the overflow signal is at the second voltage level, the gain is maintained.

15. The detection method as described in claim 14, characterized in that, The aforementioned gain has a maximum gain, and the aforementioned detection method further includes: When the aforementioned gain is between a first ratio and a second ratio of the aforementioned maximum gain, a first warning is issued; When the aforementioned gain exceeds the aforementioned second proportion of the aforementioned maximum gain, a second warning is issued; and When the aforementioned gain is less than the aforementioned first proportion of the aforementioned maximum gain, neither the aforementioned first warning nor the aforementioned second warning is issued, wherein the aforementioned second proportion is greater than the aforementioned first proportion, and the aforementioned first warning is different from the aforementioned second warning.

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