RF Receiver

Abstract

The present disclosure relates to a radio frequency (RF) receiver. In one embodiment, a radio frequency (RF) receiver circuit includes a main circuit and a wake-up circuit. The main circuit is configured to process an RF signal. The wake-up circuit is configured to detect receipt of the RF signal. The wake-up circuit includes an automatic gain control (AGC) loop and is configured to have a first operating mode and a second operating mode. In the first operating mode, a setpoint voltage of the loop has a first substantially constant value. In the second operating mode, the setpoint voltage of the loop has a second value that depends on a supply voltage of the wake-up circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French application No. 2110408, filed on October 10, 2021, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic devices and, in particular embodiments, to radio frequency wave receivers. Background Art

[0004] Radio frequency signal or wave receiver circuits or receivers primarily have two types of cycles of operation: a wait period, during which no radio frequency signal containing information is received; and an active period, during which radio frequency signals conveying information are received. Because active periods are not always desirable, it is important for the receiver to be ready to receive signals. However, the circuitry capable of processing the signals can be energy-intensive.

[0005] It is therefore known to include a wake-up circuit which consumes less energy and is able to wake up the processing circuit upon reception of radio frequency waves. Summary of the Invention

[0006] A less power intensive RF receiver wake-up circuit is required.

[0007] One embodiment overcomes all or some of the disadvantages of known radio frequency receiver wake-up circuits.

[0008] One embodiment provides a radio frequency signal receiver circuit, including a main circuit configured to process radio frequency signals and a wake-up circuit configured to detect reception of radio frequency signals, the wake-up circuit including an automatic gain control loop, and the wake-up circuit configured to have two operating modes:

[0009] a first operating mode in which the setpoint voltage of the loop has a first substantially constant value, and

[0010] a second operating mode in which the setpoint voltage of the loop has a second value that depends on the supply voltage of the wake-up circuit.

[0011] According to one embodiment, the circuit includes an antenna that delivers a first signal to the wake-up circuit at a first node.

[0012] According to one embodiment, the wake-up circuit is configured to deliver a second signal on the second node instructing the master circuit to wake up.

[0013] According to one embodiment, the wake-up circuit includes a resistor coupled between a third node to which a power supply voltage is applied to the wake-up circuit and the second node.

[0014] According to one embodiment, the loop comprises a variable gain circuit coupled at its input to the first node and to the second node.

[0015] According to one embodiment, the loop comprises a circuit for controlling the gain of the variable gain circuit, the control circuit being coupled to the second node via an input and coupled to the set point voltage on another input.

[0016] According to one embodiment, the other input is coupled to the fourth node to which a voltage is applied and to the fifth node to which a voltage is applied via a selection element.

[0017] According to one embodiment, the fourth node is coupled to a sixth node to which a reference voltage is applied via a first voltage source, the first voltage source delivering a voltage having a first value on the fourth node.

[0018] According to one embodiment, the fifth node is coupled to the third node via a second voltage source, such that the voltage on the fifth node depends on the supply voltage.

[0019] According to one embodiment, the supply voltage is in the range of 0.1V to 5V.

[0020] According to one embodiment, the supply voltage of the main circuit is substantially equal to the supply voltage of the wake-up circuit.

[0021] According to one embodiment, the circuit is configured to operate in on-off keying or Manchester-type on-off keying.

[0022] Another embodiment provides an automatic gain control circuit configured to have two operating modes:

[0023] a first operating mode in which a setpoint voltage of the circuit has a substantially constant first value, and

[0024] A second operating mode in which the setpoint voltage has a second value that is dependent on the supply voltage of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The foregoing features and advantages and other features and advantages will be described by way of illustration and not limitation in the following description of specific embodiments with reference to the accompanying drawings, in which:

[0026] Figure 1 shows an example of a radio frequency wave receiver circuit to which the embodiments described below are applicable;

[0027] Figure 2 A portion of one embodiment of a radio frequency wave receiver circuit is schematically shown;

[0028] Figure 3 Shown Figure 2operation of the circuit; and

[0029] Figure 4 Shown Figure 2 Operation of the embodiment. DETAILED DESCRIPTION

[0030] In the various drawings, the same features are represented by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0031] For clarity, only the steps and elements that are useful for understanding the embodiments described herein are shown and described in detail.

[0032] Unless otherwise stated, when two elements are referred to as being connected together, this means a direct connection without any intermediate elements other than conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0033] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as terms "front", "back", "top", "bottom", "left", "right", etc., or when referring to relative position qualifiers, such as terms "upper", "lower", "upper", "lower", etc., or when referring to orientation qualifiers, such as "horizontal", "vertical", etc., it refers to the orientation shown in the figures.

[0034] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, preferably within 5%.

[0035] Figure 1 There is shown an example of a radio frequency (RF) wave or signal receiver circuit 1, to which the embodiments described below may apply. The circuit 1 forms part of an electronic device, such as a cellular phone, for example.

[0036] Radio frequency waves or signals are waves or signals with electromagnetic wave frequencies in the range of 3 kHz to 300 GHz. Radio frequency waves or signals include frequencies used by various radio communication devices, in particular mobile phones, WiFi or radio broadcasts, as well as signals intended for other purposes, such as radar or microwave ovens.

[0037] Circuit 1 is a radio frequency wave receiving circuit and includes antenna 3. Antenna 3 is configured to receive radio frequency waves.

[0038] Circuit 1 includes circuit 5 or a main circuit for receiving and processing waves received via antenna 3. Circuit 5 may further include a wave transmission circuit. Circuit 5 may include, for example, a microprocessor. Circuit 5 is thus coupled to antenna 3, preferably connected to antenna 3. Circuit 5 is configured to process the radio frequency signal RFS received by the antenna in an analog and / or digital manner.

[0039] Circuit 5 is powered by a power supply voltage VDD1. In other words, the circuit receives a voltage VDD1 applied, for example, between nodes 7 and 8. Circuit 5 is coupled to, preferably connected to, node 8, for example, which has a reference voltage applied thereto, such as ground (GND), and is coupled to, preferably connected to, node 7, which has a voltage VDD1 applied thereto. Voltage VDD1 is, for example, a power supply voltage delivered by an electronic device and used, for example, in another part of the device. For example, the power supply voltage is in the range of 0.2V to 6V.

[0040] Circuit 1 further includes a radio frequency wave receiving circuit 9 or auxiliary circuit. Circuit 9 is known as a wake-up radio circuit. Circuit 9 is configured to detect a radio frequency signal indicating that a signal that can be processed by main circuit 5 is about to be received. Main circuit 5 is then awakened to prepare to process the radio frequency signal. Circuit 9 is coupled to antenna 3, preferably connected to antenna 3, and receives the signal RFS received and transmitted by antenna 3. Circuit 9 is further coupled to circuit 5, preferably connected to circuit 5, and delivers a signal S (e.g., a square wave signal) to circuit 5, enabling circuit 5 to be awakened.

[0041] Circuit 9 is powered by power supply voltage VDD2. In other words, circuit 9 receives voltage VDD2 applied between node 8 and node 10, for example. Circuit 9 is coupled to node 8, preferably connected to node 8, which has a reference voltage applied thereto, such as ground (GND), and is coupled to node 10, preferably connected to node 10, which has voltage VDD2 applied thereto.

[0042] During operation of circuit 1, circuit 1 may not receive radio frequency waves for extended periods. During these periods, keeping main circuit 5 operational results in high power consumption. Therefore, it is known to use a wake-up circuit 9. Thus, when circuit 5 is off, in standby, or in low-power mode, circuit 9 remains operational. Circuit 9 receives and detects radio frequency signals and determines whether circuit 5 needs to be woken up.

[0043] In existing wake-up circuits, circuit 9 receives a power supply voltage VDD2 that is lower than voltage VDD1 and is generated specifically for circuit 9. However, generating a voltage specifically for circuit 9 requires the presence of additional circuitry, such as a linear voltage regulator, in circuit 1. Furthermore, due to the low power supply voltage, the linearity of circuit 9 may be affected.

[0044] Figure 2 A portion of an embodiment of a circuit 20 is schematically shown. The circuit 20 is an automatic gain control circuit. The circuit 20 is, for example, a radio frequency wave receiver. The circuit 20 is, for example, Figure 1 The circuit 1 is part of the wake-up circuit of the circuit 9, for example the first stage. In the example described here, the circuit 1 is in on-off keying or OOK. The circuit 1 can also operate in Manchester type on-off keying.

[0045] Circuit 20 includes an input node 22 at which a power supply voltage VDD2 is received. Figure 2 In the embodiment of the present invention, voltage VDD2 is, for example, in the range of 0.1V to VDD1, for example, in the range of 0.1V to 5V, for example, in the range of 1.7V to 3.7V. Power supply voltage VDD2 is, for example, a power supply voltage used in another circuit of the device. Voltage VDD2 is, for example, substantially equal to voltage VDD1. Circuit 20 includes an input node 24 having an input voltage RFS received thereon. Circuit 20 includes an output node 26 having an output voltage S' received thereon. Output voltage S' is then provided to a circuit (not shown) to be processed and used to generate Figure 1 For example, a signal S is processed digitally, not shown. The circuit 20 includes an input node 28 having a reference voltage GND received thereon.

[0046] Circuit 20 includes an automatic gain control loop. The loop includes a variable gain circuit or gain stage 30. Circuit 30 is, for example, a power sensor or a variable gain amplifier. Circuit 30 is coupled to, preferably connected to, node 24, and thus receives an input signal RFS. Circuit 30 is further coupled to, preferably connected to, output node 26, which delivers signal S'. Circuit 30 further includes a control input 32 at which circuit 30 receives information indicating a gain change. In other words, the gain of circuit 30 varies depending on the voltage applied to the control input.

[0047] The control loop includes circuit 34, which is configured to generate a signal for controlling circuit 30. Control input 32 is coupled to, and preferably is connected to, the output of circuit 34. Circuit 34 is coupled via an input to, and preferably is connected to, output node 26. Circuit 34 is coupled via another input to, and preferably is connected to, node 36, which has a setpoint voltage applied thereto. The gain of circuit 30 is thus modified according to the difference between the voltage at node 26 and the setpoint voltage at node 36.

[0048] Circuit 20 includes a resistor 38 coupled between node 22 and node 26. In other words, one terminal of resistor 38 is coupled to node 22, preferably connected to node 22, and the other is coupled to node 26, preferably connected to node 26, and thus coupled to the output node of circuit 30.

[0049] Circuit 20 includes two voltage sources 40 and 42. Voltage source 42 is coupled between node 28 and node 44. In other words, one terminal of source 42 (preferably the positive terminal (+)) is coupled to node 36, preferably connected to node 36, while the other terminal of source 42 (preferably the negative terminal (-)) is coupled to node 28, preferably connected to node 28. Source 42 delivers a preferably substantially constant voltage V42 between nodes 44 and 28, for example, in the range of 0V to 1.5V, for example, substantially equal to 0.2V. Voltage source 40 is coupled between node 22 and node 46. In other words, one terminal of source 40 (preferably the positive terminal (+)) is coupled to node 22, preferably connected to node 22, while the other terminal of source 40 (preferably the negative terminal (-)) is coupled to node 46, preferably connected to node 46. Source 40 delivers a preferably substantially constant voltage V40 between nodes 44 and 28 , for example in the range from 0V to VDD2 , for example substantially equal to 1.2V.

[0050] Therefore, the voltage at the node 44 is equal to V42 , ie, substantially equal to 0.2V, for example, and the voltage at the node 46 is substantially equal to VDD2 − V40 , ie, substantially equal to VDD2 −1.2V, for example.

[0051] Circuit 20 includes a selection circuit or element 48. On one side of circuit 48, one terminal of circuit 48 is coupled to, preferably connected to, node 46, and another terminal of circuit 48 is coupled to, preferably connected to, node 44.

[0052] In a first operating mode, referred to as a high linearity operating mode, node 36 is connected to node 44 via selection circuit 48. The voltage at node 36 is therefore substantially equal to the voltage at node 44. The value of the setpoint voltage is then substantially constant. The value of the setpoint voltage is independent of the supply voltage VDD2 of circuit 20.

[0053] In the second operating mode, referred to as the low-power operating mode, node 36 is connected to node 46 via selection circuit 48. The voltage at node 36 is therefore substantially equal to the voltage at node 46. The value of the setpoint voltage then depends on the supply voltage VDD2. The higher the supply voltage, the higher the setpoint voltage.

[0054] Switching from one operating mode to another corresponds to switching between the states of the selection circuit 48. In other words, the switching control from one operating mode to another is performed by controlling the selection circuit 48. Switching from one operating mode to another can be performed manually by a user or automatically by software, for example.

[0055] Figure 3 Shown Figure 2 More precisely, Figure 3 The current consumed by the circuit 20 is shown in amperes as a function of the value of the supply voltage VDD2 (in volts).

[0056] Figure 3 A curve 50 is shown which illustrates the power consumption of the circuit 20 during operating periods in which the circuit 20 receives no radio frequency signals. Figure 3 A curve 52 is shown which illustrates the power consumption of the circuit 20 during a period B of the first operating mode, ie the low power operating mode. Figure 3 Curve 54 is shown, illustrating the maximum power consumption of circuit 20 during the high linearity mode of operation.

[0057] As shown by curve 50 , when the antenna is not receiving a radio frequency signal, the power consumption is substantially constant and, in this example, substantially equal to 1 μA.

[0058] In the low-power operating mode represented by curve 52, the maximum power consumption that can be achieved in the presence of a radio frequency signal and / or an interfering channel is substantially constant and, in this example, substantially equal to 2 μA. The maximum power consumption represented by curve 52 is greater than the power consumption represented by curve 50. In the absence of a signal, the consumption in the low-power mode is substantially equal to 1 μA and corresponds to curve 50.

[0059] The power consumption in the high linearity operating mode depends on the supply voltage VDD2. The power consumption increases according to the supply voltage. In the absence of a signal, the consumption in the high linearity mode is substantially equal to 1 μA and corresponds to the curve 50.

[0060] Therefore, in Figure 4 In the example of , the power consumption in the low power mode is less than the power consumption in the high linearity mode. In addition, the higher the power supply voltage VDD2 is, the higher the power consumption in the high linearity mode is.

[0061] Figure 4 Shown Figure 2 More precisely, Figure 4 The magnitude of the range of possible values for the input signal (ie the radio frequency signal or the signal of the interfering channel) is shown as a function of the value of the supply voltage VDD2 in volts.

[0062] Figure 4 A curve 60 is shown which illustrates the difference during the second mode of operation (ie, the low power mode of operation). Figure 4 A curve 62 is shown which illustrates the difference during a first operating mode, ie a high linearity operating mode.

[0063] The magnitude of the range of possible values for the input signal is independent of the value of the supply voltage VDD2 in the low power mode of operation as shown by curve 60. Thus, the magnitude is substantially constant regardless of the value of the supply voltage VDD2.

[0064] In the high linearity operating mode, the magnitude of the range of possible values for the input signal depends on the value of the supply voltage VDD2. The higher the supply voltage, the greater the magnitude of the range of possible values for the input signal, in other words, the higher the accuracy of the RF signal.

[0065] Compared to the high-linearity operating mode, the low-power operating mode has lower power consumption but lower voltage dynamics. Therefore, the most suitable operating mode can be selected based on the device's application. For the same application, one or the other operating mode can also be selected for certain time periods. For example, certain operating periods may be determined to require greater dynamics than others.

[0066] An advantage of the described embodiments is that for a wake-up circuit of a radio frequency receiver circuit, it is possible to select between a power-intensive operating mode with large voltage dynamics and a low-power operating mode with limited voltage dynamics.

[0067] Another advantage of the described embodiment is that the wake-up circuit can use the supply voltage used in another part of the device, for example, the same power supply as the main circuit of the receiver. Therefore, a linear voltage regulator does not need to generate a supply voltage with a value specific to the radio frequency wave receiver circuit.

[0068] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0069] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A radio frequency signal receiver circuit, comprising: a main circuit configured to process a radio frequency signal; as well as a wake-up circuit configured to detect reception of the radio frequency signal, the wake-up circuit comprising an automatic gain control loop, the wake-up circuit being configured to have a first operating mode in which a setpoint voltage of the loop has a substantially constant first value and a second operating mode in which the setpoint voltage of the loop has a second value that depends on a supply voltage of the wake-up circuit. 2 . The receiver circuit of claim 1 , further comprising an antenna terminal configured to deliver a first signal to the wake-up circuit on a first node. 3 . The receiver circuit of claim 2 , wherein the wake-up circuit is configured to deliver a second signal on a second node commanding the master circuit to wake up. 4 . The receiver circuit of claim 3 , wherein the wake-up circuit comprises a resistor coupled between a third node to which the power supply voltage is applied to the wake-up circuit and the second node.

5. The receiver circuit of claim 4, wherein the loop comprises a variable gain circuit having a first input coupled to the first node and an output coupled to the second node.

6. The receiver circuit of claim 5 , wherein the loop comprises a control circuit configured to control the gain of the variable gain circuit, the control circuit having a first input coupled to the second node and a second input coupled to a setpoint voltage node configured to receive a setpoint voltage.

7. The receiver circuit of claim 6, wherein the second input of the control circuit is coupled to a fourth node and a fifth node to which voltages are applied via a selection circuit, the fourth node and the fifth node to which voltages are applied having the first value and the second value, respectively. 8 . The receiver circuit of claim 7 , wherein the fourth node is coupled to a sixth node to which a reference voltage is applied by a first voltage source, the first voltage source being configured to deliver a voltage having the first value on the fourth node.

9. The receiver circuit of claim 7, wherein the fifth node is coupled to the third node through a second voltage source such that the voltage on the fifth node depends on the supply voltage. 10 . The receiver circuit of claim 2 , further comprising an antenna coupled to the antenna terminal and configured to deliver the first signal to the wake-up circuit on the first node via the antenna terminal.

11. The receiver circuit of claim 1, wherein the power supply voltage is in the range from 0.1V to 5V. 12 . The receiver circuit of claim 1 , wherein a power supply voltage of the main circuit is substantially equal to the power supply voltage of the wake-up circuit.

13. The receiver circuit of claim 1, wherein the receiver circuit is configured to operate in on-off keying.

14. The receiver circuit of claim 1, wherein the receiver circuit is configured to operate in Manchester-type on-off keying.

15. An automatic gain control circuit, comprising: a first output configured to deliver an output signal; as well as a control input configured to receive a gain control signal, wherein a gain of the automatic gain control circuit is based on a voltage difference between the output signal and the gain control signal, wherein in a first operating mode, a setpoint voltage of the automatic gain control circuit has a substantially constant first value, and in a second operating mode, the setpoint voltage has a second value that is dependent on a supply voltage of the automatic gain control circuit. 16 . The automatic gain control circuit of claim 15 , wherein the automatic gain control circuit is configured to receive the supply voltage at the first output via a resistor.

17. A method for operating a circuit, comprising: receiving a first supply voltage at a first supply node; delivering an output signal at a first output of the automatic gain control circuit; receiving a gain control signal at a control input of the automatic gain control circuit, wherein a gain of the automatic gain control circuit is based on a voltage difference between the first output and the control input; in a first operating mode, setting a setpoint voltage at the first output to a substantially constant first value; as well as In a second operating mode, the setpoint voltage at the first output is set to a second value, the second value being dependent on the first supply voltage.

18. The method according to claim 17, further comprising: receiving an input signal; Powering the main circuit with the first power supply voltage; Processing the input signal with the main circuit; as well as The main circuit is awakened using the output signal.

19. The method of claim 18, receiving the input signal with an antenna coupled to the automatic gain control circuit and the main circuit.

20. The method of claim 17, wherein during the first operating mode, the gain control signal is provided using a first voltage source coupled to a reference node, and during the second operating mode, the gain control signal is provided using a second voltage source coupled to the first power supply node.

21. The method of claim 17 , further comprising powering the automatic gain control circuit using the first supply voltage, wherein the first supply voltage varies within a first voltage range, and wherein during the first operating mode, the automatic gain control circuit consumes a substantially constant current as the first supply voltage varies within the voltage range.

22. The method of claim 21, wherein the first voltage range comprises a voltage range between 1.8V and 3.6V.

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