Method, apparatus, processor and computer-readable storage medium for implementing high-precision coefficient update processing in channel simulation
By performing the decimal accumulation and carry processing of the coefficient update time in the channel simulator on the FPGA side, the problems of accuracy missing and error accumulation in the prior art are solved, and high-precision coefficient update signal generation and accurate coefficient access and simulation processes are realized.
Patent Information
- Application Number
- CN202211589822.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-12
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2042-12-12
AI Technical Summary
The prior art cannot convert the coefficient update time into the coefficient update signal with high accuracy in channel simulators, resulting in the absence of accuracy and accumulation of errors, affecting the subsequent coefficient access and simulation process.
By performing the decimal accumulation of carry processing on the received coefficient update time on the FPGA side, the carry number and the complete update length are generated, and a high-precision coefficient update signal is achieved.
The accuracy of FPGA terminal processing of coefficient update time is improved, error accumulation is reduced, and the accuracy of subsequent coefficient access and simulation processes is ensured.
Smart Images
Figure CN115941067B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of FPGA hardware, and more particularly to the field of digital signal processing. Specifically, it refers to a method, device, processor, and computer-readable storage medium for implementing high-precision coefficient update processing in channel simulation. Background Art
[0002] During the current coefficient update process of the channel simulator, the host computer sends the coefficients to the FPGA, and the FPGA performs the main large-scale channel simulation calculation process. There will be a corresponding coefficient sending time between the host computer starting to send the first set of coefficients and starting to send the second set of coefficients, which is called the coefficient update time. The host computer will inform the FPGA side of the coefficient update time, and the FPGA side will generate a corresponding coefficient update signal according to each coefficient update time. The generation of the coefficient update signal has an indication effect on the subsequent access of the coefficients in the FPGA. Therefore, a mechanism is needed in the FPGA to accurately and highly precisely convert the received coefficient update time from the host computer into a coefficient update signal.
[0003] The existing technology for the processing of this mechanism is mainly based on continuously accumulating and counting the coefficient clock of the FPGA. Whenever the accumulated value reaches the coefficient update time, an update signal is generated. The coefficient clock of the FPGA is a periodically changing clock signal. We cannot use the method of cumulative counting to achieve a coefficient update time with a precision that is not an integer multiple of this clock cycle. Therefore, the counted update time is always limited by the clock signal, and there will be a precision problem with this mechanism, that is, the minimum precision of the coefficient update time that the FPGA can handle is one cycle time of the FPGA coefficient clock. When the coefficient update signal is generated multiple times, the error caused by this precision loss will continuously accumulate and become more and more serious. The inaccurate coefficient update signal generated in this case will have varying degrees of impact on subsequent functions such as coefficient access and simulation. Summary of the Invention
[0004] The object of the present invention is to overcome the above-mentioned disadvantages of the prior art, and provide a method, device, processor, and computer-readable storage medium for implementing high-precision coefficient update processing in channel simulation that have small errors, high precision, and high accuracy.
[0005] In order to achieve the above object, the method, device, processor, and computer-readable storage medium of the present invention for implementing high-precision coefficient update processing in channel simulation are as follows:
[0006] The method for implementing high-precision coefficient update processing in channel simulation is mainly characterized in that the method includes the following steps:
[0007] (1) The host computer sends a column of coefficients to the FPGA side through PCIe and notifies the FPGA side of the updated time after processing;
[0008] (2) Generate an update signal update;
[0009] (3) Accumulate and carry the fractional part of the update time;
[0010] (4) Generate a carry number integer;
[0011] (5) Generate a complete update length Length.
[0012] Preferably, the updated time after processing in step (1) is the update length, and the update length is divided into an integer part Length_m and a fractional part Length_n.
[0013] Preferably, step (2) specifically includes the following steps:
[0014] (2.1) If the run signal run is set high, the system runs orderly and normally issues coefficients;
[0015] (2.2) The update counter count continuously counts every clock cycle. If the pause signal pause or the run signal run is set low, the counting process is paused;
[0016] (2.3) When the count of the update counter count is equal to the update length Length, the update counter count is cleared, and at the same time, an update signal update is generated, which is a pulse signal.
[0017] Preferably, step (3) specifically includes the following steps:
[0018] (3.1) Use the fractional part Length_n of the update length Length as the initial value to be input into the accumulator for accumulation. The enable en of the accumulator operation is the update signal update generated every once in a while;
[0019] (3.2) Perform a pipelining operation on the output result out of the accumulator, and generate a new data out_delay after pipelining the output result out by one clock cycle;
[0020] (3.3) Compare the output result out with out_delay. If out is less than out_delay, the fractional part Length_n of the update length Length has completed the complete fractional accumulation and carry process, and a pulse signal out_done is generated.
[0021] Preferably, step (4) is specifically:
[0022] If the pulse signal out_done is detected, the carry integer is pulled high and remains 1 until the next update signal update is encountered.
[0023] Preferably, step (5) is specifically as follows:
[0024] Adding the integer part Length_m of the update length to the carry integer gives the complete update length Length for each time.
[0025] The device for implementing high-precision coefficient update processing applied to channel simulation is characterized in that the device includes:
[0026] A processor configured to execute computer-executable instructions;
[0027] A memory storing one or more computer-executable instructions, which, when executed by the processor, implement each step of the method for implementing high-precision coefficient update processing applied to channel simulation as described above.
[0028] The processor for implementing high-precision coefficient update processing applied to channel simulation is characterized in that the processor is configured to execute computer-executable instructions, which, when executed by the processor, implement each step of the method for implementing high-precision coefficient update processing applied to channel simulation as described above.
[0029] The computer-readable storage medium is characterized in that a computer program is stored thereon, and the computer program can be executed by a processor to implement each step of the method for implementing high-precision coefficient update processing applied to channel simulation as described above.
[0030] By adopting the method, device, processor and computer-readable storage medium for implementing high-precision coefficient update processing applied to channel simulation of the present invention, compared with the prior art, it has higher precision and accuracy, makes up for the increasing error caused by insufficient precision, can have a smaller processing precision for the coefficient update time received at the FPGA end, makes the generated coefficient update signal more accurate, and makes the subsequent coefficient access and simulation process more accurate. Brief Description of the Drawings
[0031] Figure 1 It is the complete structure diagram of fractional carry counting for the method of implementing high-precision coefficient update processing applied to channel simulation of the present invention.
[0032] Figure 2Waveform diagram of the update signal update generation process of the method for implementing high-precision coefficient update processing in channel simulation according to the present invention.
[0033] Figure 3 Waveform diagram of the fractional accumulation carry process of the method for implementing high-precision coefficient update processing in channel simulation according to the present invention.
[0034] Figure 4 Waveform diagram of the carry digit integer generation process of the method for implementing high-precision coefficient update processing in channel simulation according to the present invention.
[0035] Figure 5 Waveform diagram of the complete update length length generation process of the method for implementing high-precision coefficient update processing in channel simulation according to the present invention. Detailed implementation manners
[0036] In order to more clearly describe the technical content of the present invention, the following will be further described in conjunction with specific embodiments.
[0037] The method for implementing high-precision coefficient update processing in channel simulation according to the present invention includes the following steps:
[0038] (1) The host computer sends a column of coefficients to the FPGA end through PCIe and informs the FPGA end of the update time after processing;
[0039] (2) Generate the update signal update;
[0040] (3) Accumulate and carry the fractional part of the update time;
[0041] (4) Generate the carry digit integer;
[0042] (5) Generate the complete update length Length.
[0043] As a preferred embodiment of the present invention, in the step (1), the update time after processing is the update length, and the update length is divided into an integer part Length_m and a fractional part Length_n.
[0044] As a preferred embodiment of the present invention, the step (2) specifically includes the following steps:
[0045] (2.1) If the run signal run is set high, the system runs orderly and normally issues coefficients;
[0046] (2.2) The update counter count continuously counts in each clock cycle. If the pause signal pause or the run signal run is set low, the counting process is paused;
[0047] (2.3) When the count of the update counter count is equal to the update length Length, the update counter count is cleared, and at the same time, an update signal update is generated, which is a pulse signal.
[0048] As a preferred embodiment of the present invention, step (3) specifically includes the following steps:
[0049] (3.1) The fractional part Length_n of the update length Length is used as the initial value and input to the accumulator for accumulation. The enable en of the accumulator operation is the update signal update generated every once in a while;
[0050] (3.2) A pipelining operation is performed on the output result out of the accumulator, and a new data out_delay is generated after delaying the output result out by one clock cycle.
[0051] (3.3) Compare the output result out with out_delay. If out is less than out_delay, it means that the fractional part Length_n of the update length Length has completed a complete fractional accumulation carry process, and a pulse signal out_done is generated.
[0052] As a preferred embodiment of the present invention, step (4) is specifically:
[0053] If the pulse signal out_done is detected, the carry integer is pulled high and maintained at 1 until the next update signal update is encountered.
[0054] As a preferred embodiment of the present invention, step (5) is specifically:
[0055] Add the integer part Length_m of the update length to the carry integer, which is the complete update length Length each time.
[0056] The device for implementing high-precision coefficient update processing applied to channel simulation according to the present invention, wherein the device includes:
[0057] A processor configured to execute computer-executable instructions;
[0058] A memory storing one or more computer-executable instructions, and when the computer-executable instructions are executed by the processor, each step of the method for implementing high-precision coefficient update processing applied to channel simulation as described above is realized.
[0059] The processor for implementing high-precision coefficient update processing applied to channel simulation according to the present invention, wherein the processor is configured to execute computer-executable instructions, and when the computer-executable instructions are executed by the processor, each step of the method for implementing high-precision coefficient update processing applied to channel simulation as described above is implemented.
[0060] The computer-readable storage medium of the present invention, on which a computer program is stored, and the computer program can be executed by a processor to implement each step of the method for implementing high-precision coefficient update processing applied to channel simulation as described above.
[0061] In the technical solution of the present invention, a pulse update signal is accurately generated at intervals according to the input update length. For example, if the input update length is 100.1 and the clock period is 10 ns, then according to this technical solution, a pulse update signal will be generated every 1001 ns precisely. In the technical solution of the present invention, the counter is for finally generating the update signal, and the accumulation is for the final carry operation of the fractional part.
[0062] In the specific implementation manner of the present invention, it aims to break through the shackles of the FPGA coefficient clock cycle. After the FPGA receives the coefficient update time sent by the host computer, the processing accuracy of the FPGA can be much less than the time of one cycle of the FPGA coefficient clock. It makes up for the serious error caused by the accumulation of precision loss after generating the coefficient update signal multiple times, making the subsequent coefficient access and simulation more rigorous.
[0063] This implementation method makes up for the loss of precision generated in the counting process based on the coefficient clock by using the method of accumulation and rounding. The host computer sends a coefficient update time that is not an integer multiple of the coefficient clock cycle. After the FPGA receives it, the coefficient update time is split into two parts. The first part is the coefficient update time that is the largest integer multiple of the coefficient clock cycle, and the second part is the coefficient update time that is less than one coefficient clock cycle. Under the system clock, continuous accumulation and counting are performed. When the accumulated value reaches the first part, a coefficient update signal is generated. The second part is temporarily stored and accumulated with the second part of the coefficient update time sent the second time, and so on. Until the accumulated time of the second part of n coefficient update times can exceed one coefficient clock cycle, a carry operation is started, and the first part of the nth coefficient update time is incremented by one, realizing the accumulation and rounding of the decimal part, thereby eliminating the serious error caused by the accumulation of precision loss after generating the coefficient update signal multiple times.
[0064] The present invention specifically includes the following steps:
[0065] Coefficient distribution process: The host computer sends a column of coefficients to the FPGA side through PCIe, and at the same time notifies the FPGA side of the update time used to send this column of coefficients. The update time has been processed in the host computer, and the data actually sent to the FPGA side is the value obtained by dividing the update time by the coefficient clock cycle T of the FPGA side, that is, the update length. And this update length is divided into two parts and sent, namely the integer part Length_m and the decimal part Length_n;
[0066] Process of generating the update signal update: The run signal run is a level signal. When it is set high, it indicates that the system is running orderly and the coefficients are normally distributed. At this time, the update counter count performs an uninterrupted counting process every clock cycle. The counting process pauses when the pause signal pause or the run signal run is set low. When the update counter count counts to be equal to the update length Length, the update counter count is cleared, and at the same time, an update signal update is generated. This signal is a pulse signal. The update signal update represents that this column of coefficients has been sent, and at the same time indicates the coming of the next coefficient distribution process. When the subsequent coefficient access module and simulation module receive this update signal update, they start to store the coefficients and perform corresponding simulation operations;
[0067] Process of decimal accumulation carry: The decimal part Length_n of the update length Length is sent to the accumulator as the initial value for accumulation, and the output result out of the accumulator's accumulation of Length_n is obtained, which is a data signal. The enable en of the accumulator operation is the update signal update generated every once in a while, and the output result out is pipelined. After the output result out is pipelined once, a new data out_delay is generated. Compare out with out_delay. Whenever out is less than out_delay, it means that the decimal part Length_n of the update length Length has completed a complete decimal accumulation carry process. At this time, a pulse signal out_done is generated to indicate the completion of this process;
[0068] Process of generating the carry number integer: The carry number integer will show the characteristics of a level signal. Each time it encounters the pulse signal out_done representing the completion of the decimal accumulation carry process, the carry number integer will be pulled high until it encounters the next update signal update and then be pulled low again. That is, the carry number integer is pulled high throughout the process of generating this update signal update and remains at 1;
[0069] Process of generating the complete update length: Each complete update length can be expressed as the integer part of the update length, Length_m, plus the carry integer.
[0070] For the specific implementation solution of this embodiment, reference can be made to the relevant descriptions in the above embodiments, which will not be elaborated here.
[0071] It can be understood that the same or similar parts in the above embodiments can be referred to each other, and for the content not described in detail in some embodiments, reference can be made to the same or similar content in other embodiments.
[0072] It should be noted that in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "a plurality of" refers to at least two.
[0073] Any process or method description shown in the flowchart or described in other ways herein can be understood to represent a module, segment, or part of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present invention includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in the reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the technical field to which the embodiments of the present invention belong.
[0074] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following well-known technologies in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits with appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0075] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried out in the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the corresponding program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.
[0076] In addition, in each embodiment of the present invention, each functional unit may be integrated into a processing module, may exist separately physically for each unit, or two or more units may be integrated into one module. The above integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.
[0077] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc.
[0078] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.
[0079] By adopting the method, device, processor, and computer-readable storage medium of the present invention for implementing high-precision coefficient update processing in channel simulation, compared with the prior art, it has higher precision and accuracy, makes up for the increasing error caused by insufficient precision, can have a smaller processing precision for the coefficient update time received at the FPGA end, makes the generated coefficient update signal more accurate, and makes the subsequent coefficient access and simulation processes more accurate.
[0080] In this specification, the present invention has been described with reference to its specific embodiments. However, it is obvious that various modifications and transformations can still be made without departing from the spirit and scope of the present invention. Therefore, the specification and the drawings should be regarded as illustrative rather than restrictive.
Claims
1. A method for implementing high-precision coefficient update processing in channel simulation, characterized in that, The method described above includes the following steps: (1) The host computer sends a column of coefficients to the FPGA side through PCIe and notifies the FPGA side of the updated time after processing; (2) Generate an update signal update; (3) Accumulate and carry the fractional part of the update time; (4) Generate a carry number integer; (5) Generate a complete update length Length; The specific steps of step (2) include the following steps: (2.1) If the run signal run is set high, the system runs orderly and coefficients are normally issued; (2.2) The update counter count continuously counts every clock cycle. If the pause signal pause or the run signal run is set low, the counting process is paused; (2.3) When the count of the update counter count is equal to the update length Length, the update counter count is cleared, and at the same time, an update signal update is generated, which is a pulse signal; The specific steps of step (3) include the following steps: (3.1) Use the fractional part Length_n of the update length Length as the initial value to be input into the accumulator for accumulation. The enable en for the accumulator to run is the update signal update generated every once in a while; (3.2) Perform a pipelining operation on the output result out of the accumulator, and generate a new data out_delay after pipelining the output result out by one clock cycle; (3.3) Compare the output result out with out_delay. If out is less than out_delay, the fractional part Length_n of the update length Length has completed the complete fractional accumulation and carry process, and a pulse signal out_done is generated.
2. The method for implementing high-precision coefficient update processing in channel simulation according to claim 1, wherein In step (1), the updated time after processing is the update length, and the update length is divided into an integer part Length_m and a fractional part Length_n.
3. The method for implementing high-precision coefficient update processing in channel simulation according to claim 1, wherein The specific step of step (4) is: If the pulse signal out_done is detected, the carry number integer is pulled high and remains 1 until the next update signal update is encountered.
4. The method for implementing high-precision coefficient update processing applied to channel simulation according to claim 1, wherein The specific step of step (5) is: Add the integer part Length_m of the update length to the carry number integer, which is the complete update length Length each time.
5. An apparatus for implementing high-precision coefficient update processing applied to channel simulation, characterized in that, The device described above includes: A processor configured to execute computer-executable instructions; A memory storing one or more computer-executable instructions, and when the computer-executable instructions are executed by the processor, each step of the method for implementing high-precision coefficient update processing applied to channel simulation described in any one of claims 1 to 4 is realized.
6. A processor for implementing high-precision coefficient update processing applied to channel simulation, characterized in that, The processor is configured to execute computer-executable instructions, and when the computer-executable instructions are executed by the processor, each step of the method for implementing high-precision coefficient update processing applied to channel simulation described in any one of claims 1 to 4 is realized.
7. A computer-readable storage medium, characterized in that, A computer program is stored thereon, and the computer program can be executed by a processor to implement each step of the method for implementing high-precision coefficient update processing in channel simulation according to any one of claims 1 to 4.
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