A method for optimizing synchronization accuracy of a clock synchronization system

Abstract

The application provides a clock synchronization system synchronization precision optimization method, and belongs to the network communication field. According to the IEEE1588 protocol, the message interaction of the end-to-end transmission mode is carried out, and the time stamp recorded in each message and the transmission delay are obtained from the slave device. The slave device uses a filtering algorithm to process the forward transmission delay and the reverse transmission delay, combines a clock deviation calculation formula, uses the time stamp in the message and the processed transmission delay to calculate the clock deviation of the slave device and the master clock, and finally adjusts the local clock by using the calculated clock deviation. The method solves the problem that the asymmetric delay existing in the message transmission process in the clock synchronization system of the IEEE1588 protocol end-to-end transmission mode influences the clock synchronization precision of the master node and the slave device, improves the time synchronization precision between the devices in the network communication system, and has a wide application prospect.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of network communication, and particularly relates to a synchronization precision optimization method for a clock synchronization system in an IEEE1588 protocol end-to-end transmission mode. BACKGROUND

[0002] In an industrial network communication system, there are various devices such as monitoring servers, switches, controllers and wireless routers. In order to make the data and information transmitted between various devices in the network have logicality, security and traceability, the various devices in the network need to have the same clock reference. This requirement for clock synchronization promotes the birth and development of the IEEE1588v2 protocol. The IEEE1588 protocol is a method for synchronizing the clocks of network devices in a distributed system. It can achieve sub-microsecond time synchronization precision without adding additional hardware devices, by exchanging message data packets between network devices. Therefore, it has been widely applied in various industries such as power transmission networks, wireless transmission networks, Internet of Things and industrial control networks.

[0003] The end-to-end transmission mode is the most basic and widely used mode in the IEEE1588 protocol. The clocks of network devices can be calculated by the interaction of four types of clock synchronization messages, namely Sync messages, Follow-up messages, Delay-Req messages and Delay-Resp messages, and then adjusted to make the devices in the network have the same clock reference. In this mode, the transmission of clock synchronization messages in the network is symmetrical by default, that is, the transmission time of clock synchronization messages in both directions between devices is the same. However, in actual applications, the transmission delays of data messages in the same path in both directions are not the same, and the difference in transmission delays in both directions is affected by various conditions such as network congestion, uplink and downlink transmission rates, and asymmetric routing.

[0004] The asymmetry of the link can have a huge and unstable impact on clock synchronization. Therefore, a transparent clock is added in the IEEE1588 v2 protocol. The transparent clock can add the transmission time of clock synchronization messages during device forwarding to the message, thereby improving the clock synchronization precision between devices. Currently, the mainstream network transmission devices support the transparent clock function. Although the transparent clock function can fundamentally solve the problem of asymmetric link delay, when the network has abnormal conditions such as network congestion, partial network device failure and re-routing path planning, there is a large error between the transmission delay added by the transparent clock in the clock synchronization message and the actual transmission delay. If the clock offset between devices is directly calculated using the transmission delay in the clock synchronization message, and the local clock is adjusted accordingly, it will affect the clock synchronization precision between devices. SUMMARY

[0005] In view of the above problems in the prior art, the application provides a clock synchronization system synchronization precision optimization method, which can improve the clock synchronization precision between network devices in a clock synchronization system in an end-to-end transmission mode.

[0006] The technical scheme adopted by the application to achieve the above object is:

[0007] A clock synchronization system synchronization precision optimization method, the clock synchronization system being an IEEE1588 protocol end-to-end transmission mode clock synchronization system, comprising the following steps:

[0008] The master node and the slave node devices in the clock synchronization system perform packet interaction in an end-to-end transmission mode according to the IEEE1588 protocol.

[0009] After the slave node device obtains the time stamp and the transmission delay recorded in each packet, the transmission delay is filtered, and the clock deviation from the master clock is calculated according to the time stamp and the filtered transmission delay.

[0010] The local clock is adjusted by using the calculated clock deviation.

[0011] Further, the master node and the slave node devices in the clock synchronization system perform packet interaction in an end-to-end transmission mode according to the IEEE1588 protocol, and the specific mode is that the master node sends Sync packets and Follow-up packets to the slave node device, the slave node device sends Delay-Req packets to the master node after receiving the packets, and the master node replies Delay-Resp packets immediately after receiving the Delay-Req packets sent by the slave node device.

[0012] Further, the transmission devices between the master node and the slave node devices in the clock synchronization system are transparent clock devices, and the residence time of the packets in the transmission devices during the transmission process is added in the packets in the form of a time stamp.

[0013] Further, the transmission delay includes a forward transmission delay delay ms from the master node to the slave node device, and a reverse transmission delay delay sm from the slave node device to the master node.

[0014] Further, the slave node device internally stores and maintains the forward transmission delay delay ms and the reverse transmission delay delay sm during the historical packet interaction process.

[0015] Further, the slave node device obtains the time stamp recorded in each message and the transmission delay, filters the transmission delay, and calculates the clock deviation from the master clock according to the time stamp and the processed transmission delay, in a specific manner as follows:

[0016] The obtained forward transmission delay delay ms and the reverse transmission delay delay sm are compared with the time t max required for transmission along the longest transmission path in the network. max If the transmission delay in any direction is greater than 2t max , the time stamp and the transmission delay obtained in the current message interaction process are discarded, and the current clock adjustment is exited, and the next message interaction is performed.

[0017] If the transmission delays in both directions are less than 2t ms , the forward transmission delay delay sm and the reverse transmission delay delay ms are selected, a window size M is set, and the weighted average of the continuous M historical transmission delays including the current forward transmission delay delay sm and the reverse transmission delay delay are calculated. Then, the clock deviation between the slave node and the master node is calculated according to the clock deviation calculation formula in the IEEE1588 protocol, using and the time stamp recorded in the message.

[0018] A time synchronization optimization device includes a memory and a processor; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory, and in the execution process, the clock synchronization system synchronization precision optimization method according to any one of claims 1-6 is realized.

[0019] A computer readable storage medium, the storage medium stores a computer program, when the computer program is executed by a processor, the clock synchronization system synchronization precision optimization method according to any one of claims 1-6 is realized.

[0020] The beneficial effects of the present application are as follows:

[0021] 1. The time synchronization adjustment speed is fast. In the method, when the transmission delay in any direction is greater than twice the longest transmission path transmission time, the slave node exits the clock adjustment; the clock deviation calculated in the clock synchronization process due to network congestion and other reasons has a large error, and the local clock of the slave node oscillates after using the clock deviation with a large error to adjust the local clock, so that the local clock of the slave node is adjusted to a stable state faster, and the adjustment speed of the time synchronization between the master and slave nodes is improved.

[0022] 2. The clock synchronization precision is high. The transmission equipment in the clock synchronization system of the method records the transmission time delay of the message between the master and slave nodes in both directions in the message, and the transmission time delay in both directions is filtered and processed, so that the influence of asymmetric delay in the clock synchronization process between the master and slave nodes is removed, and the clock synchronization precision between the master and slave nodes in the clock synchronization system is improved.

[0023] 3. Easy to implement. The clock synchronization process and the filtering algorithm for transmission time delay in the method are based on mature clock synchronization technology and data processing technology, and the technical difficulty of developing and implementing the method is relatively small, and the method has low requirements for the processing capacity of the hardware system platform, and can be applied to various industrial control system platforms, and has strong universality. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a clock synchronization system structure diagram of an embodiment of the application.

[0025] Figure 2 is a whole flow chart of an embodiment of the application.

[0026] Figure 3 is a clock synchronization principle diagram of the IEEE1588 protocol end-to-end transmission mode.

[0027] Figure 4 is a flow chart of transmission time delay filtering processing in an embodiment of the application. DETAILED DESCRIPTION

[0028] The application will be further described in detail below with reference to the drawings and embodiments.

[0029] A clock synchronization system synchronization precision optimization method is used to improve the clock synchronization precision between network devices in an end-to-end transmission mode clock synchronization system, and includes the following steps:

[0030] The master node and the slave node equipment in the clock synchronization system exchange messages according to the end-to-end transmission mode of the IEEE1588 protocol, and the slave node equipment obtains the time stamp and the transmission delay recorded in each message.

[0031] The master node and the slave node equipment in the clock synchronization system exchange messages according to the end-to-end transmission mode of the IEEE1588 protocol. First, the master node sends Sync messages and Follow-up messages to the slave node equipment, and the slave node equipment sends Delay-Req messages to the master node after receiving the messages. The master node replies with Delay-Resp messages immediately after receiving the Delay-Req messages from the slave node equipment.

[0032] The master node equipment in the clock synchronization system fully supports the IEEE1588 protocol, that is, it can send and receive corresponding messages according to the IEEE1588 protocol standard requirements, and add the time of sending and receiving the messages in the form of time stamp in the specified position of the corresponding message.

[0033] The transmission equipment between the master node and the slave node equipment in the clock synchronization system is a transparent clock equipment, which can add the residence time of the message in the transmission equipment during the forward transmission process and the reverse transmission process between the master node and the slave node equipment in the form of time stamp in the corresponding position of the message.

[0034] After the slave node equipment extracts the forward transmission delay and the reverse transmission delay between the master node and the slave node equipment recorded in the message, it filters the transmission delay using a filtering algorithm. The specific process of the filtering algorithm mainly includes the following two steps:

[0035] First step: compare the obtained forward transmission delay delay ms and the reverse transmission delay delay sm with the time t max required for transmission along the longest transmission path in the network. If the transmission delay in any direction is greater than 2t max , discard the time stamp and transmission delay obtained in this message exchange process, exit this clock adjustment, and proceed to the next message exchange; if the transmission delay in both directions is less than 2t max , execute the next step.

[0036] Second step: the slave node equipment stores the forward transmission delay delay ms and the reverse transmission delay delaysm , select a set window size M, calculate the weighted average value of the continuous M historical transmission delays including the current forward transmission delay delay ms and the reverse transmission delay delay sm and Then use and and the time stamp recorded in the message to calculate the clock offset of the slave node and the master node.

[0037] Finally, according to the clock offset calculation formula in the IEEE1588 protocol, the clock offset of the slave node device and the master clock is calculated using the time stamp in the message and the processed transmission delay, and the local clock is adjusted using the calculated clock offset.

[0038] The method can improve the clock synchronization accuracy between devices by filtering the transmission delay added in the clock synchronization message of the transmission device, calculating the clock offset between devices according to the time stamp and the processed transmission delay, and finally adjusting the local clock of the device using the calculated clock offset.

[0039] The following is a more specific example:

[0040] Figure 1 is a structural diagram of a clock synchronization system, the master clock node device in the clock synchronization system receives the satellite signal of GPS / Beidou satellite through the satellite receiver, extracts the time information in the satellite signal, and uses it as the clock reference in the entire clock synchronization system. The time information is transmitted to each slave node device through the interaction of clock synchronization messages with each slave node device. The master clock node device fully supports the IEEE1588 protocol end-to-end transmission mode, that is, it can send and receive corresponding messages according to the requirements of the IEEE1588 protocol standard, and add the time of sending and receiving the message in the form of time stamp at the specified position of the corresponding message. The switch in the clock synchronization system is an IEEE1588 switch, that is, a transparent clock device defined in the IEEE1588 v2 protocol. The IEEE1588 switch can add the residence time of the message in the transmission device during the forward transmission process and the reverse transmission process between the master node and the slave node in the form of time stamp at the corresponding position in the message. Figure 1 The controller 1-8 in the clock synchronization system is a slave node device, which runs the clock synchronization accuracy optimization method.

[0041] Figure 2 ​is the overall flow chart of the clock synchronization precision optimization method, the method first makes the master and slave nodes in the clock synchronization system interact with each other according to the IEEE1588 protocol, and the slave node device obtains the time stamp recorded in each message and the transmission delay written by the transparent clock device in the specified position of the message; then the slave node device uses a filtering algorithm to process the forward transmission delay and the reverse transmission delay, combines the clock bias calculation formula in the IEEE1588 protocol, uses the time stamp in the message and the processed transmission delay to calculate the clock bias between the slave node device and the master clock, and finally adjusts the local clock by using the calculated clock bias, so as to realize the clock synchronization between each device in the clock synchronization system.

[0042] Figure 3 is the schematic diagram of the clock synchronization principle of the IEEE1588 protocol end-to-end transmission mode. First, the master clock node sends Sync messages to the clock synchronization system at a fixed frequency, the IEEE1588 switch forwards the Sync messages sent by the master clock node to each slave node device in the clock synchronization system, and at the same time, the residence time of the Sync message in the IEEE1588 switch is transmitted forwardly delay ms The time stamp is added in the corresponding position of the Sync message, and the master clock node adds the time t2 when the Sync message leaves the master clock node in the form of a time stamp in the Follow-up message and forwards it to each slave node device through the IEEE1588 switch; the slave node device immediately records and stores the time t1 when the Sync message is received after receiving the Sync message, then sends the Delay_Req message to the master clock node, and records and stores the time t3 when the Delay_Req message leaves the slave node device, the IEEE1588 switch forwards the Delay_Req message sent by the slave node device to the master node device, and at the same time, the residence time of the Delay_Req message in the IEEE1588 switch is transmitted reversely delay sm The time stamp is added in the corresponding position of the Delay_Req message; the master clock node immediately records and stores the time t4 when the Delay_Req message is received after receiving the Delay_Req message, then adds the time t4 in the form of a time stamp in the corresponding position of the Delay_Resp message, and sends it to the slave node device through the IEEE1588 switch; the slave node device receives the Delay_Resp message, extracts the time stamp in the Delay_Resp message, and thus a complete clock synchronization process between the master and slave nodes in the end-to-end transmission mode has ended. Finally, the slave node device calculates the forward transmission delay delay ms and the reverse transmission delay delaysm And the four times t1, t2, t3, and t4 obtained during the clock synchronization process, according to Figure 3 The clock skew calculation formula can be used to calculate the clock skew between the slave node and the master clock node. However, when network congestion occurs, or when some network devices fail and routing path replanning is performed, the positive transmission delay added to the clock synchronization message by the transparent clock will be affected. ms With reverse transmission delay sm There is a significant error between the calculated and actual transmission delays. If the clock offset between devices is directly calculated using the transmission delay data recorded within the message, the calculated clock offset will have a large discrepancy with the actual clock offset. Therefore, this method utilizes a filtering algorithm to filter the transmission delay. The specific process of the filtering algorithm is as follows: Figure 4 As shown, the filtering algorithm mainly consists of the following two steps:

[0043] Step 1: Obtain the forward transmission delay With reverse transmission delay The time t required for transmission along the longest transmission path within the network max The comparison is made based on the time t required for transmission along the longest transmission path within the network. max This can be obtained from the routing management table of the IEEE 1588 switch within the network. If the transmission delay in any direction is greater than 2t... max This indicates that during the clock synchronization process, if network congestion or partial network device failure requiring rerouting occurs, the timestamps and transmission delays obtained during this message exchange will be discarded, and the clock adjustment will be terminated, proceeding to the next message exchange; if the transmission delays in both propagation directions are less than 2t... max If so, proceed to the next step;

[0044] Step 2: Calculate the forward transmission delay processed in Step 1. With reverse transmission delay The latency is stored internally on the slave node device, while the oldest transmission latency value in the historical forward and reverse transmission latency records stored internally on the slave node device is discarded. The number of historical forward and reverse transmission latency records needs to be selected with an appropriate parameter N value based on the internal storage space and processing capacity of the slave node device; in this example, N = 10. Next, the latency including the current forward transmission latency is calculated. With reverse transmission delay The weighted average of M consecutive historical transmission delays, including time. and The value of the moving average window size M can be selected according to the actual network jitter. In this example, the window size value M = 5.

[0045] Finally, by using and and the time stamp recorded in the message, the clock offset from the node to the master node is calculated according to the clock offset formula shown in Figure 3 and the clock deviation calculated is used to adjust the local clock of the slave node device.

[0046] In summary, the application solves the problem that the asymmetric delay in the message transmission process in the IEEE1588 protocol end-to-end transmission mode clock synchronization system affects the clock synchronization accuracy of the master node and the slave node device, improves the time synchronization accuracy between devices in the network communication system, and has a wide application prospect.

Claims

1. A method for optimizing the synchronization accuracy of a clock synchronization system, characterized in that, The clock synchronization system is an IEEE 1588 protocol end-to-end transmission mode clock synchronization system, including the following steps: In a clock synchronization system, the master node and slave node devices exchange messages in an end-to-end transmission mode according to the IEEE 1588 protocol. After obtaining the timestamps and transmission delays recorded in each message from the node device, the transmission delays are filtered, and the clock deviation from the master clock is calculated based on the timestamps and the processed transmission delays. Adjust the local clock using the calculated clock offset; The master node and slave node devices in the clock synchronization system communicate with each other in end-to-end transmission mode according to the IEEE 1588 protocol. Specifically, the master node sends Sync and Follow-up messages to the slave node devices. After receiving the messages, the slave node devices send Delay-Req messages to the master node. After receiving the Delay-Req messages from the slave node devices, the master node immediately replies with Delay-Resp messages. In the clock synchronization system, the transmission device between the master node and the slave node is a transparent clock device. During the transmission process, the dwell time of the message in the transmission device is added to the message in the form of a timestamp. The transmission delay includes the forward transmission delay from the master node to the slave node device. And the reverse transmission delay when messages sent from node devices are transmitted to the master node. ; Store and maintain the forward transmission latency of historical message exchanges within the node device. With reverse transmission delay ; After obtaining the timestamps and transmission delays recorded in each message from the slave node device, the transmission delay is filtered, and the clock deviation from the master clock is calculated based on the timestamps and the processed transmission delay. Specifically: The obtained forward transmission delay With reverse transmission delay The time required to transmit along the longest transmission path within the network Comparison: If the transmission delay in any direction is greater than... If the timestamp and transmission delay obtained during this message exchange are discarded, the clock adjustment will be terminated, and the next message exchange will begin. If the transmission delay in both propagation directions is less than For forward transmission delay With reverse transmission delay Select the desired window size. The calculation includes the forward transmission delay of this time. With reverse transmission delay Including continuous The weighted average of historical transmission delays and Then use , In addition to the timestamp recorded in the message, the clock offset between the slave node and the master node is calculated according to the clock offset calculation formula in the IEEE 1588 protocol.

2. A time synchronization optimization device, characterized in that, It includes a memory and a processor; the memory is used to store computer programs; the processor is used to execute the computer programs stored in the memory, and to implement the clock synchronization system synchronization accuracy optimization method as described in claim 1 during execution.

3. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the clock synchronization system synchronization accuracy optimization method as described in claim 1.

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