Multi-bit operation module and in-memory computing circuit structure using the module

Abstract

The present invention relates to the field of static random access memory (SRAM) technology, and more specifically, to a multi-bit operation module and an in-memory computation circuit structure utilizing the module. The multi-bit operation module of the present invention performs multi-bit multiplication-accumulation operations by calculating the discharge accumulation of bit line load capacitance. The design of split bit weights and separate global bit lines offers excellent computational parallelism and stability, high inference accuracy, and, in conjunction with a subsequent quantization unit module to obtain quantized output, supports multi-bit MAC operations in deep neural networks.

Description

Technical Field

[0001] The present invention relates to the technical field of static random access memory (SRAM), and more specifically, to a multi-bit operation module and an in-memory calculation circuit structure using the module. Background Art

[0002] In recent years, convolutional neural networks (CNNs) have achieved unprecedented success in numerous applications involving artificial intelligence (AI) and the Internet of Things (IoT), such as image recognition, speech keyword detection, and face recognition.

[0003] However, due to the limitations of computing hardware, it is inefficient when processing AI tasks. Traditional computing hardware is based on the von Neumann architecture. Since the memory and computing unit are two independent parts, when the computer performs a computing operation, it needs to take out the data from the memory, transfer it to the computing unit for calculation, and then write it back to the memory. Due to the movement of data between the processing elements (PEs) and the memory, problems such as excessive energy consumption and delays are prone to occur, which is called the "memory wall". Computing In Memory (CIM) breaks the von Neumann architecture of traditional computers and embeds the computing circuit into the memory, integrating storage and computing, thereby greatly reducing data migration and memory access consumption.

[0004] Nonvolatile computing in memory (Nonvolatile Computing In Memory) offers significant advantages for battery-powered miniature AI devices that require nonvolatile data storage and low power consumption. Current nonvolatile in-memory computing technology solutions support binary neural networks (BNNs) or binary weight networks (BWNs), which reduce storage requirements and improve energy efficiency to a certain extent. However, BNNs and BWNs are only applicable to simple networks and can only provide limited system-level reasoning accuracy when applied to complex applications, limiting the further development of AI technology. Therefore, in-memory multiply and accumulate (MAC) computing technology with multi-bit input (IN), weight (W), and output (OUT) is extremely important for advanced AI edge chips that require high reasoning accuracy. Summary of the Invention

[0005] Based on this, it is necessary to provide a multi-bit operation module and an in-memory computing circuit structure using the module to address the problem of limited accuracy of existing traditional in-memory computing reasoning.

[0006] The present invention is achieved by adopting the following technical solutions:

[0007] In a first aspect, the present invention provides a multi-bit operation module, including a first sub-bit calculation module and a second sub-bit calculation module.

[0008] The bit-division calculation module includes n cascaded calculation units and n weighted bit lines LW[1] to LW[n].

[0009] The kth cascade computing unit 1 includes four NMOS transistors N1[k], N2[k], N3[k], and N4[k]. N1[k] and N2[k] have the same specifications. 1≤k≤n.

[0010] N1[k] has a gate connected to weighted bit line 1 LW[k], a drain connected to computational bit line CBL, and a source connected to node 1 X1[k]. N2[k] has a gate connected to weighted bit line 1 LW[k], a drain connected to computational bit line CBLB, and a source connected to node 2 X2[k]. N3[k] has a gate connected to global bit line GBL, a drain connected to node 1 X1[k], and a source connected to ground GND. N4[k] has a gate connected to global bit line GBLB, a drain connected to node 2 X2[k], and a source connected to ground GND.

[0011] The bit-division calculation module 2 includes n cascade calculation units 2 and n even-weighted bit lines 2 RW[1] to RW[n].

[0012] The kth cascade computing unit 2 includes four NMOS transistors: N5[k], N6[k], N7[k], and N8[k]. N5[k] and N6[k] have the same specifications. N7[k], N8[k], N3[k], and N4[k] have the same specifications. The width-to-length ratio of N5[k] is h times that of N1[k].

[0013] The gate of N5[k] is connected to weighted bit line 2 RW[k], its drain is connected to computational bit line CBL, and its source is connected to node 3 X3[k]. The gate of N6[k] is connected to weighted bit line 2 RW[k], its drain is connected to computational bit line CBLB, and its source is connected to node 4 X4[k]. The gate of N7[k] is connected to global bit line GBL, its drain is connected to node 3 X3[k], and its source is connected to ground GND. The gate of N8[k] is connected to global bit line GBLB, its drain is connected to node 4 X4[k], and its source is connected to ground GND.

[0014] The weight bit line 2 RW[k] and the weight bit line 1 LW[k] are used to provide weight values, and the global bit lines GBL and GBLB are used to provide multi-bit input values.

[0015] The multi-bit operation module operates in parallel with the selected columns of the sub-bit calculation module 1 and sub-bit calculation module 2, receiving weight values ​​and multi-bit input values ​​to perform multi-bit multiplication and accumulation calculations. The calculation bit lines CBL and CBLB are used to reflect the multi-bit multiplication and accumulation calculation results through voltage changes.

[0016] The implementation of such a multi-bit operation module is in accordance with the method or process of an embodiment of the present disclosure.

[0017] In the second aspect, the present invention discloses an in-memory computing circuit structure, including a storage array module, a data selection module, a sensitive amplifier module, a mode selection module, a multi-bit operation module as disclosed in the first aspect, a quantization unit module, and a timing control circuit module.

[0018] The storage array module is used to provide standard read / write modes and multi-bit multiplication-accumulation (M / A) calculation modes. The storage array module includes a storage unit and a reference unit. The data selection module, including a column selection module and a row decoding module, is used to locate and access corresponding memory cells in the storage unit based on external address signals in the standard read / write mode. The column selection module is also connected to a write driver circuit for controlling writes to the memory cells. The sense amplifier module is used to compare the read current generated by the storage unit with the reference current of the reference unit to generate a conversion voltage, amplify the conversion voltage, and obtain an output weight value. The sense amplifier module is also connected to a read driver circuit for reading the output weight value during a read operation in the standard read / write mode. The mode selection module is used to switch the storage array module between the standard read / write mode and the multi-bit M / A calculation mode. In the multi-bit calculation mode, the multi-bit operation module performs multi-bit M / A calculations based on the weight values ​​and multi-bit input values. The multi-bit operation module is connected to an input register for inputting the multi-bit input value into the multi-bit operation module via global bit lines GBL and GBLB. The quantization unit module is used to quantize the voltage changes accumulated by the calculation bit lines CBL and CBLB in the multi-bit multiplication and accumulation calculation mode to obtain a quantized output. The timing control circuit module is used to control the timing of each part of the calculation circuit structure in the memory so that it works accordingly.

[0019] The implementation of this in-memory computing circuit structure is based on the method or process of the embodiment of the present disclosure.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. The multi-bit operation module of the present invention completes the multi-bit multiplication and accumulation operation by calculating the discharge accumulation of the bit line load capacitance. The design of bit weighting and separation of global bit lines has good computational parallelism and stability, high inference accuracy, and cooperates with the subsequent quantization unit module to obtain quantized output, which can support multi-bit MAC operation of deep neural networks.

[0022] 2. The memory array module of the present invention uses MRAM composed of 1T-1MTJ memory cells, which has high storage density and computing power density, reducing area overhead. The present invention can perform multi-bit multiplication and accumulation operations while accessing memory, significantly reducing overall network power consumption.

[0023] 3. The present invention realizes multi-bit multiplication and accumulation calculation based on MRAM, which has the characteristics of low static power consumption and non-volatility, and has advantages in device applications requiring non-volatile data storage and low-power battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art,

[0025] Other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 Schematic diagram of the structure of the in-memory computing circuit in Example 1 of the present invention;

[0027] Figure 2 for Figure 1 The structure diagram of the storage array module, column selector module, sense amplifier module, mode selector module, and multi-bit operation module;

[0028] Figure 3 for Figure 2 Structural diagram of the middle left storage array and left reference array;

[0029] Figure 4 for Figure 2 Structural diagram of the storage array on the middle right and the reference array on the left;

[0030] Figure 5 for Figure 2 A structural diagram of a pair of cascade computing units formed by the kth cascade computing unit 1 and the kth cascade computing unit 2 in the multi-bit computing module;

[0031] Figure 6 for Figure 2 Equivalent circuit diagram of multi-bit operation module in analog domain multiplication and accumulation calculation;

[0032] Figure 7 for Figure 2 Structural diagram of the medium-sensing amplifier module;

[0033] Figure 8 for Figure 7 Transient simulation waveform of read operation of the sensitive amplifier module;

[0034] Figure 9 for Figure 2 The structural diagram of the medium quantitative unit module;

[0035] Figure 10 for Figure 9 Schematic diagram of the quantization process of the quantization unit module;

[0036] Figure 11 for Figure 2 Schematic diagram of the multi-bit operation module performing the multiplication and accumulation calculation of 2-bit input and 2-bit weight;

[0037] Figure 12 for Figure 1 The in-memory computing circuit structure is based on 2-bit input and 2-bit weight multiplication and accumulation calculation Monte Carlo simulation results Figure A;

[0038] Figure 13 for Figure 1 The in-memory computing circuit structure is based on 2-bit input and 2-bit weight multiplication and accumulation calculation Monte Carlo simulation results Figure B;

[0039] Figure 14 for Figure 1 The in-memory computing circuit structure is based on 2-bit input and 2-bit weight multiplication and accumulation calculation Monte Carlo simulation results Figure C;

[0040] Figure 15 Schematic diagram showing how system power consumption and energy efficiency vary with operating voltage in the in-memory computing circuit structure provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0042] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] Example 1

[0045] See Figure 1 , which is a structural diagram of the in-memory computing circuit structure disclosed in this embodiment 1.

[0046] The in-memory computing circuit structure includes a storage array module, a data selection module, a sensitive amplifier module, a mode selection module, a multi-bit operation module, a quantization unit module, and a timing control circuit module. Figure 3 , from top to bottom, the structural diagram of the storage array module, column selection module, sensitive amplifier module, mode selector module, and multi-bit operation module is shown.

[0047] The memory array module is used to provide standard read and write modes and multi-bit multiplication and accumulation calculation modes. The memory array module includes a storage part and a reference part, including a (2N+2N / j) column and M row array.

[0048] Specifically, such as Figure 2 As shown, the storage unit includes a left storage array and a right storage array:

[0049] like Figure 3 As shown, Figure 2 The left memory array includes N columns and M rows of memory cells, wherein every j columns form a left sub-array, and the left memory array includes N / j groups of left sub-arrays.

[0050] like Figure 4 As shown, Figure 2 The right memory array also includes N columns and M rows of memory cells, wherein every j columns form a right sub-array, and the right memory array includes N / j groups of right sub-arrays.

[0051] The reference unit includes a left reference array and a right reference array. The left reference array includes left reference cells in N / j columns and M rows corresponding to the left memory array. The kth column of left reference cells corresponds to the kth group of left sub-arrays; 1 ≤ k ≤ N / j. Similarly, the right reference array includes right reference cells in N / j columns and M rows corresponding to the right memory array; the kth column of right reference cells corresponds to the kth group of right sub-arrays.

[0052] The storage cell, left reference cell, and right reference cell are all based on MRAM, the difference being the connected bit lines and source lines:

[0053] The memory cell includes an NMOS transistor M1 and a magnetic tunnel junction device MTJ1. The gate of the NMOS transistor M1 is connected to a word line WL, and the drain is connected to a source line SL. One end of the magnetic tunnel junction device MTJ1 is electrically connected to a bit line BL, and the other end is electrically connected to the source of M1.

[0054] The left and right reference cells have the same structure, including an NMOS transistor M2 and a magnetic tunnel junction device MTJ2. The gate of NMOS transistor M2 is connected to the word line WL, and the drain is connected to the reference source line. One end of the magnetic tunnel junction device MTJ2 is electrically connected to the reference bit line, and the other end is electrically connected to the source of M2.

[0055] It should be noted that the magnetic tunnel junction devices MTJ1 and MTJ2 will present two states, high resistance and low resistance, depending on the direction of the write operation current.

[0056] Memory cells, left reference cells, and right reference cells in the same row share the same word line WL. Memory cells in the same column share the same bit line BL and source line SL. Left reference cells in the same column share the same reference bit line and reference source line. Right reference cells in the same column share the same reference bit line and reference source line.

[0057] The kth reference bit line of the left reference array is used to output the reference current I REF1 [k], the kth reference bit line of the right reference array is used to output the reference current I REF2 [k].

[0058] The multi-bit operation module is configured to correspond to the storage array module and is used to perform multi-bit multiplication and accumulation calculations based on weight values ​​and multi-bit input values ​​in multi-bit calculation mode. The multi-bit operation module is connected to an input register, which is used to input the multi-bit input values ​​into the multi-bit operation module via global bit lines GBL and GBLB. The weight values ​​come from the sense amplifier module.

[0059] The multi-bit operation module includes a first sub-bit calculation module and a second sub-bit calculation module.

[0060] The bit-division calculation module includes n cascaded calculation units and n weighted bit lines LW[1] to LW[n].

[0061] See Figure 5 The kth cascade computing unit includes four NMOS tubes N1(k), N2(k), N3(k), and N4(k).

[0062] The gate of N1(k) is connected to the kth weighted bitline LW(k), its drain is connected to the computational bitline CBL, and its source is connected to the kth node X1(k). The gate of N2(k) is connected to the weighted bitline LW(k), its drain is connected to the computational bitline CBLB, and its source is connected to the kth node X2(k). The gate of N3(k) is connected to the global bitline GBL, its drain is connected to the node X1(k), and its source is connected to ground GND. The gate of N4(k) is connected to the global bitline GBLB, its drain is connected to the node X2(k), and its source is connected to ground GND.

[0063] The bit-division calculation module 2 includes n cascade calculation units 2 and n even-weighted bit lines 2 RW[1] to RW[n].

[0064] See Figure 5 The k-th cascade computing unit 2 includes four NMOS transistors: N5[k], N6[k], N7[k], and N8[k]. The gate of N5[k] is connected to the k-th weighted bit line 2 RW[k], the drain is connected to the computing bit line CBL, and the source is connected to the k-th node 3 X3[k]. The gate of N6[k] is connected to the weighted bit line 2 RW[k], the drain is connected to the computing bit line CBLB, and the source is connected to the k-th node 4 X4[k]. The gate of N7[k] is connected to the global bit line GBL, the drain is connected to the node 3 X3[k], and the source is connected to ground GND. The gate of N8[k] is connected to the global bit line GBLB, the drain is connected to the node 4 X4[k], and the source is connected to ground GND.

[0065] It's important to emphasize that n = N / j. N1[k] and N2[k] have the same specifications, with 1 ≤ k ≤ n. N5[k] and N6[k] have the same specifications. N7[k], N8[k], N3[k], and N4[k] have the same specifications. The aspect ratio of N5[k] is h times that of N1[k]. Adjusting the value of h allows for weighted control of the on-state current of the cascaded computing units.

[0066] The weight bit line 2 RW[k] and the weight bit line 1 LW[k] are used to provide weight values, and the global bit lines GBL and GBLB are used to provide multi-bit input values.

[0067] The multi-bit operation module operates in parallel with the selected columns of the sub-bit calculation module 1 and sub-bit calculation module 2, receiving weight values ​​and multi-bit input values ​​to perform multi-bit multiplication and accumulation calculations. The calculation bit lines CBL and CBLB are used to reflect the multi-bit multiplication and accumulation calculation results through voltage changes.

[0068] In the multi-bit multiplication and accumulation calculation mode, the multi-bit operation module uses the calculation bit line capacitance (C CBL / C CBLB )’s discharge information is used to realize the convolution operation of the neural network.

[0069] In general, both the left and right storage arrays have N columns and M rows, and each storage array is divided into N / j groups of sub-arrays according to j columns. The left storage array corresponds to cascade computing unit one (i.e., the low-order cascade computing unit), and the right storage array corresponds to cascade computing unit two (i.e., the high-order cascade computing unit). In the standard read-write mode and the multi-bit multiplication and accumulation computing mode, the N / j groups of sub-arrays in the left and right storage arrays work in parallel, and the left and right sub-arrays in corresponding positions (i.e., the k-th left sub-array and the k-th right sub-array) are a pair, for a total of N / j pairs; the corresponding cascade computing unit one corresponding to the left storage array and the cascade computing unit two corresponding to the right storage array (i.e., the k-th low-order cascade computing unit and the k-th high-order cascade computing unit) constitute a pair of cascade computing units, for a total of N / j pairs, as shown in FIG. Figure 5 As shown, this ensures computational parallelism and stability.

[0070] When the memory array module completes the standard read operation, N / j pairs of stored data are read out through the sense amplifier module. Each pair of outputs consists of DOUTL[k] and DOUTR[k] with a 2-bit weight W[1:0].

[0071] In the multi-bit multiplication-accumulation calculation mode, MEN is set to a high level, and N / j pairs of 2-bit weights are transmitted bit by bit to the corresponding N / j pairs of cascaded calculation units. The external 4-bit input IN[3:0] is divided into two groups (IN[3:2], IN[1:0]) and transmitted to the global bit lines GBL / GBLB respectively, which are represented by the duration of the high level of VGBL / VGBLB. The calculation results correspond to the voltage changes on the calculation bit lines CBL / CBLB respectively.

[0072] When a single pair of cascaded computation units is activated, it begins to read the weight information output by the corresponding sense amplifier (CSA):

[0073] If the read weight W[1:0] is "00", the calculation unit does not generate current, that is, the multiplication operation result is 0; if the read weight W[1:0] is 1 "01", "10" and "11", the calculation bit line capacitance (CCBL / CCBLB) of the pair of calculation units begins to discharge the calculation unit, and the final multiplication and accumulation results generate discharge currents I, 2I and 3I respectively, and a discharge voltage drop is generated on the calculation bit line CBL / CBLB according to the global discharge time corresponding to the input value.

[0074] N / j accumulates the discharge generated by the multiplication result on the corresponding calculation bit line CBL / CBLB, that is, the total voltage change on CBL / CBLB corresponds to the final multiplication and accumulation calculation result.

[0075] See Figure 6, is the equivalent circuit diagram of a multi-bit operation module performing a multiplication and accumulation calculation of a 2-bit input and a 2-bit weight, taking half of the first cascaded computing unit 1 and half of the first cascaded computing unit 2 for illustration. In this embodiment, h is set to 2.

[0076] N1[1] and N2[1] (not shown) constitute a low-order cascade calculation unit to read the weight value stored in the left storage sub-array. N5[1] and N6[1] (not shown) constitute a high-order cascade calculation unit to read the weight value stored in the right storage sub-array, where LW[1] and RW[1] represent the weight values ​​of the left storage sub-array and the right storage sub-array, respectively. That is, the 2-bit weight W[1:0] is transmitted bit by bit to the high-order cascade calculation unit and the low-order cascade calculation unit, where a pair of 2-bit inputs IN[3:2] are transmitted to the global bit line GBL, and V is determined according to the input data. GBL High level duration T GBL The width-to-length ratio of N5[1] is twice that of N1[1]. Therefore, when both the high-order cascade computing unit and the low-order cascade computing unit are turned on, the current I2 generated when the high-order cascade computing unit is turned on is twice the current I1 of the low-order cascade computing unit.

[0077] The above-mentioned multi-bit operation module supports multi-bit multiplication and accumulation operations involving multi-bit inputs and multi-bit weights. Compared with existing single-bit multiplication and accumulation operations, Boolean logic operations, etc., this multi-bit operation module is suitable for a variety of multi-bit neural networks and can improve the inference accuracy of AI edge devices.

[0078] The storage array module requires a data selection module to locate and access the corresponding memory cells in the storage unit based on external address signals in standard read / write mode. Based on the distributed nature of the storage array, the data selection module includes a row decoding module and a column selection module. The latter is used to enable the corresponding row, while the former is used to enable the corresponding row. The column selection module is also connected to a write driver circuit to control writes to the memory cells.

[0079] (1) The row decoding module is connected to the word line WL ( Figure 3 Not shown), the M word lines WL share the same row decoding module (ie, the same row decoder).

[0080] (2) The column selection module includes n column selectors 1 and n column selectors 2. Figure 3 As shown,

[0081] The kth column selector 1 is set corresponding to the kth left sub-array. The bit line BL of the kth left sub-array is connected to the input end of the kth column selector 1, and the output end of the kth column selector 1 outputs the read current I CELL1 [k].

[0082] The kth column selector 2 is set corresponding to the kth right sub-array. The bit line BL of the kth right sub-array is connected to the input end of the kth column selector 2, and the output end of the kth column selector 2 outputs the read current I CELL2 [k].

[0083] The n column selectors 1 and n column selectors 2 share the same addressing signal CS, facilitating unified control. Specifically, the addressing signal CS is input to the column select module to enable the kth column. Column selector 1 then enables the kth left subarray, and column selector 2 enables the kth right subarray.

[0084] The sense amplifier module is used to compare the read current generated by the storage part with the reference current of the reference part and generate a conversion voltage, amplify the conversion voltage and obtain an output weight value.

[0085] like Figure 3 As shown, the sense amplifier module includes n sense amplifiers 1 and n sense amplifiers 2.

[0086] (A) The kth sensitive amplifier 1 is connected to the kth column selector 1. The kth sensitive amplifier 1 includes the kth current sampling unit 1 and the kth voltage amplifier 1, which are used to CELL1 [k]、I REF1 [k] is sampled and compared, and the output is DOUTL[k].

[0087] For details, see Figure 7 The current sampling unit 1 includes 6 PMOS transistors P1 to P6 and 4 NMOS transistors NM1 to NM4.

[0088] P1's gate is connected to an external enable signal SAEN, its source is connected to power supply VDD, and its drain is connected to the first node NET1. P2's gate and drain are connected to the first node NET1, and its source is connected to power supply VDD. P3's gate is connected to the first node NET1, its source is connected to power supply VDD, and its drain is connected to the first-stage output node SO. P4's gate is connected to the second node NET2, its source is connected to power supply VDD, and its drain is connected to the first-stage output node SOB. P5's gate and drain are connected to the second node NET2, and its source is connected to power supply VDD. P6's gate is connected to an external enable signal SAEN, its source is connected to power supply VDD, and its drain is connected to the second node NET2.

[0089] The gate of NM1 is connected to the clamp signal CLP, and the source is connected to the read current I CELL , the drain is connected to the first node NET1. The gate of NM2 is connected to the first-stage output node SOB, the source is connected to the ground GND, and the drain is connected to the first-stage output node SO. The gate and drain of NM3 are connected to the first-stage output node SOB, and the source is connected to the ground GND. The gate of NM4 is connected to the clamp signal CLP, and the source is connected to the reference current IREF , the drain is connected to the second node NET2.

[0090] The voltage amplifier 1 includes two PMOS transistors P7 - P8 , three NMOS transistors NM5 - NM7 , and one inverter INV.

[0091] The gate and drain of P7 are connected to the third node NET3, and the source is connected to the power supply VDD. The gate and drain of P8 are connected to the fourth node NET4, and the source is connected to the power supply VDD. The gate of NM5 is connected to the first-stage output node SO, the source is connected to the fifth node NET5, and the drain is connected to the third node NET3. The gate of NM6 is connected to the first-stage output node SOB, the source is connected to the fifth node NET5, and the drain is connected to the fourth node NET4. The gate of NM7 is connected to the external enable signal SAEN, the source is connected to ground GND, and the drain is connected to the fifth node NET5. The input of inverter INV is connected to the fourth node NET4, and the output signal is the weight value DOUT, which is split into two paths: one path is used to connect to the readout driver circuit, and the other path is connected to the weight bit line WW.

[0092] Since the kth sense amplifier and the kth voltage amplifier are in (A), P1 to P8 are PL1[k] to PL8[k], NM1 to NM5 are NML1[k] to NML5[k], INV is INVL[k], NET1 to NET are NETL1[k] to NETL5[k], SO is SOL[k], SOB is SOBL[k], and I CELL For I CELL1 [k],I REF For I REF1 [k], DOUT is DOUTL[k] (i.e., the kth weight value is one), and WW is LW[k].

[0093] (2) The kth sensitive amplifier 2 is connected to the kth column selector 2. The kth sensitive amplifier 2 includes the kth current sampling unit 2 and the kth voltage amplifier 2, which are used to CELL2 [k]、I REF2 [k] is sampled and compared, and the output is DOUTR[k].

[0094] The second sense amplifier includes a second current sampling unit and a second voltage amplifier, which is used to read the current I of the even-numbered memory sub-array. CELL2 and the reference current I of the even reference array REF2 Perform sampling and comparison, and output weight value two.

[0095] Similar to (A), the current sampling unit 2 has the same structure as the current sampling unit 1, and also includes 6 PMOS transistors P1 to P6 and 4 NMOS transistors NM1 to NM4.

[0096] The voltage amplifier 1 and the voltage amplifier 2 have the same structure, including two PMOS transistors P7-P8, three NMOS transistors NM5-NM7, and one inverter INV.

[0097] For specific connections, please refer to the introduction of (A), and Figure 7 :

[0098] Since (B) is the kth sense amplifier 2 and the kth voltage amplifier 2, P1~P8 are PR1[k]~PR8[k], NM1~NM5 are NMR1[k]~NMR5[k], INV2 is INVR[k], NET1~NET5 are NETR1[k]~NETR5[k], SO is SOR[k], SOB is SOBR[k], I CELL For I CELL2 [k],I REF For I REF2 [k], DOUT is DOUTR[k] (i.e., the kth weight value is two), and WW is RW[k].

[0099] For the output signal DOUTL / DOUTR, if the reference current is less than the bit line current, the output is a low level 0; when the reference current is greater than the bit line current, the output is a high level 1.

[0100] See Figure 8 , which is a transient simulation waveform diagram of a read operation according to an embodiment of the present invention, is described using the general parameters without serial numbers in (A) and (B):

[0101] The read operation process can be divided into two stages:

[0102] Precharge / voltage difference stabilization stage: The clamp signal CLP is enabled, and the clamp tube between the bit line and the current source is turned on. The word line WL is turned on, and the current flows through the storage part and the reference part. When the MTJ1 in the memory cell is in a high impedance state, the reference current I REF Greater than the bit line current I CELL ; When MTJ1 in the memory cell is in low resistance state, the reference current I REF Less than the bit line current I CELL . Bit line current I CELL The current mirror formed by PMOS transistors P2 and P3 is copied to node SO, and the reference current IREF is copied to node SOB through the current mirror formed by PMOS transistors P4 and P5. Therefore, the current difference between the storage part and the reference part is converted into a voltage difference between nodes SO and SOB.

[0103] Sampling stage: When a stable voltage difference is formed between the node SO and the node SOB, the voltage amplifier enable signal SAE is turned on, the voltage difference between the node SO and the node SOB is amplified, and the stored data is read out of the output terminal.

[0104] Of course, the sense amplifier module is also connected to a readout driving circuit, which is used to read the output weight value during a read operation in a standard read / write mode.

[0105] The mode selection module is used to switch between the standard read and write mode and the multi-bit multiplication and accumulation calculation mode of the storage array module.

[0106] like Figure 3 As shown, the mode selection module selects a mode according to an external enable signal MEN.

[0107] When the external enable signal MEN is at a high level, that is, the weight bit line 1 LW[1]~LW[n] and the weight bit line 2 RW[1]~RW[n] are not connected to the multi-bit operation module, and the storage array module is in standard read and write mode.

[0108] When the external enable signal MEN is at a low level, the storage array module is in a multi-bit multiplication and accumulation calculation mode, and the weight bit line 1 LW[1]~LW[n] and the weight bit line 2 RW[1]~RW[n] are connected to the multi-bit operation module, so that the kth sensitive amplifier 1 is connected to the kth cascade calculation unit 1, and the kth sensitive amplifier 2 is connected to the kth cascade calculation unit 2.

[0109] In standard read / write mode and multi-bit multiply-accumulate mode, both the left and right subarrays operate in parallel. After the storage array module completes a standard read operation, the stored data is read out through the sense amplifier module, which outputs the corresponding weight values ​​DOUTL and DOUTR, corresponding to the 2-bit weight.

[0110] In the multi-bit multiplication and accumulation mode, the 2-bit weight is transmitted to the cascaded computing unit 1 / 2 in bits; the external 4-bit input is divided into two groups and transmitted to the global bit lines GBL / GBLB respectively, represented by V GBL / V GBLB The duration of the high level and the calculation results correspond to the voltage changes on the bit lines CBL / CBLB.

[0111] If the weight value read is "0", the calculation unit does not generate current, that is, the multiplication result is 0; if the weight value read is "1", the bit line capacitance (C CBL / C CBLB ) starts to discharge the computing unit, and the final multiplication and accumulation result corresponds to the discharge amount generated on the global bit line CBL / CBLB.

[0112] The quantization unit module is used to quantize the voltage variation accumulated by the calculation bit lines CBL / CBLB in a multi-bit multiplication and accumulation calculation mode to obtain a quantized output.

[0113] It should be noted that there are two quantization unit modules, one connected to the calculation bit line CBL for quantizing the voltage variation of the calculation bit line CBL; the other connected to the calculation bit line CBLB for quantizing the voltage variation of the calculation bit line CBLB.

[0114] See Figure 10 ,The two quantization unit modules have the same structure, both ,include a capacitor array, a successive approximation logic control unit, and a voltage ,comparator.

[0115] The capacitor array includes five capacitors C0 to C4, where the first capacitor is C0, the second capacitor is C1, the third capacitor is C2, the fourth capacitor is C3, and the fifth capacitor is C4. The relationship between the five capacitors is C4:C3:C2:C1:C0=8:4:2:1:1.

[0116] The upper plates of capacitors C0, C1, C2, C3, and C4 are all connected to the input node INP of the voltage comparator, and the lower plates of capacitors C0, C1, C2, C3, and C4 are connected to the calculation bit line CBL or CBLB, the reference voltage VREF, and the power supply VDD through the control switches S[0], S[1], S[2], S[3], and S[4] respectively.

[0117] The successive approximation logic control unit uses successive approximation logic to generate a control signal S[4:0] for controlling the capacitor array to generate a voltage comparator enable signal EN and thus control the voltage comparator.

[0118] The input node INN of the voltage comparator is connected to the common mode voltage VCM. When the control signal CE is turned on, the input nodes INP and INN are short-circuited, and the voltage comparator enable signal EN turns on the voltage comparator, which compares the voltages of the input nodes INP and INN and generates an output Output.

[0119] For a single quantization unit module, it quantizes 7 different multiplication-accumulation results into 4-bit data (0-15), that is, the maximum quantization result MAC_MAX=15.

[0120] The quantization unit module performs the standard dichotomy transformation, refer to Figure 10 For the quantization unit module 1 connected to the calculation bit line CBL, take the multiplication and accumulation MAC=9 as an example:

[0121] First, the control signal CE is turned on, and the nodes INN and INP are short-circuited to the common-mode voltage VCM. VCM corresponds to the quantized digital output 0.

[0122] After the capacitor array completes sampling the analog voltage obtained by multiplication and accumulation on the bit line CBL, the switch S[4:0] switches to the power supply VDD. At this time, the voltage of the node INP is:

[0123] V INP (0) = V CM +V DD -V CBL ;

[0124] When the comparison phase begins, the successive approximation logic control unit controls the switch S[4] to connect the lower plate of the fifth capacitor C4 to the reference voltage V REF Connected, the first approximation (ie 1 st VREF), the voltage of the node INP is:

[0125] V INP (1 st )=V CM -V CBL +(V REF +V DD ) / 2;

[0126] After the voltage comparator is applied to V INP With V INN The voltage is compared to get the output 0, which is fed back to the successive approximation logic control unit. The successive approximation logic control unit controls the switch S[3] to connect the lower plate of the fourth capacitor C3 to the reference voltage V REF Connected, the second approximation (ie 2 nd VREF), the voltage of the node INP is:

[0127] V INP (2 nd )=V CM -V CBL +3*(V REF +V DD ) / 4;

[0128] After the voltage comparator is applied to V INP With V INN The voltages are compared to obtain output 1, which is fed back to the successive approximation logic control unit. The successive approximation logic control unit controls switches S[3] and S[2], switches the lower plate of the fourth capacitor C3 to be connected to the power supply VDD, and connects the lower plate of the third capacitor C2 to the reference voltage VREF, and performs the third approximation (i.e., 3 rd VREF), the voltage of the node INP is:

[0129] V INP (3 rd )=V CM -V CBL+5*(V REF +V DD ) / 8;

[0130] After the voltage comparator is applied to V INP With V INN The voltages are compared to obtain output 1, which is fed back to the successive approximation logic control unit. The successive approximation logic control unit controls switches S[2] and S[1] to switch the lower plate of the third capacitor C2 to be connected to the power supply VDD, and connect the lower plate of the second capacitor C1 to the reference voltage VREF, and perform the fourth approximation (i.e., 4 th VREF), the voltage of the node INP is:

[0131] V INP (4 th )=V CM -V CBL / CBLB +9*(V REF +V DD ) / 16;

[0132] At this time, V INP With V INN The voltages are equal, and the quantization unit outputs the multiplication-accumulation calculation digital result MAC=9, which is the output of the quantization unit module 1.

[0133] Similarly, for the quantization unit module 2 connected to the calculation bit line CBLB, taking the multiplication-accumulation MAC=9 as an example, the working process is similar to the above, and the multiplication-accumulation calculation digital result MAC=9 is also output, which is the output of the quantization unit module 2.

[0134] The outputs of quantization module 1 and quantization module 2 are fed into a digital combinational circuit for weight redistribution. This circuit then converts the result into a full-precision digital output. For example, if both outputs have a value of MAC = 9, the final full-precision output is FMAC = 153 ("10011001").

[0135] In addition, the operation of the above components is controlled by the timing control circuit module, which controls the timing of each part of the in-memory computing circuit structure to make it work accordingly. Specifically, the timing control circuit controls the high and low level switching of each input signal and control signal.

[0136] Example 2

[0137] This embodiment 2 provides a principle explanation and simulation proof of the specific simulation domain calculation process when h is 2 in embodiment 1.

[0138] See Figure 11, which is a schematic diagram of the result of performing a multiplication of a 2-bit input and a 2-bit weight on any pair of cascaded computing units in a multi-bit operation module (taking the first pair of cascaded computing units consisting of the first cascaded computing unit 1 and the first cascaded computing unit 2 as an example).

[0139] The specific analog domain calculation process of W[1:0]×IN[3:2] is as follows:

[0140] When the weight W[1:0]=00, that is, the weight value LW[1] of the left storage array and the weight value RW[1] of the right storage array are both "0", at this time, no matter what the input IN[3:2] value is (IN[3:2]=00, 01, 10, 11), the low-order cascade calculation unit and the high-order cascade calculation unit are not turned on, that is, no discharge current is generated on the calculation bit line CBL, and the calculation bit line capacitance C CBL There is no discharge path; when input IN[3:2]=00, that is, V GBL When it is always low level in a calculation cycle, at this time, no matter what the weight W[1:0] is (W[1:0]=00, 01, 10, 11), the low-bit cascade calculation unit and the high-bit cascade calculation unit are not turned on, that is, no discharge current is generated on the calculation bit line CBL, and the calculation bit line capacitance C CBL No discharge path,

[0141] In the above 7 cases, the voltage change ΔV occurs on the bit line CBL. CBL =0, that is: W[1:0]×IN[3:2]=00×00=00×01=00×10=00×11=01×00=10×00=11×00=0.

[0142] When W[1:0]=01, IN[3:2]=01, that is, RW[1]=0, LW[1]=1, V GBL The high level duration T in one calculation cycle GBL When t is t, the high-order cascade calculation unit is not turned on, and the low-order cascade calculation unit is turned on to generate current I, and the bit line capacitance C is calculated. CBL The low-order cascade computing unit begins to discharge, and the bit line CBL produces a voltage change Right now:

[0143] When W[1:0]=01, IN[3:2]=10, that is, RW[1]=1, LW[1]=0, V GBL The high level duration T in one calculation cycle GBL When the current flowing through the calculation bit line CBL is I, the calculation bit line capacitance C CBLThe low-order cascade computing unit begins to discharge, and the bit line CBL produces a voltage change Right now:

[0144] When W[1:0]=01, IN[3:2]=11, that is, RW[1]=0, LW[1]=1, V GBL When the high level duration is 3t in a calculation cycle, the high-order cascade calculation unit is not turned on, and the low-order cascade calculation unit is turned on to generate a current I, that is, the current flowing through the calculation bit line CBL is I, and the calculation bit line capacitance C CBL The low-order cascade computing unit begins to discharge, and the bit line CBL produces a voltage change Right now

[0145] When W[1:0]=10, IN[3:2]=01, that is, RW[1]=1, LW[1]=0, V GBL The high level duration T in one calculation cycle GBL When t is t, the lower cascade calculation unit is turned on, and the higher cascade calculation unit is turned on to generate a current of 2I, that is, the current flowing through the calculation bit line CBL is 2I, and the calculation bit line capacitance C CBL The low-order cascade computing unit begins to discharge, and the bit line CBL produces a voltage change Right now:

[0146] When W[1:0]=10, IN[3:2]=10, that is, RW[1]=1, LW[1]=0, V GBL The high level duration T in one calculation cycle GBL When the bit line capacitance C is 2t, the lower cascade calculation unit is turned on, and the upper cascade calculation unit is turned on to generate a current of 2I. CBL The low-order cascade computing unit begins to discharge, and the bit line CBL produces a voltage change Right now:

[0147] When W[1:0]=10,IN[3:2]=11,that is, RW[1]=1,LW[1]=0,V GBL The high level duration T in one calculation cycle GBL When the current flowing through the calculation bit line CBL is 2I, the calculation bit line capacitance C CBL The low-order cascade computing unit begins to discharge, and the bit line CBL produces a voltage change Right now:

[0148] When W[1:0]=11, IN[3:2]=01, that is, RW[1]=1, LW[1]=1, VGBL high level duration T in one calculation cycle GBL When t is t, the lower cascade calculation unit is turned on to generate a current I and the upper cascade calculation unit is turned on to generate a current 2I, that is, the current flowing through the calculation bit line CBL is 3I, and the calculation bit line capacitance C CBL Start discharging the low-order cascade computing unit, and the computing bit line CBL generates a voltage change Right now:

[0149] When W[1:0]=11, IN[3:2]=10, that is, RW[1]=1, LW[1]=1, V GBL The high level duration T in one calculation cycle GBL When the current is 2t, the lower cascade calculation unit is turned on to generate a current I and the upper cascade calculation unit is turned on to generate a current 2I, that is, the current flowing through the calculation bit line CBL is 3I, and the calculation bit line capacitance C CBL Start discharging the low-order cascade computing unit, and the computing bit line CBL generates a voltage change Right now:

[0150] When W[1:0]=11, IN[3:2]=11, that is, RW[1]=1, LW[1]=1, VGBL high level duration T in one calculation cycle GBL When the current is 3t, the lower cascade calculation unit is turned on to generate a current I and the upper cascade calculation unit is turned on to generate a current 2I, that is, the current flowing through the calculation bit line CBL is 2I, and the calculation bit line capacitance C CBL Start discharging the low-order cascade computing unit, and the computing bit line CBL generates a voltage change Right now:

[0151] The specific truth table is shown in Table 1 below:

[0152] Table 1 Truth table of multi-bit multiplication and accumulation operation performed by multi-bit operation module

[0153]

[0154] From the above analysis, we can see that in the simulation domain,

[0155]

[0156]

[0157]

[0158] It is easy to prove that when IN[3:2] is "00", "01", "10" and "11", the corresponding discharge times are "0t", "1t", "2t" and "3t" respectively.

[0159] In order to prove that when W[1:0] is "00", "01", "10" and "11", the corresponding calculation unit discharge current is "0I", "1I", "2I" and "3I" respectively, we need to use Figure 6 The equivalent circuit for DC analysis is:

[0160] When N1[1] and N5[1] both work in the saturation region, and N2[1] and N6[1] both work in the deep linear region, a circuit consisting of an adjustable current source I and an adjustable linear resistor R can be made. on Equivalent analysis circuit in series, where the width-to-length ratio of N1[1] is (W / L)1, the width-to-length ratio of N5[1] is 2(W / L)1, the width-to-length ratio of N2[1] and N6[1] is (W / L)2, and the threshold voltage of N1[1] and N5[1] is V TH1 , the threshold voltage of N2[1] and N6[1] is V TH2 ; The voltage of LW[1] is V LW1 , the voltage of RW[1] is V RW1 .

[0161] It should be noted that (W / L)1 and (W / L)2 represent two width-to-length ratios.

[0162] Before starting the calculation, calculate the bit line capacitance C CBL is precharged to V PRE When both the high-order cascade computing unit and the low-order cascade computing unit are activated, the conduction current I1 of the low-order cascade computing unit is:

[0163]

[0164] Among them, μ n 、C ox All are process-related constants.

[0165] The conduction current I2 of the high-order cascade calculation unit is:

[0166]

[0167] Adjustable linear resistor R on for:

[0168]

[0169] Among them, the voltage V LX for:

[0170] V LX =I1*R on ; (7)

[0171] The voltage V at node RX (i.e. X3[1]) RX for:

[0172] V RX =I2*R on ; (8)

[0173] When the adjustable linear resistor R on If the resistance is small enough, it can be considered that V LX 、V RX The effect of the change on I1 and I2 can be ignored, that is, the conduction current of the low-order cascade computing unit and the high-order cascade computing unit changes linearly with their width-to-length ratio, that is:

[0174]

[0175]

[0176]

[0177] The discharge current of a pair of cascade computing units is equal to the sum of the current I2 of the upper cascade computing unit and the current I1 of the lower cascade computing unit. According to formulas (9), (10), and (11), we can know that:

[0178] When W[1:0] is "00", "01", "10" and "11" respectively, the total discharge current is: 0*I1+0*I2=0, 1*I1+0*I2=I1, 0*I1+1*I2=I2=2I1, 1*I1+1*I2=3I1.

[0179] According to the linear capacitance VCR (Voltage Current Relation) relationship, we can get:

[0180]

[0181] That is, formulas (1), (2), and (3) are verified.

[0182] In addition, see Figure 12 、 Figure 13 、 Figure 14 Monte Carlo simulation diagram for calculating 7 discharge results for 2-bit input and 2-bit weight multiplication. Figure 12It is verified that the discharge amount on the CBL for both W[1:0]×N[3:2]=10×01 and W[1:0]×N[3:2]=01×10 is 2ΔV, and the Gaussian distribution of its Monte Carlo simulation shows that the mean and standard deviation of the voltage on the CBL are approximately equal after the discharge operation. Figure 13 It is verified that the discharge amount on CBL for both calculation cases of W[1:0]×IN[3:2]=01×11 and W[1:0]×N[3:2]=11×01 is 3ΔV; Figure 14 It was verified that the discharge amount on the CBL for both calculation cases of W[1:0]×IN[3:2]=10×11 and W[1:0]×N[3:2]=11×10 was 6ΔV. This shows that the multi-bit multiplication and accumulation calculation performed by this multi-bit operation module in the analog domain is reliable.

[0183] This embodiment 2 also simulates the power consumption and energy efficiency of the in-memory computing circuit system disclosed in embodiment 1 as the operating voltage changes. Figure 15 The horizontal axis represents the operating voltage, the left vertical axis represents power consumption, and the right vertical axis represents energy efficiency. As can be seen from the figure, as the operating voltage decreases, power consumption decreases and energy efficiency improves. The circuit can operate at a minimum voltage of 0.5V, at which point the power consumption and energy efficiency are 43.21μW and 84.39TOPS / W, respectively, meeting the requirements.

[0184] Example 3

[0185] This embodiment 3 considers a more general situation, that is, in order to verify the practicality of the design method: the width-to-length ratio of N5[k] in the high-order cascade computing unit is set to h times the width-to-length ratio of N1[k] in the low-order cascade computing unit, while other conditions remain unchanged, so that the discharge current I generated when the high-order cascade computing unit is activated can be h It is h times the discharge current I1 generated when the low-order cascade computing unit is activated.

[0186] Referring to Example 2, formulas (5) and (8) are replaced by formulas (13) and (14):

[0187] The conduction current I of the high-order cascade computing unit h for:

[0188]

[0189] The voltage V at the node RX (ie X3[k]) RX for:

[0190] V RX =I h *R on (14)

[0191] Substituting formula (14) into formula (13), and substituting formula (7) into formula (4), we can obtain:

[0192]

[0193]

[0194] make

[0195] Then rewriting formulas (15) and (16) yields:

[0196]

[0197] This can be transformed into a proof:

[0198] That is to prove formula (18): Just establish it.

[0199] According to L'Hôpital's rule, we can get:

[0200]

[0201] That is, formula (18) is proved, so I h =I1*h.

[0202] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0203] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A multi-bit operation module, which is used to implement multi-bit multiplication and accumulation calculations, characterized in that: The multi-bit operation module includes: A bit-division calculation module 1, comprising n cascade calculation units 1 and n weight bit lines 1 LW[1] to LW[n]; The kth cascade computing unit 1 includes: NMOS transistor N1[k], with its gate connected to weight bit line LW[k], drain connected to calculation bit line CBL, and source connected to node X1[k]; The NMOS transistor N2[k] has its gate connected to the weighted bit line LW[k], its drain connected to the calculation bit line CBLB, and its source connected to the node X2[k]. N1[k] and N2[k] have the same specifications. NMOS transistor N3[k], with its gate connected to global bit line GBL, its drain connected to node X1[k], and its source connected to ground GND; and NMOS transistor N4[k], its gate is connected to the global bit line GBLB, its drain is connected to the node 2 X2[k], and its source is connected to the ground GND; 1≤k≤n; A second bit-division calculation module includes n second cascade calculation units and n second even-weighted bit lines RW[1] to RW[n]; The kth cascade computing unit 2 includes: NMOS transistor N5[k], its gate is connected to weighted bit line 2 RW[k], its drain is connected to calculation bit line CBL, and its source is connected to node 3 X3[k]; NMOS transistor N6[k], its gate is connected to weighted bit line 2 RW[k], its drain is connected to calculation bit line CBLB, and its source is connected to node 4 X4[k]. N5[k] and N6[k] have the same specifications. NMOS transistor N7[k], with its gate connected to global bit line GBL, its drain connected to node three X3[k], and its source connected to ground GND; and NMOS transistor N8[k], whose gate is connected to global bit line GBLB, drain is connected to node four X4[k], and source is connected to ground GND; N7[k], N8[k], N3[k], and N4[k] have the same specifications, and the width-to-length ratio of N5[k] is h times that of N1[k]; Weight bit line 2 RW[k] and weight bit line 1 LW[k] are used to provide weight values; global bit lines GBL and GBLB are used to provide multi-bit input values; The multi-bit operation module works in parallel from the selection columns of the sub-bit calculation module 1 and the sub-bit calculation module 2, receives the weight value and the multi-bit input value, and performs multi-bit multiplication and accumulation calculation; the calculation bit lines CBL and CBLB are used to reflect the multi-bit multiplication and accumulation calculation results through voltage changes.

2. In-memory computing circuit structure, characterized in that: include: A storage array module, which is used to provide a standard read-write mode and a multi-bit multiplication-accumulation calculation mode; the storage array module includes a storage unit and a reference unit; The data selection module includes a column selection module and a row decoding module, and is used to locate and access the corresponding storage unit in the storage unit according to the external address signal in the standard read and write mode; the column selection module is also connected to the write drive circuit for controlling the writing of the storage unit; A sense amplifier module, configured to compare the read current generated by the storage unit with the reference current of the reference unit to generate a conversion voltage, amplify the conversion voltage, and obtain an output weight value; the sense amplifier module is further connected to a readout driver circuit, configured to read the output weight value during a read operation in a standard read / write mode; A mode selection module for switching between a standard read / write mode and a multi-bit multiplication-accumulation calculation mode of the storage array module; The multi-bit operation module according to claim 1, wherein in a multi-bit calculation function mode, the multi-bit multiplication and accumulation calculation is performed according to the weight value and the multi-bit input value; the multi-bit operation module is connected to an input register, which is used to input the multi-bit input value into the multi-bit operation module through the global bit lines GBL and GBLB; A quantization unit module is used to quantize the voltage variation accumulated by the bit lines CBL and CBLB in a multi-bit multiplication and accumulation calculation mode to obtain a quantized output; as well as The timing control circuit module is used to control the timing of each part of the in-memory computing circuit structure so that it works accordingly.

3. The in-memory computing circuit structure according to claim 2, wherein: The storage unit includes a left storage array and a right storage array; The left storage array includes N columns and M rows of storage cells; wherein every j columns constitute a group of left sub-arrays, and the left storage array includes N / j groups of left sub-arrays, where N=n*j; The right storage array also includes N columns and M rows of storage cells; wherein every j columns constitute a group of right sub-arrays, and the right storage array includes N / j groups of right sub-arrays; The reference unit includes a left reference array and a right reference array; the left reference array includes left reference cells in N / j columns and M rows corresponding to the left storage array; wherein the left reference cell in the kth column is arranged corresponding to the kth group of left sub-arrays; 1≤k≤N / j; The right reference array includes right reference units in N / j columns and M rows corresponding to the right storage array; wherein the k-th column of right reference units is arranged corresponding to the k-th group of right sub-arrays.

4. The in-memory computing circuit structure according to claim 3, wherein: The storage unit includes: NMOS transistor M1, whose gate is connected to word line WL and whose drain is connected to source line SL; and A magnetic tunnel junction device MTJ1, one end of which is electrically connected to the bit line BL and the other end of which is electrically connected to the source of M1; The left reference unit and the right reference unit have the same structure, including: NMOS transistor M2, whose gate is connected to word line WL and whose drain is connected to reference source line; and A magnetic tunnel junction device MTJ2, one end of which is electrically connected to a reference bit line and the other end of which is electrically connected to the source of M2; The memory cells, left reference cells, and right reference cells in the same row share the same word line WL; the memory cells in the same column share the same bit line BL and the same source line SL; the left reference cells in the same column share the same reference bit line and the same reference source line; the right reference cells in the same column share the same reference bit line and the same reference source line; The kth reference bit line of the left reference array is used to output the reference current I REF1 [k], the kth reference bit line of the right reference array is used to output the reference current I REF2 [k].

5. The in-memory computing circuit structure according to claim 4, characterized in that: The column selection module includes n column selectors 1 and n column selectors 2; the n column selectors 1 and n column selectors 2 share the same addressing signal CS; The kth column selector 1 is set corresponding to the kth left sub-array, and the kth column selector 2 is set corresponding to the kth right sub-array; The bit line BL of the kth group of the left sub-array is connected to the input terminal of the kth column selector 1, and the output terminal of the kth column selector 1 outputs the read current I CELL1 [k]; The bit line BL of the kth right sub-array is connected to the input terminal of the kth column selector 2, and the output terminal of the kth column selector 2 outputs the read current I CELL2 [k]; The row decoding module is connected to the word line WL, and the M word lines WL share the same row decoding module.

6. The in-memory computing circuit structure according to claim 5, characterized in that: The sensitive amplifier module includes n sensitive amplifiers 1 and n sensitive amplifiers 2; The kth sense amplifier 1 is connected to the kth column selector 1; the kth sense amplifier 2 is connected to the kth column selector 2; The kth sensitive amplifier 1 includes the kth current sampling unit 1 and the kth voltage amplifier 1, which is used to CELL1 [k]、I REF1 [k] is sampled and compared, and the output is DOUTL[k]; The kth sensitive amplifier 2 includes the kth current sampling unit 2 and the kth voltage amplifier 2, which are used to CELL2 [k]、I REF2 [k] is sampled and compared, and the output is DOUTR[k].

7. The in-memory computing circuit structure according to claim 6, wherein: The kth current sampling unit 1 includes: A PMOS transistor PL1[k], whose gate is connected to an external enable signal SAEN, whose source is connected to a power supply VDD, and whose drain is connected to a first node NETL1[k]; The PMOS transistor PL2[k] has a gate and a drain connected to the first node NETL1[k], and a source connected to the power supply VDD; A PMOS transistor PL3[k], whose gate is connected to the first node NETL1[k], whose source is connected to the power supply VDD, and whose drain is connected to the first-stage output node SOL[k]; A PMOS transistor PL4[k], whose gate is connected to the second node NETL2[k], whose source is connected to the power supply VDD, and whose drain is connected to the first-stage output node SOBL[k]; A PMOS transistor PL5[k], whose gate and drain are connected to the second node NETL2[k], and whose source is connected to the power supply VDD; A PMOS transistor PL6[k], whose gate is connected to the external enable signal SAEN, whose source is connected to the power supply VDD, and whose drain is connected to the second node NETL2[k]; The gate of the NMOS transistor NML1[k] is connected to the clamp signal CLP, and the source is connected to the read current I CELL1 [k], the drain is connected to the first node NETL1[k]; NMOS transistor NML2[k], whose gate is connected to the first-stage output node SOBL[k], source is connected to the ground GND, and drain is connected to the first-stage output node SOL[k]; NMOS transistor NML3[k], whose gate and drain are connected to the first-stage output node SOBL[k], and whose source is connected to the ground GND; and The gate of the NMOS transistor NML4[k] is connected to the clamp signal CLP, and the source is connected to the reference current I REF1 [k], the drain is connected to the second node NETL2[k]; The k-th voltage amplifier comprises: A PMOS transistor PL7[k], whose gate and drain are connected to the third node NETL3[k], and whose source is connected to the power supply VDD; A PMOS transistor PL8[k], whose gate and drain are connected to the fourth node NETL4[k], and whose source is connected to the power supply VDD; NMOS transistor NML5[k], whose gate is connected to the first-stage output node SOL[k], whose source is connected to the fifth node NETL5[k], and whose drain is connected to the third node NETL3[k]; NMOS transistor NML6[k], whose gate is connected to the first-stage output node SOBL[k], whose source is connected to the fifth node NETL5[k], and whose drain is connected to the fourth node NETL4[k]; An NMOS transistor NML7[k], whose gate is connected to the external enable signal SAEN, whose source is connected to the ground GND, and whose drain is connected to the fifth node NETL5[k]; and The inverter INVL[k] has its input connected to the fourth node NETL4[k], and its output signal is a weight value DOUTL[k] and is divided into two paths, one of which is used to connect to the readout drive circuit and the other is connected to the weight bit line LW[k].

8. The in-memory computing circuit structure according to claim 7, wherein: The kth current sampling unit 2 includes: A PMOS transistor PR1[k], whose gate is connected to an external enable signal SAEN, whose source is connected to a power supply VDD, and whose drain is connected to a first node NETR1[k]; The PMOS transistor PR2[k] has a gate and a drain connected to the first node NETR1[k], and a source connected to the power supply VDD; A PMOS transistor PR3[k], whose gate is connected to the first node NETR1[k], whose source is connected to the power supply VDD, and whose drain is connected to the first-stage output node SOR[k]; A PMOS transistor PR4[k], whose gate is connected to the second node NETR2[k], whose source is connected to the power supply VDD, and whose drain is connected to the first-stage output node SOBR[k]; The PMOS transistor PR5[k] has a gate and a drain connected to the second node NETR2[k], and a source connected to the power supply VDD; A PMOS transistor PR6[k], whose gate is connected to the external enable signal SAEN, whose source is connected to the power supply VDD, and whose drain is connected to the second node NETR2[k]; The gate of the NMOS transistor NMR1[k] is connected to the clamp signal CLP, and the source is connected to the read current I CELL2 [k], the drain is connected to the first node NETR1[k]; NMOS transistor NMR2[k], whose gate is connected to the first-stage output node SOBR[k], source is connected to the ground GND, and drain is connected to the first-stage output node SOR[k]; NMOS transistor NMR3[k], whose gate and drain are connected to the first-stage output node SOBR[k], and whose source is connected to the ground GND; and The gate of the NMOS transistor NMR4[k] is connected to the clamp signal CLP, and the source is connected to the reference current I REF2 [k], the drain is connected to the second node NETR2[k]; The voltage amplifier 2 includes: A PMOS transistor PR8[k], whose gate and drain are connected to the third node NETR3[k], and whose source is connected to the power supply VDD; A PMOS transistor PR9[k], whose gate and drain are connected to the fourth node NETR4[k], and whose source is connected to the power supply VDD; NMOS transistor NMR5[k], whose gate is connected to the first-stage output node SOR[k], whose source is connected to the fifth node NETR5[k], and whose drain is connected to the third node NETR3[k]; NMOS transistor NMR6[k], whose gate is connected to the first-stage output node SOBR[k], whose source is connected to the fifth node NETR5[k], and whose drain is connected to the fourth node NETR4[k]; NMOS transistor NMR7[k], whose gate is connected to the external enable signal SAEN, source is connected to the ground GND, and drain is connected to the fifth node NETR5[k]; The inverter INVR[k] has its input connected to the fourth node NETR4[k], and its output signal is the weight value DOUTR[k] and is divided into two paths, one of which is used to connect to the readout drive circuit and the other is connected to the weight bit line 2 RW[k].

9. The in-memory computing circuit structure according to claim 7, wherein: The mode selection module selects a mode according to an external enable signal MEN; When the external enable signal MEN is at a high level, the storage array module is in a standard read-write mode; When the external enable signal MEN is at a low level, the storage array module is in a multi-bit multiplication-accumulation calculation mode, the kth sense amplifier 1 is connected to the kth cascade calculation unit 1, and the kth sense amplifier 2 is connected to the kth cascade calculation unit 2.

10. The in-memory computing circuit structure according to claim 7, wherein: The quantization unit module includes a capacitor array, a successive approximation logic control unit, and a voltage comparator; The capacitor array includes capacitors C0, C1, C2, C3, and C4, the upper plates of the capacitors C0, C1, C2, C3, and C4 are all connected to the input node INP of the voltage comparator, and the lower plates of the capacitors C0, C1, C2, C3, and C4 are connected to the calculation bit line CBL / CBLB, the reference voltage VREF, and the power supply VDD through control switches S[0], S[1], S[2], S[3], and S[4] respectively; The successive approximation logic control unit uses successive approximation logic to generate a control signal S[4:0] for controlling the capacitor array to generate a voltage comparator enable signal EN and thus control the voltage comparator; The input node INN of the voltage comparator is connected to the common mode voltage VCM; when the control signal CE is turned on, the input nodes INP and INN are short-circuited, and the voltage comparator enable signal EN turns on the voltage comparator to compare the voltages of the input nodes INP and INN to generate an output Output.

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