A ring gate transistor and a manufacturing method thereof, a semiconductor device

Abstract

The application discloses a ring gate transistor and a manufacturing method thereof and a semiconductor device, and relates to the technical field of semiconductors. The length of a gate stack structure is limited, and the manufacturing process of the ring gate transistor is simplified. The ring gate transistor comprises a semiconductor substrate, a nano structure, a gate stack structure and a gate length control structure. At least one layer of the nano structure is formed on the semiconductor substrate. In the length direction of the nano structure, each layer of the nano structure comprises a source region, a drain region and a channel region between the source region and the drain region. The material of the source region and the drain region comprises a first metal semiconductor compound. The gate stack structure surrounds the outer periphery of the channel region. In the length direction of the gate stack structure, the sidewall of the gate stack structure is inwardly recessed relative to the sidewall of the channel region to form a notch. The gate length control structure fills the notch. The material of the gate length control structure is a second metal semiconductor compound, and the semiconductor material for manufacturing the second metal semiconductor compound is different from the semiconductor material for manufacturing the first metal semiconductor compound.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a ring gate transistor, a manufacturing method thereof, and a semiconductor device. BACKGROUND

[0002] The ring gate transistor has higher gate control ability than planar transistors and fin field effect transistors, and can improve the working performance of a semiconductor device including the ring gate transistor. The ring gate transistor includes an inner spacer formed between a source region and a gate stack structure, and between a drain region and the gate stack structure, to limit the length of the gate stack structure.

[0003] However, the forming process of the inner spacer included in the ring gate transistor is complicated, which reduces the manufacturing efficiency of the ring gate transistor. SUMMARY

[0004] The present application aims to provide a ring gate transistor, a manufacturing method thereof, and a semiconductor device, which can simplify the manufacturing process of the ring gate transistor while limiting the length of the gate stack structure.

[0005] To achieve the above-mentioned purpose, the present application provides a ring gate transistor, which includes: a semiconductor substrate,

[0006] at least one layer of nanostructure formed on the semiconductor substrate. Each layer of nanostructure has a gap between the semiconductor substrate. Along the length direction of the nanostructure, each layer of nanostructure includes a source region, a drain region, and a channel region between the source region and the drain region. The material of the source region and the drain region includes a first metal semiconductor compound.

[0007] a gate stack structure formed on the semiconductor substrate. The gate stack structure surrounds the outer periphery of the channel region. Along the length direction of the gate stack structure, the sidewall of the gate stack structure is recessed inwardly relative to the sidewall of the channel region, forming a notch.

[0008] and a gate length control structure filling the notch. The material of the gate length control structure is a second metal semiconductor compound, and the semiconductor material for manufacturing the second metal semiconductor compound is different from the semiconductor material for manufacturing the first metal semiconductor compound.

[0009] Compared with the prior art, in the ring gate transistor provided by the present application, at least one layer of nanostructure is formed on the semiconductor substrate. The material of the source region and the drain region included in the nanostructure includes a first metal semiconductor compound. Based on this, since the electrical conductivity of the metal semiconductor compound is greater than that of the semiconductor material, in the case where the material of the source region and the drain region of the nanostructure includes the first metal semiconductor compound, not only the contact resistance between the source region and the source electrode, and the contact resistance between the drain region and the drain electrode can be reduced, but also the electrical performance of the ring gate transistor can be improved.

[0010] In addition, the ring gate transistor further comprises a gate stack structure surrounding the channel region. Furthermore, along the length direction of the gate stack structure, the sidewall of the gate stack structure is recessed inwardly relative to the sidewall of the channel region, forming a notch. The gate length control structure included in the ring gate transistor fills the notch, so as to limit the length of the gate stack structure between the gate length control structures. In addition, the material of the gate length control structure is a second metal semiconductor compound, and the semiconductor material used to manufacture the second metal semiconductor compound is different from the semiconductor material used to manufacture the first metal semiconductor compound. Based on this, in the actual application process, the fin structure including at least one layer of stack can be formed on the semiconductor substrate. Each layer of stack includes a sacrificial layer and a channel layer on the sacrificial layer. Since the semiconductor material used to manufacture the second metal semiconductor compound is different from the semiconductor material used to manufacture the first metal semiconductor compound, and the materials used to manufacture the channel layer and the sacrificial layer are different semiconductor materials, the material of the channel layer can be set as the semiconductor material used to manufacture the first metal semiconductor compound, and the material of the sacrificial layer can be set as the semiconductor material used to manufacture the second metal semiconductor compound. In this case, after removing the part of each layer of sacrificial layer corresponding to the source region and the drain region, and depositing a metal layer covering the part of each layer of channel layer corresponding to the source region and the drain region, the remaining part of each layer of sacrificial layer along the length direction of the two side edges will also react with the metal layer to form the gate length control structure during the process of metallizing the part of each layer of channel layer corresponding to the source region and the drain region to form the source region and the drain region. Therefore, the source region and the drain region having the effect of reducing the contact resistance, and the gate length control structure having the effect of controlling the length of the gate stack structure can be formed at the same operation step, and the process of manufacturing the source region, the drain region and the gate length control structure is relatively simple, so that the manufacturing process of the ring gate transistor can be simplified, and the manufacturing efficiency of the ring gate transistor can be improved.

[0011] The application further provides a semiconductor device comprising the ring gate transistor provided in the technical solutions.

[0012] Compared with the prior art, the semiconductor device provided by the application has the beneficial effects of the ring gate transistor, which will not be repeated here.

[0013] The application further provides a manufacturing method of a ring gate transistor, which comprises the following steps:

[0014] A semiconductor substrate is provided.

[0015] Forming at least one nanostructure and a gate length control structure on a semiconductor substrate. The at least one nanostructure includes a source region, a drain region, and a channel region between the source region and the drain region along a length direction of the at least one nanostructure. The source region and the drain region are made of a first metal semiconductor compound. The gate length control structure is made of a second metal semiconductor compound, and the semiconductor material for making the second metal semiconductor compound is different from the semiconductor material for making the first metal semiconductor compound.

[0016] Forming a gate stack structure on the semiconductor substrate. The gate stack structure surrounds an outer periphery of the channel region. The gate stack structure has a side wall that is recessed inwardly relative to a side wall of the channel region along a length direction of the gate stack structure, forming a notch. The gate length control structure fills the notch.

[0017] Compared with the prior art, the method for manufacturing the ring gate transistor has the beneficial effects of the ring gate transistor, which are described above and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0019] Figure 1 A structure in a manufacturing process of a ring gate transistor according to an embodiment of the application Figure 1 ;

[0020] Figure 2 A structure in a manufacturing process of a ring gate transistor according to an embodiment of the application Figure 2 ;

[0021] Figure 3 A structure in a manufacturing process of a ring gate transistor according to an embodiment of the application Figure 3 ;

[0022] Figure 4 A structure in a manufacturing process of a ring gate transistor according to an embodiment of the application Figure 4 ;

[0023] Figure 5 A structure in a manufacturing process of a ring gate transistor according to an embodiment of the application Figure 5 ;

[0024] Figure 6 A structure in a manufacturing process of a ring gate transistor according to an embodiment of the application Figure 6 ;

[0025] Figure 7 A schematic diagram of the manufacturing process of a gate-ring transistor provided in an embodiment of the present invention. Figure 7 ;

[0026] Figure 8 A schematic diagram of the manufacturing process of a gate-ring transistor provided in an embodiment of the present invention. Figure 8 ;

[0027] Figure 9 A schematic diagram of the manufacturing process of a gate-ring transistor provided in an embodiment of the present invention. Figure 9 ;

[0028] Figure 10 A schematic diagram of the manufacturing process of a gate-ring transistor provided in an embodiment of the present invention. Figure 10 ;

[0029] Figure 11 A schematic diagram of the manufacturing process of a gate-ring transistor provided in an embodiment of the present invention. Figure 10 one;

[0030] Figure 12 A schematic diagram of the manufacturing process of a gate-ring transistor provided in an embodiment of the present invention. Figure 10 two;

[0031] Figure 13 A schematic diagram of the manufacturing process of a gate-ring transistor provided in an embodiment of the present invention. Figure 10 three;

[0032] Figure 14 A schematic diagram of the manufacturing process of a gate-ring transistor provided in an embodiment of the present invention. Figure 10 Four;

[0033] Figure 15 A schematic diagram of the manufacturing process of a gate-ring transistor provided in an embodiment of the present invention. Figure 10 five;

[0034] Figure 16 A schematic diagram of the manufacturing process of a gate-ring transistor provided in an embodiment of the present invention. Figure 10 six;

[0035] Figure 17 This is a flowchart illustrating a method for manufacturing a gate-ring transistor according to an embodiment of the present invention.

[0036] Reference numerals: 11 is a semiconductor substrate, 12 is a shallow trench isolation structure, 13 is a fin structure, 131 is a stack, 1311 is a sacrificial layer, 1312 is a channel layer, 14 is a first region, 15 is a second region, 16 is a third region, 17 is a sacrificial gate, 18 is a gate sidewall, 19 is a metal layer, 20 is a source region, 21 is a drain region, 22 is a first material portion, 23 is a second material portion, 24 is a gate length control structure, 25 is a dielectric layer, 26 is a first contact hole, 27 is a second contact hole, 28 is a source electrode, 29 is a drain electrode, 30 is a channel region, 31 is a gate stack structure, 311 is a gate dielectric layer, 312 is a gate electrode. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it is to be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0038] In the drawings, various structural diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and precision, and certain details can be omitted. The shapes of various regions, layers, and the relative size and positional relationship between them shown in the drawings are merely exemplary, and in actuality, they can deviate due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0039] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly located on the other layer / element, or an intermediate layer / element can be present therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present disclosure, the technical solutions and beneficial effects more clear and apparent, the present disclosure will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present disclosure and not to limit the present disclosure.

[0040] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implying a specific number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited. The meaning of "several" is one or more, unless otherwise explicitly and specifically limited.

[0041] In the description of the present application, it should be noted that unless specifically defined and limited otherwise, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0042] The channel included in the ring gate transistor has at least one layer of nanowire or sheet. Each layer of nanowire or sheet has a gap between the semiconductor substrate. And when the ring gate transistor includes at least two layers of nanowire or sheet, there is also a gap between adjacent nanowires or sheets. Based on this, the gate stack structure included in the ring gate transistor can be wrapped around the outer periphery of the corresponding part of each layer of nanowire or sheet through the above-mentioned gap. In other words, the gate stack structure included in the ring gate transistor can not only be formed on the top of each layer of nanowire or sheet, and on the sidewall in the width direction, but also on the bottom of each layer of nanowire or sheet, so that the ring gate transistor has the advantages of higher gate control capability and the like compared with planar transistors and fin field effect transistors, and can improve the working performance of semiconductor devices including the ring gate transistor. In actual application, the above-mentioned ring gate transistor includes an inner spacer formed between the source region and the gate stack structure, and between the drain region and the gate stack structure, to limit the length of the gate stack structure through the inner spacer.

[0043] However, the inner spacers included in the above-mentioned ring gate transistor are formed through a complicated process, which reduces the manufacturing efficiency of the ring gate transistor. The following takes an example of a channel included in a ring gate transistor having two layers of nanowires or sheets to briefly introduce the process of manufacturing the ring gate transistor: first, a fin structure is formed on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes two layers of stacks. Each layer of stack includes a sacrificial layer and a channel layer on the sacrificial layer. In addition, along the length direction of the fin structure, the fin structure includes a first region, a second region, and a third region between the first region and the second region. Next, a sacrificial gate and a gate sidewall are formed across the third region. The gate sidewall is formed at least on both sides of the sacrificial gate along the length direction. Then, the portions of the fin structure in the first region and the second region are removed, so that the edge portions of the third region along the length direction are exposed. The edge portions of the remaining sacrificial layer along the length direction are also removed, forming notches. Next, an inner spacer is formed to fill the notches by using processes such as deposition and etching. A source region is formed in at least the first region and a drain region is formed in at least the second region by using processes such as epitaxial growth. Then, the surfaces of the source region and the drain region can be subjected to a metallization process to form a metal semiconductor compound on the surfaces of the source region and the drain region, thereby reducing the contact resistance. A dielectric layer is formed on the semiconductor substrate, and then the sacrificial gate and the remaining sacrificial layer are removed, so that the portions of each channel layer in the third region form a corresponding nanowire or sheet. Since the inner spacer has an etching selectivity ratio with the sacrificial layer, and the remaining sacrificial layer is located between the inner spacers, the length of the gate formation region formed by removing the remaining sacrificial layer is easy to control. Finally, a gate stack structure is formed around the periphery of each nanowire or sheet.

[0044] As can be seen from the above manufacturing process, in order to form the inner spacer, not only the etching process is needed to remove the portions of the fin structure in the first region and the second region, but also deposition and etching processes are needed to form the inner spacer to fill the notches. In addition, in order to reduce the source-drain contact resistance, the surfaces of the source region and the drain region need to be subjected to a metallization process by using processes such as deposition, annealing, and etching, so that a metal semiconductor compound can be formed on the surfaces of the source region and the drain region. Moreover, the inner spacer and the metal semiconductor compound are formed in different operations, which makes the manufacturing process of the ring gate transistor complicated and reduces the manufacturing efficiency of the ring gate transistor.

[0045] To solve the above technical problems, the embodiment of the present application provides a ring gate transistor and a manufacturing method thereof, and a semiconductor device. In the ring gate transistor provided by the embodiment of the present application, the material of the source region and the drain region comprises a first metal semiconductor compound. The material of the gate length control structure for limiting the length of the gate stack structure is a second metal semiconductor compound. Moreover, the semiconductor material for manufacturing the second metal semiconductor compound is different from the semiconductor material for manufacturing the first metal semiconductor compound, so that the source region, the drain region and the gate length control structure can be formed simultaneously in the same operation step, the manufacturing process of the ring gate transistor is simplified, and the manufacturing efficiency of the ring gate transistor is improved.

[0046] As shown in Figure 16 , the embodiment of the present application provides a ring gate transistor. The ring gate transistor comprises a semiconductor substrate, a nanostructure, a gate stack structure 31 and a gate length control structure 24.

[0047] As shown in Figure 16 , at least one layer of the nanostructure is formed on the semiconductor substrate. There is a gap between each layer of the nanostructure and the semiconductor substrate. Along the length direction of the nanostructure, each layer of the nanostructure comprises a source region 20, a drain region 21 and a channel region 30 located between the source region 20 and the drain region 21. The material of the source region 20 and the drain region 21 comprises a first metal semiconductor compound. The gate stack structure 31 is formed on the semiconductor substrate. The gate stack structure 31 surrounds the outer periphery of the channel region 30. Along the length direction of the gate stack structure 31, the sidewall of the gate stack structure 31 is recessed inwardly relative to the sidewall of the channel region 30, forming a notch. The gate length control structure 24 fills the notch. The material of the gate length control structure 24 is a second metal semiconductor compound, and the semiconductor material for manufacturing the second metal semiconductor compound is different from the semiconductor material for manufacturing the first metal semiconductor compound.

[0048] Specifically, the above semiconductor substrate can be a semiconductor substrate on which no other structure is formed, such as a silicon substrate, a germanium-silicon substrate, a germanium substrate, a silicon-on-insulator substrate, etc. Alternatively, the semiconductor substrate can also be a semiconductor substrate on which some structures are formed. Specifically, the specific structure of the semiconductor substrate can be set according to the actual application scenario, which is not limited here.

[0049] For example: as shown in Figure 1 , if the ring gate transistor provided by the embodiment of the present application is applied to the ring gate transistor of the first layer included in the semiconductor device, the semiconductor substrate can comprise a semiconductor substrate 11 and a shallow trench isolation structure 12 for isolating different active regions of the semiconductor substrate 11. The material of the shallow trench isolation structure 12 can be an insulating material such as SiN, Si3N4, SiO2 or SiCO.

[0050] For example, if the gate-around transistor provided in this embodiment of the invention is applied to a gate-around transistor comprising a second or higher layer in a semiconductor device, the semiconductor substrate may at least include a semiconductor substrate, a first device structure formed on the semiconductor substrate, and a dielectric layer covering the first device structure. In this case, the materials of each part of the semiconductor substrate can be set according to actual needs, as long as they can be applied to the gate-around transistor provided in this embodiment of the invention.

[0051] For the aforementioned nanostructures, the gate-ring transistor can consist of a single nanostructure or multiple nanostructures. For example, Figure 16 As shown, when the gate-around transistor includes multiple nanostructures, the multiple nanostructures are spaced apart along the thickness direction of the semiconductor substrate. Specifically, the height of the gap between each nanostructure and the semiconductor substrate, as well as the height of the gap between adjacent nanostructures, can be determined based on the thickness of the gate stack structure 31, and is not specifically limited here.

[0052] From a materials perspective, the channel region within each nanostructure layer is made of semiconductor material. For example... Figure 16 As shown, the source region 20 and drain region 21 of the nanostructure may consist solely of the first metallic semiconductor material. Alternatively, as... Figure 8 As shown, each source region 20 and each drain region 21 includes a first material portion 22 and a second material portion 23 formed on the outer periphery of the first material portion 22. The material of the first material portion 22 is a semiconductor material. The material of the second material portion 23 is a first metal semiconductor compound, which is a compound of the aforementioned semiconductor material and a metal.

[0053] In practical applications, whether the source and drain regions consist only of the first metal semiconductor material, or the source and drain regions consist of the first metal semiconductor material and the semiconductor material used to manufacture the first material part, the semiconductor material used to manufacture the first metal semiconductor compound is the same as the material used in the channel region.

[0054] Furthermore, the types of materials used in the source and drain regions can be determined based on the actual manufacturing process. For example, Figure 6 and Figure 7 As shown, when metallizing the portions of the channel layer 1312 located in the first and second regions, if the processing time is long, the entire portion of the channel layer 1312 located in the first and second regions will react with the metal layer 19. Therefore, in this case, the material of the source region 20 and the drain region 21 obtained is only the first metal semiconductor compound. Figure 6 and Figure 8As shown, when the channel layer 1312 in the first region and the second region is subjected to the metalization process, if the processing time is short, only the surface of the channel layer 1312 in the first region and the second region reacts with the metal layer 19, and thus the material of the source region 20 and the drain region 21 obtained in this case includes the semiconductor material and the first metal semiconductor compound.

[0055] Secondly, the semiconductor material can be any one of silicon, silicon-germanium, germanium, or a group III-V compound. The first metal semiconductor compound can be any compound formed by the reaction of any metal with the semiconductor material, as long as it can be applied to the ring gate transistor provided in the embodiments of the present application.

[0056] For the gate stack structure, as shown, Figure 16 The gate stack structure 31 can include a gate dielectric layer 311 and a gate electrode 312. The gate dielectric layer 311 is formed on the outer periphery of the channel region 30 included in each layer of nanostructure. The material of the gate dielectric layer 311 can be an insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The gate electrode 312 is formed on the gate dielectric layer 311. The material of the gate electrode 312 can be a conductive material such as TiN, TaN, or TiSiN.

[0057] For the gate length control structure, the material of the gate length control structure is a second metal semiconductor compound. The semiconductor material used to manufacture the second metal semiconductor compound being different from the semiconductor material used to manufacture the first metal semiconductor compound can mean that the type of the semiconductor material used to manufacture the second metal semiconductor compound is different from the type of the semiconductor material used to manufacture the first metal semiconductor compound. For example, in the case where the semiconductor material used to manufacture the first metal semiconductor compound is silicon, the semiconductor material used to manufacture the second metal semiconductor compound can be a semiconductor material such as germanium or a group III-V compound.

[0058] It can also mean that the type of the semiconductor material used to manufacture the second metal semiconductor compound is the same as the type of the semiconductor material used to manufacture the first metal semiconductor compound, and the stoichiometric ratio of the elements in the semiconductor material used to manufacture the second metal semiconductor compound is different from the stoichiometric ratio of the elements in the semiconductor material used to manufacture the first metal semiconductor compound. For example, in the case where the semiconductor material used to manufacture the first metal semiconductor compound is Si 0.2 Ge 0.8 , the semiconductor material used to manufacture the second metal semiconductor compound can be a germanium-silicon material such as Si 0.6 Ge 0.4 .

[0059] In addition, the metal material for manufacturing the first metal semiconductor compound and the metal material for manufacturing the second metal semiconductor compound are the same. The type of the metal material can be set according to actual needs. The metal material can be nickel, platinum, titanium, or the like.

[0060] As for the length direction of the gate stack structure, the width of the gate length control structure can be set according to actual needs, which is not specifically limited here. For example, the width of the gate length control structure can be 3-10 nm along the length direction of the gate stack structure. For example, the width of the gate length control structure can be 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. In this case, the width of the gate length control structure in this range can prevent the need for a longer metallization process in the actual manufacturing process due to the larger width of the gate length control structure, further improving the manufacturing efficiency of the ring gate transistor. It can also prevent the gate length control structure from being difficult to block the corresponding etchant during the removal of the remaining sacrificial layer due to the smaller width of the gate length control structure, ensuring that the gate length control structure can limit the length of the gate stack structure.

[0061] From the above, as shown in Figure 16 The ring gate transistor provided by the embodiment of the present application has at least one nanostructure formed on the semiconductor substrate. The material of the source region 20 and the drain region 21 included in the nanostructure includes a first metal semiconductor compound. Based on this, since the electrical conductivity of the metal semiconductor compound is greater than that of the semiconductor material, in the case where the material of the source region 20 and the drain region 21 of the nanostructure includes the first metal semiconductor compound, not only can the contact resistance between the source region 20 and the source electrode 28 and the contact resistance between the drain region 21 and the drain electrode 29 be reduced, but also the electrical performance of the ring gate transistor can be improved.

[0062] In addition, as shown in Figure 16 The ring gate transistor further includes a gate stack structure 31 surrounding the outer periphery of the channel region 30. Moreover, along the length direction of the gate stack structure 31, the sidewall of the gate stack structure 31 is recessed inwardly relative to the sidewall of the channel region 30, forming a notch. The gate length control structure 24 included in the ring gate transistor fills the notch to limit the length of the gate stack structure 31 between the gate length control structures 24. In addition, the material of the gate length control structure 24 is a second metal semiconductor compound, and the semiconductor material for manufacturing the second metal semiconductor compound is different from the semiconductor material for manufacturing the first metal semiconductor compound. Based on this, in the actual application process, as shown in Figures 1 to 9As shown, the fin structure 13 including at least one layer stack 131 can be formed on the semiconductor substrate first. Each layer stack 131 includes a sacrificial layer 1311 and a channel layer 1312 on the sacrificial layer 1311. Since the semiconductor material for manufacturing the second metal semiconductor compound is different from the semiconductor material for manufacturing the first metal semiconductor compound, and the materials for manufacturing the channel layer 1312 and the sacrificial layer 1311 are different semiconductor materials, the material of the channel layer 1312 can be set as the semiconductor material for manufacturing the first metal semiconductor compound, and the material of the sacrificial layer 1311 can be set as the semiconductor material for manufacturing the second metal semiconductor compound. In this case, after removing the portions of each sacrificial layer 1311 corresponding to the source region 20 and the drain region 21, and depositing a metal layer 19 covering the portions of each channel layer 1312 corresponding to the source region 20 and the drain region 21, the portions of each channel layer 1312 corresponding to the source region 20 and the drain region 21 are subjected to a metallization process to form the source region 20 and the drain region 21, and the remaining portions of each sacrificial layer 1311 along the length direction of the two side edges will also react with the metal layer 19 to form the gate length control structure 24. Thus, the source region 20 and the drain region 21 having at least the effect of reducing the contact resistance, and the gate length control structure 24 having the effect of controlling the length of the gate stack structure 31 can be formed simultaneously in the same operation step, and the process of manufacturing the source region 20, the drain region 21 and the gate length control structure 24 is relatively simple, thereby simplifying the manufacturing process of the ring gate transistor and improving the manufacturing efficiency of the ring gate transistor.

[0063] In an example, as shown in FIG. 1, the ring gate transistor further includes a source electrode 28 and a drain electrode 29. The materials of the source electrode 28 and the drain electrode 29 are both metal materials. The source electrode 28 is connected to the source region 20, and the drain electrode 29 is connected to the drain region 21. Specifically, the formation range of the source electrode 28 and the drain electrode 29 can be divided into the following two cases: Figure 16

[0064] The first case is shown in FIG. 2 and FIG. 3. The source electrode 28 covers the outer periphery of each source region 20 and fills the space between each source region 20 and a first structure. The first structure includes at least a semiconductor substrate. The drain electrode 29 covers the outer periphery of each drain region 21 and fills the space between each drain region 21 and a second structure. The second structure includes at least a semiconductor substrate. Figure 12 Figure 16 Specifically, in the first case, if the ring gate transistor includes only one nanostructure, the first structure and the second structure include only a semiconductor substrate, respectively. The source electrode covers the outer periphery of the source region of the nanostructure and fills the space between the source region and the semiconductor substrate. The drain electrode covers the outer periphery of the drain region of the nanostructure and fills the space between the drain region and the semiconductor substrate.

[0065] The second case is shown in FIG. 4 and FIG. 5. The source electrode 28 covers the outer periphery of each source region 20 and fills the space between each source region 20 and a first structure. The first structure includes at least a semiconductor substrate. The drain electrode 29 covers the outer periphery of each drain region 21 and fills the space between each drain region 21 and a second structure. The second structure includes at least a semiconductor substrate.

[0066] ​​If the ring gate transistor comprises a multi-layer nanostructure, the first structure and the second structure are adjacent layer source regions and a semiconductor substrate, respectively. At this time, the source covers the periphery of each layer source region and fills the space between adjacent layer source regions and between the source region and the semiconductor substrate. The drain covers the periphery of each layer drain region and fills the space between adjacent layer drain regions and between the drain region and the semiconductor substrate.

[0067] In addition, in the first case, the ring gate transistor can further comprise a dielectric layer. The dielectric layer covers the semiconductor substrate and the top is flush with the top of the gate stack structure. The source and the drain region both penetrate the dielectric layer. The material of the dielectric layer can be an insulating material such as silicon oxide or silicon nitride.

[0068] Secondly, as shown in Figure 13 The ring gate transistor further comprises a dielectric layer 25, a source and a drain. The dielectric layer 25 covers the semiconductor substrate. The top of the dielectric layer 25 is flush with the top of the gate stack structure 31. Along the thickness direction of the semiconductor substrate, the dielectric layer 25 is provided with a first contact hole 26 and a second contact hole 27 penetrating the dielectric layer 25. The first contact hole 26 exposes part of each layer source region 20, and the second contact hole 27 exposes part of each layer drain region 21. The source fills the first contact hole 26. The drain fills the second contact hole 27.

[0069] Specifically, in the second case, along the length direction of the gate stack structure, the specific width of the first contact hole and the second contact hole can be set according to actual needs, as long as they are respectively smaller than the length of the source region and the drain region along the length direction of the gate stack structure.

[0070] As for the materials of the source and the drain in the first case and the second case, the materials of both can be metal materials such as titanium nitride, tungsten, copper, silver or gold.

[0071] It is worth noting that the materials of the source and the drain are metal materials, and the electrical conductivity of the metal material is greater than the electrical conductivity of the metal semiconductor compound and the electrical conductivity of the semiconductor material, respectively. Based on this, no matter whether the source and the drain are the corresponding formation range in the first case or the corresponding formation range in the second case, compared with the source region and the drain region being semiconductor materials and the source and the drain being respectively formed only on the top of the source region and the drain region, in the case that the source and the drain are respectively located between the source region and the first structure and between the drain region and the second structure, the source-drain parasitic resistance can be improved, the conduction current of the channel region located at the bottom can be increased, and thus the electrical characteristics of the ring gate transistor can be improved.

[0072] In one example, as shown in Figure 16As shown, the above-mentioned ring gate transistor can further include a gate side wall 18. The above-mentioned gate side wall 18 is formed at least on both sides of the gate stack structure 31 along the length direction to isolate the gate stack structure 31 from other conductive structures and improve the electrical characteristics of the ring gate transistor. The material of the gate side wall 18 can be an insulating material such as silicon oxide or silicon nitride.

[0073] The embodiment of the present application further provides a semiconductor device including the above-mentioned ring gate transistor provided by the above-mentioned embodiment.

[0074] Compared with the prior art, the semiconductor device provided by the embodiment of the present application has the beneficial effects of the ring gate transistor as described above, which will not be described herein again.

[0075] As shown in the drawings, the embodiment of the present application provides a manufacturing method of a ring gate transistor. Hereinafter, the manufacturing process will be described according to the perspective view or sectional view of the operation shown in the drawings. Specifically, the manufacturing method of the ring gate transistor includes the following steps: Figure 17 As shown in the drawings, the embodiment of the present application provides a manufacturing method of a ring gate transistor. Hereinafter, the manufacturing process will be described according to the perspective view or sectional view of the operation shown in the drawings. Specifically, the manufacturing method of the ring gate transistor includes the following steps: Figures 1 to 16

[0076] Firstly, a semiconductor substrate is provided. Specifically, the specific structure and material of the semiconductor substrate can be referred to the above, which will not be described herein again.

[0077] As shown in the drawings, the embodiment of the present application provides a manufacturing method of a ring gate transistor. Hereinafter, the manufacturing process will be described according to the perspective view or sectional view of the operation shown in the drawings. Specifically, the manufacturing method of the ring gate transistor includes the following steps: Figure 8 and Figure 9 As shown in the drawings, the embodiment of the present application provides a manufacturing method of a ring gate transistor. Hereinafter, the manufacturing process will be described according to the perspective view or sectional view of the operation shown in the drawings. Specifically, the manufacturing method of the ring gate transistor includes the following steps:

[0078] Specifically, the number of layers of the nanometer structure formed on the semiconductor substrate, the material of the source region, the drain region and the channel region included in the nanometer structure and other information can be referred to the above, which will not be described herein again.

[0079] In actual application process, the above-mentioned forming at least one layer of nanometer structure and gate length control structure on the semiconductor substrate can include the following steps:

[0080] As shown in the drawings, the embodiment of the present application provides a manufacturing method of a ring gate transistor. Hereinafter, the manufacturing process will be described according to the perspective view or sectional view of the operation shown in the drawings. Specifically, the manufacturing method of the ring gate transistor includes the following steps: Figure 1 ​As shown, a fin structure 13 is formed on the semiconductor substrate. The fin structure 13 comprises at least one layer stack 131, each layer stack 131 comprising a sacrificial layer 1311 and a channel layer 1312 on the sacrificial layer 1311. Along the length direction of the fin structure 13, the fin structure 13 has a first region 14, a second region 15, and a third region 16 between the first region 14 and the second region 15.

[0081] Specifically, the channel layer is a film layer for manufacturing the nanostructure, and thus the number of layer stacks included in the fin structure is equal to the number of nanostructures included in the ring gate transistor. In addition, the material of the channel layer is the same as the material of the channel region included in the nanostructure. Meanwhile, the material of the channel layer is also a semiconductor material for manufacturing the first metal semiconductor compound. As for the sacrificial layer, the sacrificial layer is a film layer for manufacturing the gap between the nanostructure and the semiconductor substrate, and between adjacent nanostructures, and thus the thickness of the sacrificial layer can be set according to the thickness of the gate stack structure as described above. In addition, the sacrificial layer is also a film layer for manufacturing the gate length control structure, and thus the material of the sacrificial layer is a semiconductor material for manufacturing the second metal semiconductor compound.

[0082] For example, the sacrificial material layer and the channel material layer can be formed by epitaxial growth or other processes. Next, the sacrificial material layer and the channel material layer stacked together, and part of the semiconductor substrate can be etched by photolithography and etching or other processes to form a fin on the semiconductor substrate. Finally, as shown, Figure 1 For example, the sacrificial material layer and the channel material layer can be formed by epitaxial growth or other processes. Next, the sacrificial material layer and the channel material layer stacked together, and part of the semiconductor substrate can be etched by photolithography and etching or other processes to form a fin on the semiconductor substrate. Finally, as shown,

[0083] In actual applications, the gate stack structure included in the ring gate transistor is usually formed by a replacement gate process to improve the formation quality of the manufactured gate stack structure. In this case, after the fin structure is formed on the semiconductor substrate, the method for manufacturing the ring gate transistor further comprises the step of: Figures 2 to 4 For example, the sacrificial material layer and the channel material layer can be formed by epitaxial growth or other processes. Next, the sacrificial material layer and the channel material layer stacked together, and part of the semiconductor substrate can be etched by photolithography and etching or other processes to form a fin on the semiconductor substrate. Finally, as shown,

[0084] It should be noted that in addition to forming the above-mentioned sacrificial gate and gate side wall, a mask layer can also be formed across the part of the fin structure corresponding to the third region, so as to protect the channel layer and the part of the sacrificial layer located in the third region through the mask layer in subsequent operations. The material of the mask layer can be silicon nitride or other materials.

[0085] As shown in Figure 5 , the part of each layer of the sacrificial layer 1311 located in the first region and the second region is removed.

[0086] Exemplarily, dry etching or wet etching process can be adopted to remove the part of each layer of the sacrificial layer located in the first region and the second region under the mask effect of the sacrificial gate and the gate side wall (or the above-mentioned mask layer). At this time, the top, bottom and outer sidewall of the part of each layer of the channel layer located in the first region and the second region are exposed. The two side edge regions of the remaining each layer of the sacrificial layer along the length direction are also exposed.

[0087] As shown in Figure 7 and Figure 8 , the part of each layer of the channel layer located in the first region and the second region, and the two side edge regions of the remaining each layer of the sacrificial layer 1311 along the length direction are subjected to a metallization process, so that the part of each layer of the channel layer 1312 located in the first region forms a corresponding layer source region 20, so that the part of each layer of the channel region 30 located in the second region forms a corresponding layer drain region 21, and a corresponding layer gate length control structure 24 is formed in the two side edge regions of each layer of the sacrificial layer 1311 along the length direction.

[0088] Exemplarily, the above-mentioned metallization process on the part of each layer of the channel layer located in the first region and the second region, and the two side edge regions of the remaining each layer of the sacrificial layer along the length direction can include the following steps:

[0089] As shown in Figure 6 , an upper metal layer 19 is formed covering the outer periphery of the part of each layer of the channel layer 1312 corresponding to the first region and the second region, and the two side edge regions of the remaining each layer of the sacrificial layer 1311 along the length direction.

[0090] In actual application process, chemical vapor deposition process can be adopted to form the above-mentioned metal layer. Among them, as shown in Figure 6As shown, the metal layer 19 can fill the gap between each source region and the first structure, and the gap between each drain region and the second structure. Alternatively, the thickness of the metal layer can be relatively small, covering only the outer periphery of the first region and the second region corresponding to each channel layer, and the remaining two side edge regions of each sacrificial layer along the length direction, and not filling the gap between each source region and the first structure, and the gap between each drain region and the second structure. Specifically, the thickness of the metal layer can be set according to the actual application scenario, as long as it can be applied to the manufacturing method of the ring gate transistor provided in the embodiments of the present application. In addition, the material of the metal layer can be determined by referring to the metal materials for manufacturing the first metal semiconductor compound and the metal materials for manufacturing the second metal semiconductor compound described above.

[0091] For example, the metal layer can be a stack of a titanium layer and a titanium nitride layer. The titanium nitride layer is covered on the titanium layer to prevent the titanium layer from reacting with the residual oxygen in the reaction chamber during the annealing process, ensuring that the gate length control structure has a high formation quality. Specifically, the thickness of the titanium layer can be 3-10 nm. The thickness of the titanium nitride layer can be 5-10 nm. Of course, the thickness of the titanium layer and the titanium nitride layer can also be set to other suitable values according to different application scenarios, which are not limited here.

[0092] As shown in Figure 7 and Figure 8 The formed structure is subjected to an annealing process to form the source region 20, the drain region 21 and the gate length control structure 24.

[0093] Specifically, the conditions of the annealing process can be determined according to the size of the channel layer, the material of the source region and the drain region, and the width of the gate length control structure along the length direction of the gate stack structure. It can be understood that in the case where the material of the source region and the drain region is only the first metal semiconductor compound, the values corresponding to the processing time and / or processing temperature of the annealing process are relatively large. In the case where the material of the source region and the drain region includes a semiconductor material and a first metal semiconductor compound, the values corresponding to the processing time and / or processing temperature of the annealing process are relatively small.

[0094] In addition, when the width of the gate length control structure along the length direction of the gate stack structure is small, the values corresponding to the processing time and / or processing temperature of the annealing process are also relatively small. Conversely, when the width of the gate length control structure along the length direction of the gate stack structure is large, the values corresponding to the processing time and / or processing temperature of the annealing process are also relatively large.

[0095] For example, the annealing process can be carried out in a nitrogen atmosphere, the temperature of the annealing process can be 500-700°C, and the annealing time can be 30s.

[0096] Then, as shown in Figure 9 , a wet etching process or the like can be used to remove the remaining metal layer. The etching solution used in the wet etching process can be set according to the actual application scenario. For example, aqua regia or the like can be used to remove the remaining metal layer.

[0097] It is worth noting that, during the above-mentioned metallization process, the source region and the drain region having at least the effect of reducing the contact resistance, and the gate length control structure having the effect of controlling the length of the gate stack structure can be formed at the same operation step, and the process of manufacturing the source region, the drain region and the gate length control structure is relatively simple, thereby simplifying the manufacturing process of the ring gate transistor and improving the manufacturing efficiency of the ring gate transistor.

[0098] For example, as described above, in the case where the manufactured ring gate transistor further includes a source and a drain, after the metallization process is performed on the part of each channel layer located in the first region and the second region, and the remaining two side edge regions of each sacrificial layer along the length direction, before the subsequent operation is performed, the manufacturing method of the above-mentioned ring gate transistor further includes: forming a source and a drain on the semiconductor substrate. The materials of the source and the drain are both metal materials.

[0099] In addition, as shown in Figure 12 and Figure 14 , the above-mentioned source 28 can cover the outer periphery of each source region 20 and fill the space between each source region 20 and the first structure. The first structure at least includes a semiconductor substrate. The drain 29 covers the outer periphery of each drain region 21 and fills the space between each drain region 21 and the second structure. The second structure at least includes a semiconductor substrate. Alternatively, as shown in Figure 13 , the above-mentioned source only fills the first contact hole exposing part of the source region 20, and the above-mentioned drain only fills the second contact hole 27 exposing part of the drain region 21.

[0100] In actual application, whether the source and the drain are the first structure or the second structure, as shown in Figure 10 , a chemical vapor deposition process or the like can be used to form a dielectric layer 25 covering the semiconductor substrate. The top of the dielectric layer 25 is flush with the top of the gate stack structure. At this time, the sacrificial gate 17 (or the above-mentioned mask layer) is exposed outside the dielectric layer 25. The material of the dielectric layer 25 can be referred to the above. Then, a photolithography and etching process or the like can be used to open a contact window penetrating the dielectric layer 25 in the dielectric layer 25 along the thickness direction of the semiconductor substrate. The width of the contact window along the length direction of the gate stack structure can be determined according to the size of the source and the drain.

[0101] For example, as shown in Figure 12 and Figure 14As shown, when the source 28 and drain 29 to be manufactured are the source 28 and drain 29 in the first case, the width of the contact window corresponding to the source region 20 is greater than or equal to the length of the source region 20 along the length direction of the gate stack structure. The width of the contact window corresponding to the drain region 21 is greater than or equal to the length of the drain region 21 along the length direction of the gate stack structure.

[0102] For example: Figure 13 As shown, when the source and drain to be manufactured are the source and drain in the second case, the contact window corresponding to the source region is the first contact hole 26. The contact window corresponding to the drain region is the second contact hole 27. In this case, the manufacturing step of forming a contact window penetrating the dielectric layer 25 in the dielectric layer 25 along the thickness direction of the semiconductor substrate is as follows: forming a first contact hole 26 and a second contact hole 27 penetrating the dielectric layer 25 in the dielectric layer 25 along the thickness direction of the semiconductor substrate. The first contact hole 26 exposes a portion of the source region of each layer, and the second contact hole 27 exposes a portion of the drain region of each layer.

[0103] Then, as Figure 14 As shown, in the first case, a deposition process can be used to form the source 28 and the drain 29 within the corresponding contact windows, respectively. In the second case, a deposition process can be used to form a source that fills the first contact hole and a drain that fills the second contact hole.

[0104] Finally, as Figure 16 As shown, a gate stack structure 31 is formed on a semiconductor substrate. The gate stack structure 31 surrounds the outer periphery of the channel region 30. Along the length direction of the gate stack structure 31, the sidewalls of the gate stack structure 31 are recessed inward relative to the sidewalls of the channel region 30, forming a notch. The gate length control structure 24 fills the notch.

[0105] Specifically, the specific structure and materials of each component in the gate stack structure can be found in the previous text and will not be repeated here.

[0106] In practical applications, before forming the gate stack structure, dry etching or wet etching processes can be used to remove the sacrificial gate (or the aforementioned mask layer) to expose the remaining sacrificial layer. Next, as... Figure 15 As shown, dry etching or wet etching processes can be used to remove the portion of each sacrificial layer located between the gate length control structures 24, so that the portion of each channel layer located in the third region forms the corresponding channel region 30. Finally, as... Figure 16 As shown, atomic layer deposition and other processes can be used to form a gate stack structure 31 surrounding the outer periphery of each channel region 30.

[0107] Compared with the prior art, the manufacturing method of the ring gate transistor provided by the embodiment of the present application has the beneficial effects of the ring gate transistor, which have been described above, and will not be described here again.

[0108] In the above description, the technical details of patterning, etching and the like of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0109] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A gate-ring transistor, characterized in that, include: Semiconductor substrate, At least one layer of nanostructure is formed on the semiconductor substrate; each layer of nanostructure has a void between it and the semiconductor substrate. Along the length of the nanostructure, each layer of the nanostructure includes a source region, a drain region, and a channel region located between the source region and the drain region; the material of the source region and the drain region includes a first metal semiconductor compound; A gate stack structure is formed on the semiconductor substrate; the gate stack structure surrounds the outer periphery of the channel region; Along the length of the gate stack structure, the sidewall of the gate stack structure is recessed inward relative to the sidewall of the channel region to form a notch; And a gate length control structure that fills the notch; the material of the gate length control structure is a second metal semiconductor compound, and the semiconductor material used to manufacture the second metal semiconductor compound is different from the semiconductor material used to manufacture the first metal semiconductor compound.

2. The gate-ring transistor according to claim 1, characterized in that, The gate-ring transistor further includes a source and a drain; both the source and the drain are made of metallic materials. The source electrode covers the outer periphery of each layer of the source region and fills the space between each layer of the source region and the first structure; the first structure includes at least the semiconductor substrate; The drain covers the outer periphery of each drain region and fills the space between each drain region and the second structure; the second structure includes at least the semiconductor substrate.

3. The gate-ring transistor according to claim 1, characterized in that, The ring gate transistor further includes: A dielectric layer covers the semiconductor substrate; the top of the dielectric layer is flush with the top of the gate stack structure; along the thickness direction of the semiconductor substrate, a first contact hole and a second contact hole are formed in the dielectric layer, the first contact hole exposing a portion of the source region of each layer, and the second contact hole exposing a portion of the drain region of each layer; The source electrode fills the first contact hole; And a drain electrode, filling the second contact hole; both the drain electrode and the source electrode are made of metallic materials.

4. The gate-ring transistor according to claim 1, characterized in that, Each source region and each drain region of each layer includes a first material portion and a second material portion formed on the periphery of the first material portion; The material of the first material section is a semiconductor material; The material of the second material part is the first metal semiconductor compound, which is a compound of the semiconductor material and the metal.

5. The gate-to-ring transistor according to claim 1, characterized in that, The type of semiconductor material used to manufacture the second metal semiconductor compound is different from the type of semiconductor material used to manufacture the first metal semiconductor compound; or, The type of semiconductor material used to manufacture the second metal semiconductor compound is the same as the type of semiconductor material used to manufacture the first metal semiconductor compound, and the stoichiometric ratio of each element in the semiconductor material used to manufacture the second metal semiconductor compound is different from the stoichiometric ratio of each element in the semiconductor material used to manufacture the first metal semiconductor compound.

6. The gate-to-ring transistor according to claim 1, characterized in that, Along the length direction of the gate stack structure, the width of the gate length control structure is 3nm to 10nm.

7. The gate-ring transistor according to any one of claims 1 to 6, characterized in that, The gate-ring transistor comprises a multilayer nanostructure; the multilayer nanostructures are spaced apart along the thickness direction of the semiconductor substrate.

8. A semiconductor device, characterized in that, Includes the gate ring transistor as described in any one of claims 1 to 7.

9. A method for manufacturing a gate-ring transistor, characterized in that, include: Provide a semiconductor substrate; At least one layer of nanostructure and gate length control structure is formed on the semiconductor substrate; Each layer of the nanostructure has a gap between it and the semiconductor substrate; Along the length of the nanostructure, the at least one layer of the nanostructure includes a source region, a drain region, and a channel region located between the source region and the drain region; the material of the source region and the drain region includes a first metal semiconductor compound; the material of the gate length control structure is a second metal semiconductor compound, and the semiconductor material used to manufacture the second metal semiconductor compound is different from the semiconductor material used to manufacture the first metal semiconductor compound; A gate stack structure is formed on the semiconductor substrate; the gate stack structure surrounds the outer periphery of the channel region. Along the length of the gate stack structure, the sidewall of the gate stack structure is recessed inward relative to the sidewall of the channel region to form a notch; the gate length control structure fills the notch.

10. The method for manufacturing a gate-to-ring transistor according to claim 9, characterized in that, The formation of at least one nanostructure and gate length control structure on the semiconductor substrate includes: A fin structure is formed on the semiconductor substrate; the fin structure includes at least one stack, each of the stacks including a sacrificial layer and a channel layer located on the sacrificial layer; along the length direction of the fin structure, the fin structure has a first region, a second region, and a third region located between the first region and the second region; Remove the portion of each sacrificial layer located within the first and second regions; The portion of each channel layer located in the first region and the second region, as well as the remaining two side edge regions of each sacrificial layer along the length direction, are metallized to form the source region of the corresponding layer in the portion of each channel layer located in the first region, the drain region of the corresponding layer in the portion of each channel layer located in the second region, and the gate length control structure of the corresponding layer is formed in the two side edge regions of each sacrificial layer along the length direction.

11. The method for manufacturing a gate-to-ring transistor according to claim 10, characterized in that, The metallization process for the portion of each channel layer located within the first and second regions, and the remaining sacrificial layers along both sides of their length direction, includes: An upper metal layer is formed covering the outer periphery of the portion of each channel layer corresponding to the first and second regions, and the remaining two edge regions of each sacrificial layer along the length direction; The formed structure is annealed to form the source region, the drain region, and the gate length control structure; Remove the remaining metal layer.

12. The method for manufacturing a gate-to-ring transistor according to claim 10, characterized in that, After forming the fin-like structure on the semiconductor substrate, and before removing the portion of each sacrificial layer located in the first and second regions, the method for manufacturing the ring-gate transistor further includes: A sacrificial gate and a gate sidewall are formed across the portion of the fin structure corresponding to the third region; the gate sidewall is formed at least on both sides of the sacrificial gate along its length.

13. The method for manufacturing a gate-to-ring transistor according to claim 10, characterized in that, After metallizing the portion of each channel layer located in the first region and the second region, and the remaining two edge regions of each sacrificial layer along the length direction, the method for manufacturing the ring-gate transistor before forming the gate stack structure on the semiconductor substrate further includes: A source and a drain are formed on the semiconductor substrate; wherein, The source and drain are both made of metallic materials; the source covers the top of the source region located at the top layer and fills the space between each layer of the source region and the first structure; the first structure includes at least the semiconductor substrate; the drain covers the top of the drain region located at the top layer and fills the space between each layer of the drain region and the second structure; the second structure includes at least the semiconductor substrate.

14. The method for manufacturing a gate-to-ring transistor according to claim 10, characterized in that, After metallizing the portion of each channel layer located in the first region and the second region, and the remaining two edge regions of each sacrificial layer along the length direction, the method for manufacturing the ring-gate transistor before forming the gate stack structure on the semiconductor substrate further includes: A dielectric layer is formed covering the semiconductor substrate; the top of the dielectric layer is flush with the top of the gate stack structure. Along the thickness direction of the semiconductor substrate, a first contact hole and a second contact hole are formed in the dielectric layer, penetrating the dielectric layer; the first contact hole exposes a portion of the source region in each layer, and the second contact hole exposes a portion of the drain region in each layer; This forms a source electrode that fills the first contact hole; A drain electrode is formed that fills the second contact hole; both the drain electrode and the source electrode are made of metallic materials.

15. The method for manufacturing a gate-to-ring transistor according to claim 10, characterized in that, The formation of the gate stack structure on the semiconductor substrate includes: Remove the portion of each sacrificial layer located between the gate length control structures, such that the portion of each channel layer located in the third region forms a corresponding channel region; The gate stack structure is formed around the periphery of the channel region in each layer.

Images