Manufacturing method of LED silver mirror chip

Abstract

The present application relates to the field of semiconductor electronic technology, particularly relates to a kind of LED silver mirror chip manufacturing method.The manufacturing method is evaporated on GaN epitaxial wafer ITO conductive layer, then deposit a layer of etching mask, the Mesa step surface is obtained by etching mask photolithography, etching, then using photoresist covers Mesa step surface, etching gets cutting path;BOE solution is used to etch the remaining silicon dioxide, then evaporate silver mirror after photolithography again, obtain current expansion layer and reflective layer, finally, silicon dioxide protective layer and metal electrode pad layer are prepared in sequence.The manufacturing method is prepared by adjusting steps, one-time photolithography is realized, the area of GaN layer and the area of ITO on it can be maximized to retain, and its luminous efficiency is increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor electronics, in particular to a manufacturing method of LED silver mirror chip. BACKGROUND

[0002] LED (Light Emitting Diode) is a kind of semiconductor component, which is often used as indicator light, display screen and illumination, and becomes the fourth generation of illumination light source or green light source.

[0003] The Chinese invention patent with publication number CN113299810A discloses a flip-chip silver mirror LED chip and a manufacturing method of the chip. The photoetching technology is used to make a regular array pattern on the P-type gallium nitride surface of the flip-chip epitaxial wafer. After the light passes through these patterns, the total reflection is reduced, and the light extraction rate is improved. The P-type gallium nitride surface is patterned to increase the Ag reflection area and improve the light output of the LED. However, this method needs to be photoetched multiple times, and about 4 mu m photoetching offset window is set each time to prevent electric leakage and other electrical problems. Therefore, the more the number of photoetching used, the higher the manufacturing difficulty, and the more photoetching offset windows need to be reserved, resulting in great waste of light emitting area. SUMMARY

[0004] In order to overcome the defects of the prior art, the technical problem to be solved by the present application is to provide a manufacturing method of LED silver mirror chip, which has fewer photoetching times and large light emitting area.

[0005] In order to solve the above technical problems, the technical scheme adopted by the present application is as follows: a manufacturing method of LED silver mirror chip, comprising the following steps:

[0006] S1: evaporating an ITO conductive layer on a GaN epitaxial wafer, and then depositing a layer of silicon dioxide as an etching mask;

[0007] S2: photoetching the etching mask to obtain Mesa photoetching pattern and cutting path photoetching pattern;

[0008] S3: first, etching the silicon dioxide of the cutting path photoetching pattern and the Mesa photoetching pattern with BOE solution, then etching the ITO conductive layer with ITO etching solution, and then etching to obtain Mesa step surface;

[0009] S4: covering the Mesa step surface with photoresist, and then etching to obtain cutting path;

[0010] S5: etching the remaining silicon dioxide with BOE solution;

[0011] S6: evaporating silver mirror after photoetching again to obtain current expansion layer and reflection layer;

[0012] S7: depositing a layer of silicon dioxide and etching to obtain a silicon dioxide protective layer;

[0013] S8: evaporating P-type and N-type pads to obtain a metal electrode pad layer, and injecting etching holes to connect and conduct with the current spreading layer.

[0014] The LED silver mirror chip manufacturing method of the present application has the following advantages: after the ITO and silicon dioxide are evaporated, the Mesa photoetching pattern and the cutting path photoetching pattern are photoetched at one time, then layer-by-layer etching is performed, and the current spreading layer and the reflection layer are synchronously photoetched and evaporated. Thus, the original five (or four) etching processes are reduced to two, the number of photoetching is reduced, the exposure deviation is reduced, the P-GaN and ITO to be etched are reduced, the area of the GaN layer and the area of the ITO thereon are maximally reserved, the light emitting efficiency is increased, and the brightness is improved. Reducing the number of photoetching can also reduce the multi-process flow and shorten the processing time, thereby saving the cost. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 Fig. 1 shows the product structure of S1 of the LED silver mirror chip manufacturing method of the first embodiment of the present application;

[0016] Figure 2 Fig. 3 shows the product structure of S3 of the LED silver mirror chip manufacturing method of the first embodiment of the present application;

[0017] Figure 3 Fig. 4 shows the product structure of S4 of the LED silver mirror chip manufacturing method of the first embodiment of the present application;

[0018] Figure 4 Fig. 5 shows the product structure of S5 of the LED silver mirror chip manufacturing method of the first embodiment of the present application;

[0019] Figure 5 Fig. 6 shows the product structure of S6 of the LED silver mirror chip manufacturing method of the first embodiment of the present application;

[0020] Figure 6 Fig. 7 shows the product structure of S7 of the LED silver mirror chip manufacturing method of the first embodiment of the present application;

[0021] Figure 7 Fig. 8 shows the product structure of S8 of the LED silver mirror chip manufacturing method of the first embodiment of the present application;

[0022] Label explanation: 1, sapphire substrate; 2, N-type semiconductor layer; 3, multi-quantum well layer; 4, P-type semiconductor layer; 5, ITO conductive layer; 6, etching mask; 7, current spreading layer; 8, reflection layer; 9, silicon dioxide protective layer; 10, metal electrode pad layer; 11, cutting path. DETAILED DESCRIPTION

[0023] To make the technical contents of the present application, the achieved purposes and effects clear, the following will be described in detail in combination with the embodiments and the accompanying drawings.

[0024] The most key idea of the present application is to adjust the preparation steps to realize one-time photolithography, to maximize the area of the GaN layer and the area of ITO thereon, and to increase the light-emitting efficiency.

[0025] Please refer to Figures 1 to 7 The manufacturing method of the LED silver mirror chip of the present application comprises the following steps:

[0026] S1: evaporating ITO (tin oxide) conductive layer on GaN epitaxial wafer, and then depositing a layer of silicon dioxide as etching mask;

[0027] S2: performing photolithography on the etching mask to obtain Mesa photolithography pattern and cutting path photolithography pattern;

[0028] S3: etching the silicon dioxide of the cutting path photolithography pattern and the Mesa photolithography pattern with BOE solution first, then etching the ITO conductive layer with ITO etching solution, and then etching to obtain Mesa step surface;

[0029] S4: covering the Mesa step surface with photoresist, and then etching to obtain cutting path;

[0030] S5: etching the remaining silicon dioxide with BOE solution;

[0031] S6: evaporating silver mirror after re-photolithography to obtain current expansion layer and reflection layer;

[0032] S7: depositing a layer of silicon dioxide and etching to obtain silicon dioxide protective layer;

[0033] S8: evaporating P-type pad and N-type pad to obtain metal electrode pad layer, and injecting etching hole to connect and conduct with the current expansion layer.

[0034] From the above description, the beneficial effects of the present application are that: in the prior art, when preparing the LED silver mirror chip, it is necessary to evaporate (or deposit) layer by layer, photoetch and etch, because the more layers that are added on the epitaxial wafer, the more times of photoetching are needed. In the present application, after evaporating ITO and silicon dioxide, Mesa photoetching pattern and cutting path photoetching pattern are photoetched at one time, and then layer-by-layer etching is carried out, and then current expansion layer and reflection layer are synchronously photoetched and evaporated, so that the original five (or four) etching is reduced to two. The number of photoetching is reduced, the exposure deviation can be reduced, the etched P-GaN and ITO are reduced, the area of GaN layer and the area of ITO thereon are maximized, the luminous efficiency is increased, and the brightness is improved. Reducing the number of photoetching can also reduce the multi-process flow, shorten the processing time, and save the cost.

[0035] The silicon dioxide protective layer prevents the silver mirror from being oxidized and prevents impurities such as moisture from being oxidized and corroded.

[0036] The cutting path includes Mesa cutting path and ISO cutting path, and the two cutting paths are synchronously photoetched and etched in the present application, the number of photoetching is reduced, and the luminous efficiency is increased.

[0037] Further, the thickness of the ITO conductive layer is 200-300 nm.

[0038] Further, the thickness of the etching mask is 200-300 nm. Preferably, the thickness of the etching mask is 250 nm.

[0039]

[0040] From the above description, the etching mask provides a sufficient window for preventing over-etching in etching.

[0041] Further, the specific steps of S2 are: coating positive photoresist on the etching mask, and then sequentially drying, exposing and developing to obtain Mesa photoetching pattern and cutting path photoetching pattern.

[0042] From the above description, the Mesa photoetching pattern and the cutting path photoetching pattern are obtained at one time, the exposure deviation can be reduced, and the luminous area is increased.

[0043] Further, the coating thickness of the positive photoresist is 2.3-2.5 μm, and the exposure amount of exposure is 75-85 mj. Preferably, the coating thickness of the positive photoresist is 2.4 μm, and the exposure amount of exposure is 80 mj.

[0044] Further, the width of the cutting path photoetching pattern is 3-5 μm. Preferably, the width of the cutting path photoetching pattern is 4 μm.

[0045] As can be seen from the above description, the smaller the cutting path is, the higher the yield of the chip is; but when the cutting path is too small, it is difficult for the cutting tool to be accurately positioned.

[0046] Further, the side etching amount of the ITO etching solution in S3 is 5-7 μm.

[0047] As can be seen from the above description, the core particle spacing of the ITO obtained by the prior art is 34 μm, but under the photolithography process of the present application, the spacing can be reduced to 18-22 μm, i.e. the single-side ITO is enlarged by 7 μm, and the luminous area of the chip is increased.

[0048] Further, the etching depth of the Mesa step surface in S3 is 5-7 μm.

[0049] Further, the etching time in S4 is 900 s, the gas flow is 155 cfm, and the etching depth is 5-7 μm.

[0050] As can be seen from the above description, the etching time of the original ISO etching is 1800 s, and the etching time is shortened to adapt to the synchronous etching of the ISO cutting path and the Mesa cutting path.

[0051] Further, the width of the cutting path is 14-18 μm.

[0052] As can be seen from the above description, the smaller the cutting path is, the higher the yield of the chip is; the minimum width of the cutting path is determined by the cutting tool.

[0053] Further, the thickness of the current spreading layer and the reflective layer is 100-200 nm.

[0054] Further, the thickness of the current spreading layer and the reflective layer is 100-200 nm. Preferably, the thickness of the current spreading layer and the reflective layer is 100-200 nm.

[0055] Further, the thickness of the silicon dioxide protective layer is 100-200 nm. Preferably, the thickness of the silicon dioxide protective layer is 100-200 nm.

[0056] As can be seen from the above description, the function of the silicon dioxide protective layer is to protect the core particles from oxidation of Ag, impurity pollution, etc.

[0057] Please refer to Figures 1 to 7 The embodiment one of the present application is a manufacturing method of an LED silver mirror chip, comprising the following steps:

[0058] S1: using metal organic chemical vapor deposition method on sapphire substrate 1 in turn growth of gallium nitride-based N-type semiconductor layer 2, multi quantum well layer 3 and P-type semiconductor layer 4, get GaN wafer;

[0059] S2: on the GaN wafer evaporation thickness of ITO (tin oxide) conductive layer 5, and then deposit a layer of silicon dioxide as etching mask 6, the thickness of etching mask 6 is

[0060] S3: on the etching mask 6 coated 2.4 μm positive photoresist, and then in turn through 110 ℃ 90 s drying, exposure amount is 80 mj exposure, and then at 135 ℃ develop 90 s, get Mesa lithography pattern, overlay pattern and cutting way lithography pattern, the width of cutting way lithography pattern is 4 μm;

[0061] S4: first using BOE solution to etch cutting way lithography pattern and Mesa lithography pattern of silicon dioxide, and then using ITO etching solution to etch ITO conductive layer 5, and then etching out N-GaN to get Mesa step surface and overlay, the etching depth of Mesa step surface is The side etching amount of ITO etching solution is 6 μm;

[0062] S5: using positive photoresist for second lithography overlay, photoresist covers Mesa step surface and etching, after using reaction coupled plasma etching, get cutting way 11, the width of cutting way 11 is 16 μm; etching time is 900 s, gas flow is 155 cfm, etching depth

[0063] S6: after removing the glue, using BOE solution to etch the remaining silicon dioxide;

[0064] S7: after re-photolithography, evaporation silver mirror, get thickness of Current expansion layer 7 and reflective layer 8; using negative photoresist for lithography, drying condition is 100 ℃ 90 s, exposure amount is 150 mj, developing condition is 116 ℃ 90 s;

[0065] S8: deposit a layer of thickness of Silicon dioxide and etching, get silicon dioxide protective layer 9;

[0066] S9: evaporation P-type pad and N-type pad to get metal electrode pad layer 10, and inject etching hole and current expansion layer connection conduction.

[0067] The performance test of LED silver mirror chip of example one, the test result is: ITO spacing is 20 μm, ITO overall area is 41340 μm 2 .

[0068] Therefore, the ITO interval of the conventional LED flip chip is generally 34μm, and the overall ITO area is about 34592μm 2 Compared with the conventional LED flip chip, the overall ITO area of the obtained LED flip chip of the present application is expanded by 6748μm 2 (about 19.5%), and the brightness ratio is improved by about 5.57%.

[0069] Embodiment two of the present application is a manufacturing method of an LED silver mirror chip, comprising the following steps:

[0070] S1: using a metal organic chemical vapor deposition method to grow a N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer of a gallium nitride base on a sapphire substrate in sequence to obtain a GaN epitaxial wafer;

[0071] S2: evaporating an ITO (indium tin oxide) conductive layer with a thickness of 300nm on the GaN epitaxial wafer, and then depositing a layer of silicon dioxide as an etching mask, wherein the thickness of the etching mask is 300nm;

[0072] S3: coating 2.3μm of positive photoresist on the etching mask, and then sequentially performing drying at 110℃ for 90s, exposure with an exposure amount of 75mj, and development at 135℃ for 90s to obtain Mesa photoetching patterns, overlaying photoetching patterns and cutting path photoetching patterns, wherein the width of the cutting path photoetching patterns is 3μm;

[0073] S4: first etching the silicon dioxide of the cutting path photoetching patterns and the Mesa photoetching patterns by using a BOE solution, and then etching the ITO conductive layer by using an ITO etching solution, and then etching out N-GaN to obtain Mesa step surfaces and overlaying, wherein the etching depth of the Mesa step surfaces is 2.3μm, and the side etching amount of the ITO etching solution is 5μm; after etching the ITO conductive layer by using the ITO etching solution;

[0074] S5: performing second photoetching overlaying by using the positive photoresist, wherein the photoresist covers the Mesa step surfaces and the overlaying, and after etching by using a reaction coupled plasma method, a cutting path is obtained, wherein the width of the cutting path is 14μm; during etching, chlorine gas is used for etching, the etching time is 900s, the gas flow is 155cfm, and the etching depth is 2.3μm;

[0075] S6: after removing the photoresist, etching the remaining silicon dioxide by using a BOE solution;

[0076] S7: after photoetching again, evaporating a silver mirror to obtain a thickness of 300nm; ​The current spreading layer and the reflecting layer are coated by using a negative photoresist, the drying condition is 100 DEG C for 90s, the exposure amount is 145mj, and the developing condition is 116 DEG C for 90s;

[0077] S8: a silicon dioxide layer with a thickness of 200nm is deposited and etched to obtain a silicon dioxide protective layer;

[0078] S9: P-type pads and N-type pads are evaporated to obtain a metal electrode pad layer, and etching holes are injected to connect and conduct with the current spreading layer.

[0079] Embodiment three of the present application is a manufacturing method of an LED silver mirror chip, comprising the following steps:

[0080] S1: a GaN epitaxial wafer is obtained by growing a N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer of gallium nitride on a sapphire substrate in sequence by using a metal organic chemical vapor deposition method;

[0081] S2: an ITO (indium tin oxide) conductive layer with a thickness of 200nm is evaporated on the GaN epitaxial wafer, and then a silicon dioxide layer with a thickness of 200nm is deposited as an etching mask;

[0082] S3: 2.5um of a positive photoresist is coated on the etching mask, and then the photoresist is subjected to drying at 110 DEG C for 90s, exposure with an exposure amount of 85mj, and developing at 135 DEG C for 90s in sequence to obtain Mesa photoetching patterns, overlaying patterns and cutting path photoetching patterns, wherein the width of the cutting path photoetching patterns is 5um;

[0083] S4: the silicon dioxide of the cutting path photoetching patterns and the Mesa photoetching patterns is etched by using a BOE solution, the ITO conductive layer is etched by using an ITO etching solution, and then N-GaN is etched to obtain Mesa step surfaces and overlaying, wherein the etching depth of the Mesa step surfaces is 200nm, and the side etching amount of the ITO etching solution is 7um;

[0084] S5: the positive photoresist is used for second photoetching overlaying, the photoresist covers the Mesa step surfaces and the overlaying, and then the cutting path is obtained after etching by using a reaction coupled plasma method, wherein the width of the cutting path is 18um; chlorine is used for etching during etching, the etching time is 900s, the gas flow is 155cfm, and the etching depth is 200nm;

[0085] S6: the remaining silicon dioxide is etched by using a BOE solution after removing the photoresist;

[0086] S7: silver mirror is evaporated after photoetching again to obtain a silver mirror layer with a thickness of 200nm; ​​​The current spreading layer and the reflecting layer are coated by using a negative photoresist, the drying condition is 100 DEG C for 90s, the exposure amount is 155mj, and the developing condition is 116 DEG C for 90s;

[0087] S8: a layer of silicon dioxide with a thickness of 1000-2000nm is deposited and etched to obtain a silicon dioxide protective layer; S8: a layer of silicon dioxide with a thickness of 1000-2000nm is deposited and etched to obtain a silicon dioxide protective layer;

[0088] S9: P-type pads and N-type pads are evaporated to obtain a metal electrode pad layer, and etching holes are injected to connect and conduct with the current spreading layer.

[0089] In summary, the manufacturing method of the LED silver mirror chip provided by the application reduces the original five (or four) etching to two by once photoetching the Mesa photoetching pattern and the cutting path photoetching pattern after evaporating ITO and silicon dioxide, then performing layer-by-layer etching, and then synchronously photoetching and evaporating the current spreading layer and the reflecting layer. The number of photoetching is reduced, the exposure deviation is reduced, the P-GaN and ITO to be etched are reduced, the area of the GaN layer and the area of ITO thereon are maximally reserved, the light emitting efficiency is increased, the brightness is improved. Reducing the number of photoetching can also reduce the multi-path processing flow, shorten the processing time, and save the cost. The silicon dioxide protective layer prevents the silver mirror from being oxidized and prevents impurities such as moisture from being oxidized and corroded.

[0090] The above description is only an embodiment of the application, and does not limit the patent scope of the application, and any equivalent transformation or direct or indirect application in the related technical field by using the content of the specification and the drawings is also included in the patent protection scope of the application.

Claims

1. A method for manufacturing an LED silver mirror chip, characterized in that, Includes the following steps: S1: An ITO conductive layer is deposited on the GaN epitaxial wafer, and then a silicon dioxide layer is deposited as an etching mask. S2: Perform photolithography on the etching mask to obtain the Mesa photolithography pattern and the dicing pattern; S3: First, use BOE solution to etch the silicon dioxide of the dicing pattern and the Mesa pattern, then use ITO etch solution to etch the ITO conductive layer, and then etch to obtain the Mesa step surface. S4: Cover the Mesa step surface with photoresist, and then etch to obtain the cutting path; S5: Use BOE solution to etch the remaining silica; S6: After photolithography, a silver mirror is deposited by vapor deposition to obtain a current spreading layer and a reflective layer; S7: Deposit a layer of silicon dioxide and etch it to obtain a silicon dioxide protective layer; S8: P-type and N-type pads are vapor-deposited to obtain a metal electrode pad layer, and etched holes are injected to connect and conduct with the current spread layer.

2. The method for manufacturing an LED silver mirror chip according to claim 1, characterized in that, The thickness of the ITO conductive layer is 3. The method for manufacturing an LED silver mirror chip according to claim 1, characterized in that, The thickness of the etching mask is 4. The method for manufacturing an LED silver mirror chip according to claim 1, characterized in that, The specific steps of S2 are as follows: positive photoresist is coated on the etching mask, and then dried, exposed and developed in sequence to obtain the Mesa lithographic pattern and the dicing lithographic pattern.

5. The method for manufacturing an LED silver mirror chip according to claim 4, characterized in that, The coating thickness of the positive photoresist is 2.3–2.5 μm, and the exposure amount is 75–85 mJ.

6. The method for manufacturing an LED silver mirror chip according to claim 1, characterized in that, The width of the lithographic pattern of the cutting track is 3 to 5 μm.

7. The method for manufacturing an LED silver mirror chip according to claim 1, characterized in that, The lateral etching depth of the ITO etching solution in S3 is 5–7 μm.

8. The method for manufacturing an LED silver mirror chip according to claim 1, characterized in that, The width of the cutting channel is 14–18 μm.

9. The method for manufacturing an LED silver mirror chip according to claim 1, characterized in that, The S6 photolithography process uses negative photoresist coating with an exposure dose of 145–155 mJ.

10. The method for manufacturing an LED silver mirror chip according to claim 1, characterized in that, The thickness of both the current spreading layer and the reflective layer is...

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