Delay circuit, layout and method for achieving different delays

Abstract

The embodiment of the present disclosure provides a delay circuit, a layout and a method for realizing different delays. The delay circuit comprises: a basic delay circuit connected between a working power supply and a ground terminal; a resistance adjusting circuit comprising at least one set of resistance adjusting units, each set of resistance adjusting units comprising a first transistor and a first switch, the first switch being connected between the first terminal of the first transistor and the second terminal; and a capacitance adjusting circuit comprising at least one set of capacitance adjusting units, each set of capacitance adjusting units comprising a second transistor, a second switch and a third switch, the second switch being connected between the second gate and the third terminal, and the third switch being connected between the second gate and the first output terminal; when the first switch is turned off, the resistance adjusting unit forms an equivalent resistance; and when the second switch is turned off and the third switch is turned on, the capacitance adjusting unit forms an equivalent capacitance. The delay circuit provided by the embodiment of the present disclosure can meet different delay requirements.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular to a delay circuit, a layout and a method for implementing different delays. BACKGROUND

[0002] Storage systems are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are currently a number of different types of storage systems, including, for example, random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low power double data rate memory (LPDDR), phase change memory (PCM), and flash memory.

[0003] During the operation of a storage system, a number of signals are transmitted, such as data signals, clock signals, or command / address signals, etc. Delay circuits are usually designed in the transmission paths of these signals, and the delays of the delay circuits on different transmission paths or during different operations are different.

[0004] Therefore, there is a need to design a delay circuit that can meet different delay requirements. SUMMARY

[0005] Embodiments of the present disclosure provide a delay circuit, a layout and a method for implementing different delays, which can at least achieve the effect of quickly modifying the layout to meet different delay requirements.

[0006] According to some embodiments of the present disclosure, the present disclosure provides, in one aspect, a delay circuit, a basic delay circuit connected between a working power supply and a ground terminal, having a first input terminal for receiving a first signal and a first output terminal for outputting a second signal having a preset delay compared with the first signal, a resistance adjustment circuit connected between the basic delay circuit and the working power supply and / or connected between the basic delay circuit and the ground terminal, including at least one set of resistance adjustment units, each set of the resistance adjustment units including a first transistor having a first gate receiving a preset voltage, a first terminal and a second terminal, and a first switch connected between the first terminal and the second terminal, and a capacitance adjustment circuit connected between the first output terminal and the working power supply and / or connected between the first output terminal and the ground terminal, including at least one set of capacitance adjustment units, each set of the capacitance adjustment units including a second transistor having a second gate, a third terminal, a fourth terminal and a substrate terminal, wherein the third terminal, the fourth terminal and the substrate terminal are directly connected, a second switch connected between the second gate and the third terminal, and a third switch connected between the second gate and the first output terminal, wherein the first switch is turned off, and the corresponding resistance adjustment unit forms an equivalent resistance connected with the basic delay circuit, and the second switch is turned off and the third switch is turned on, and the corresponding capacitance adjustment unit forms an equivalent capacitance connected with the basic delay circuit.

[0007] In some embodiments, the resistance adjustment circuit includes a first resistance adjustment circuit connected between the basic delay circuit and the working power supply, and the first resistance adjustment circuit includes at least two sets of the resistance adjustment units connected in series.

[0008] In some embodiments, the basic delay circuit includes a first PMOS transistor having a gate receiving the first signal, a source connected with the working power supply via the first resistance adjustment circuit, and a drain connected with the first output terminal.

[0009] In some embodiments, in the first resistance adjustment circuit, the first transistor is a second PMOS transistor.

[0010] In some embodiments, the resistance adjustment circuit includes a second resistance adjustment circuit connected between the basic delay circuit and the ground terminal, and the second resistance adjustment circuit includes at least two sets of the resistance adjustment units connected in series.

[0011] In some embodiments, the basic delay circuit comprises a first NMOS transistor, a gate of the first NMOS transistor receives the first signal, a drain of the first NMOS transistor is connected to the first output terminal, and a source of the first NMOS transistor is connected to the ground terminal via the second resistance adjusting circuit.

[0012] In some embodiments, in the second resistance adjusting circuit, the first transistor is a second NMOS transistor.

[0013] In some embodiments, the capacitance adjusting circuit comprises a first capacitance adjusting circuit connected between the first output terminal and the working power supply, and the first capacitance adjusting circuit comprises at least two groups of the capacitance adjusting units connected in parallel.

[0014] In some embodiments, in the first capacitance adjusting circuit, the second transistor is a third PMOS transistor, and the third terminal, the fourth terminal and the substrate terminal are directly connected to the working power supply.

[0015] In some embodiments, the capacitance adjusting circuit comprises a second capacitance adjusting circuit connected between the first output terminal and the ground terminal, and the second capacitance adjusting circuit comprises at least two groups of the capacitance adjusting units connected in parallel.

[0016] In some embodiments, in the second capacitance adjusting circuit, the second transistor is a third NMOS transistor, and the third terminal, the fourth terminal and the substrate terminal are directly connected to the ground terminal.

[0017] In some embodiments, the delay circuit comprises a plurality of cascaded basic delay circuits, and each of the basic delay circuits is connected to a corresponding resistance adjusting circuit and capacitance adjusting circuit.

[0018] In some embodiments, the basic delay circuit is an inverter, and the delay circuit comprises an even number of cascaded basic delay circuits.

[0019] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a layout corresponding to the delay circuit, comprising: a basic delay layout for defining the basic delay circuit; a resistance adjustment layout for defining the resistance adjustment circuit, comprising at least one set of resistance layout, each set of the resistance layout being used for defining a set of the resistance adjustment units, each set of the resistance layout comprising a first switch region, the first switch region being used for defining the first switch, the first switch region having a conductive layer to turn on the first switch, and the first switch region not having the conductive layer to turn off the first switch; and a capacitance adjustment layout for defining the capacitance adjustment circuit, comprising at least one set of capacitance layout, each set of the capacitance layout being used for defining a set of the capacitance adjustment units, each set of the capacitance layout comprising a second switch region and a third switch region, the second switch region being used for defining the second switch, the third switch region being used for defining the third switch, the second switch region having a conductive layer to turn on the second switch, and the second switch region not having the conductive layer to turn off the second switch, the third switch region having the conductive layer to turn on the third switch, and the third switch region not having the conductive layer to turn off the third switch.

[0020] In some embodiments, the resistance adjustment layout and the capacitance adjustment layout are located on opposite sides of the basic delay layout.

[0021] In some embodiments, the first switch region, the second switch region, and the third switch region have the same area.

[0022] In some embodiments, the capacitance adjustment layout further comprises: a capacitance transistor region for defining the second transistor, the capacitance transistor region comprising a second gate region, a third terminal region, a fourth terminal region, and a substrate terminal region for defining the second gate, the third terminal, the fourth terminal, and the substrate terminal, respectively; a first connection region, a second connection region, a third connection region, and a fourth connection region for defining a first conductive column, a second conductive column, a third conductive column, and a fourth conductive column electrically connected to the second gate, the third terminal, the fourth terminal, and the substrate terminal, respectively; wherein the second switch region and the first connection region have an overlapping region, and the second switch region and the second connection region have an overlapping region; and the third switch region and the first connection region have an overlapping region.

[0023] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a method for realizing different delays, comprising: providing the layout provided by the above embodiments; and based on a preset delay requirement, revising the layout by selecting whether to layout a conductive layer in the first switch region of each set of the resistance layout, and selecting whether to layout a conductive layer in one of the second switch region or the third switch region of each set of the capacitance layout.

[0024] In some embodiments, the layout is provided by providing a first basic layout for being used as the first switch region with the conductive layer, the second switch region with the conductive layer, or the third switch region with the conductive layer; and providing a second basic layout for being used as the first switch region without the conductive layer, the second switch region without the conductive layer, or the third switch region without the conductive layer; and the selection of whether to layout the conductive layer for the first switch region in each of the resistance layout is performed by calling one of the first basic layout or the second basic layout; and the selection of whether to layout the conductive layer for one of the second switch region or the third switch region in each of the capacitance layout is performed by calling one of the first basic layout or the second basic layout.

[0025] In some embodiments, each of the basic delay layout, the resistance adjustment layout, and the capacitance adjustment layout constitutes a standard delay layout; the layout is provided by providing N standard delay layouts, and different standard delay layouts correspond to delay circuits with different delays; and the modification of the layout is performed by selecting M standard delay layouts from the N standard delay layouts based on the preset delay requirement, where M is less than or equal to N.

[0026] The technical solution of the delay circuit provided by the embodiments of the present disclosure has at least the following advantages:

[0027] In the technical solution of the delay circuit provided by the embodiments of the present disclosure, the basic delay circuit, the resistance adjustment circuit connected between the basic delay circuit and the working power supply and / or the ground terminal, the capacitance adjustment circuit connected between the basic delay circuit and the working power supply and / or the ground terminal, and the like are included. The resistance adjustment circuit includes a first transistor and a first switch connected in parallel between the source and the drain of the first transistor. If the first switch is open, the first transistor can be used as a resistance for adjusting the delay in the delay circuit. If the first switch is closed, the first transistor does not participate in the adjustment of the delay in the delay circuit. The capacitance adjustment circuit includes a second transistor, a second switch connected between the gate and the source or the drain of the second transistor, and a third switch connected between the gate of the second transistor and the first output terminal of the basic delay circuit. If the second switch is closed and the third switch is open, the second transistor does not serve as a capacitance for adjusting the delay in the delay circuit. If the second switch is open and the third switch is closed, the second transistor serves as a capacitance for adjusting the delay in the delay circuit. In this way, in the embodiments of the present disclosure, by adjusting the closing and opening of the first switch, the second switch, and / or the third switch, the RC parameters participating in the delay adjustment in the delay circuit can be adjusted, so that the same delay circuit can meet different delay requirements. BRIEF DESCRIPTION OF DRAWINGS

[0028] One or more embodiments are illustrated by way of example in the drawings in which like reference numerals indicate like elements, and in which: the drawings are not necessarily to scale as the emphasis instead is placed upon illustrating the principles of the embodiments; for the purpose of clarity, not every component component of an embodiment is labeled in the figures, but a person of ordinary skill in the art will appreciate that the illustrated embodiments include all components of the exclusive property of the present disclosure, and that not all components of the embodiments are required to practice the embodiments; and, for the purpose of clarity, not every component of the figures is required to practice the embodiments.

[0029] Figures 1 to 5 Different circuit structure diagrams of the delay circuit provided by the embodiments of the present disclosure;

[0030] Figure 6 A schematic diagram of a layout;

[0031] Figure 7 A schematic diagram of a layout; Figure 6 An enlarged structure schematic diagram of the capacitor adjusting the capacitor transistor region in the layout shown in the layout;

[0032] Figure 8 An enlarged structure schematic diagram of the resistance adjusting the resistance transistor region in the layout shown in the layout; Figure 6 An enlarged structure schematic diagram of the resistance adjusting the resistance transistor region in the layout shown in the layout;

[0033] Figure 9 A schematic diagram of a layout including two different basic layout structures;

[0034] Figures 10 to 17 Four different schematic diagrams of the delay circuit and the corresponding layout thereof. DETAILED DESCRIPTION

[0035] As known from the background art, there is a need to design a delay circuit that can meet different delay requirements. A delay circuit can be designed to add a capacitor on the basis of an inverter, so that the adjustable delay is large. If the size of the delay needs to be changed, the number of capacitors needs to be increased or decreased to achieve this, and the layout corresponding to the delay circuit also needs to be adjusted relatively greatly.

[0036] The embodiments of the present disclosure provide a delay circuit that can meet different delay requirements using the same delay circuit. The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are presented in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0037] Figures 1 to 5The delay circuit provided by the embodiments of the present disclosure has a plurality of different circuit structure diagrams.

[0038] Reference Figures 1 to 5 The delay circuit comprises a basic delay circuit 101 connected between a working power supply VDD and a ground terminal, having a first input end IN1 and a first output end OUT1, the first input end being configured to receive a first signal, and the first output end being configured to output a second signal, the second signal having a preset delay compared with the first signal; a resistance adjustment circuit 102 connected between the basic delay circuit 101 and the working power supply VDD and / or connected between the basic delay circuit 101 and the ground terminal, comprising at least one set of resistance adjustment units 12, each set of resistance adjustment units 12 comprising a first transistor and a first switch S1, the first transistor having a first gate, a first end and a second end, the first gate receiving a preset voltage, and the first switch S1 being connected between the first end and the second end; and a capacitance adjustment circuit 103 connected between the first output end and the working power supply VDD and / or connected between the first output end and the ground terminal, comprising at least one set of capacitance adjustment units 13, each set of capacitance adjustment units 13 comprising a second transistor, a second switch S2 and a third switch S3, the second transistor having a second gate, a third end, a fourth end and a substrate end, wherein the third end, the fourth end and the substrate end are directly connected, the second switch S2 being connected between the second gate and the third end, and the third switch S3 being connected between the second gate and the first output end; wherein when the first switch S1 is open, the corresponding resistance adjustment unit 12 forms an equivalent resistance connected with the basic delay circuit 101, and when the second switch S2 is open and the third switch S3 is closed, the corresponding capacitance adjustment unit 13 forms an equivalent capacitance connected with the basic delay circuit 101.

[0039] The first transistor serves as an adjustable resistance selectively connected to the delay circuit, if the first switch S1 is closed, the first transistor connected with the first switch S1 is not connected to the delay circuit and does not serve as a resistance, and if the first switch S1 is open, the first transistor connected with the first switch S1 is connected to the delay circuit and serves as a resistance; the second transistor serves as an adjustable capacitance selectively connected to the delay circuit, if the second switch S2 is closed and the third switch S3 is open, the second transistor connected with the second switch S2 is not connected to the delay circuit and does not serve as a capacitance, and if the second switch S2 is open and the third switch S3 is closed, the second transistor connected with the second switch S2 is connected to the delay circuit and serves as a capacitance. For the delay circuit, the equivalent resistance and the equivalent capacitance affect the delay of the delay circuit, thus, by adjusting the closing and opening of the first switch S1, the second switch S2 or the third switch S3, the size of the equivalent resistance and the equivalent capacitance of the delay circuit can be changed, so that the delay of the delay circuit can be changed.

[0040] The resistance adjusting circuit 102 can comprise a first resistance adjusting circuit 112 connected between the basic delay circuit 101 and the working power supply VDD, and the first resistance adjusting circuit 112 comprises at least two groups of series-connected resistance adjusting units 12. For any resistance adjusting unit 12, if the first switch S1 is closed, the resistance adjusting unit 12 does not play a role of resistance, and if the first switch S1 is disconnected, the resistance adjusting unit 12 plays a role of resistance. The first resistance adjusting circuit 112 serves as a pull-up resistance in the basic delay circuit 101, and the resistance value of the pull-up resistance is adjustable.

[0041] The more the number of the resistance adjusting units 12 is, the more the adjustable gears of the equivalent resistance between the basic delay circuit 101 and the working power supply VDD are, i.e. the more the adjustable gears of the resistance value of the pull-up resistance are, and the more the gears in which the first resistance adjusting circuit 112 can participate in the delay adjustment of the basic delay circuit 101 are. Therefore, the number of the resistance adjusting units 12 in the first resistance adjusting circuit 112 can be reasonably set according to requirements.

[0042] Reference Figure 3 The basic delay circuit 101 can comprise a first PMOS transistor MP1, the gate of the first PMOS transistor MP1 receives the first signal, the source is connected with the working power supply VDD via the first resistance adjusting circuit 112, and the drain is connected with the first output end. The gate of the first PMOS transistor MP1 is connected with the first input end.

[0043] The first resistance adjusting circuit 112 constitutes a pull-up resistance connected between the source of the first PMOS transistor MP1 and the working power supply VDD. The greater the resistance value of the pull-up resistance is, the smaller the current between the working power supply VDD and the source of the first PMOS transistor MP1 is, the slower the voltage of the source of the first PMOS transistor MP1 is pulled up, the longer the time required for the first PMOS transistor MP1 to be turned on, and the longer the delay required for the first signal to be transmitted from the first input end to the first output end, i.e. the longer the delay of the delay circuit. The smaller the resistance value of the pull-up resistance is, the greater the current between the working power supply VDD and the source of the first PMOS transistor MP1 is, the faster the voltage of the source of the first PMOS transistor MP1 is pulled up, the shorter the time required for the first PMOS transistor MP1 to be turned on, and the shorter the delay required for the first signal to be transmitted from the first input end to the first output end, i.e. the shorter the delay of the delay circuit.

[0044] In the first resistance adjusting circuit 112, the first transistor can be a second PMOS transistor MP2, wherein one of the source and the drain of the second PMOS transistor MP2 is the first terminal, and the other of the source and the drain of the second PMOS transistor MP2 is the second terminal. The first switch S1 has one end connected to the source of the second PMOS transistor MP2 and the other end connected to the drain of the second PMOS transistor MP2. The preset voltage received by the second PMOS transistor MP2 is denoted as VSS. Generally, VSS is a low voltage, and can also be the voltage of a ground terminal.

[0045] It can be understood that, in some embodiments, the first resistance adjusting circuit 112 can also include only one resistance adjusting unit 12 composed of the first transistor.

[0046] The resistance adjusting circuit 102 can include a second resistance adjusting circuit 122 connected between the basic delay circuit 101 and a ground terminal, and the second resistance adjusting circuit 122 includes at least two groups of resistance adjusting units 12 connected in series. For any resistance adjusting unit 12, if the first switch S1 is closed, the resistance adjusting unit 12 does not play a role of resistance, and if the first switch S1 is open, the resistance adjusting unit 12 plays a role of resistance. The second resistance adjusting circuit 122 serves as a pull-down resistance in the basic delay circuit 101, and the resistance value of the pull-down resistance is adjustable.

[0047] The more the number of resistance adjusting units 12 in the second resistance adjusting circuit 122, the more the adjustable gears of the equivalent resistance between the basic delay circuit 101 and the ground terminal, i.e., the more the adjustable gears of the resistance value of the pull-down resistance, and the more the gears of the second resistance adjusting circuit 122 that can participate in the delay adjustment of the basic delay circuit 101. Therefore, the number of resistance adjusting units 12 in the second resistance adjusting circuit 122 can be reasonably set according to requirements. It should be noted that the second resistance adjusting circuit 122 can also include only one resistance adjusting unit 12 composed of the first transistor.

[0048] It can be understood that, although Figures 1 to 5 In the first resistance adjusting circuit 112 and the second resistance adjusting circuit 122, both the first resistance adjusting circuit 112 and the second resistance adjusting circuit 122 are shown, in fact, the delay circuit can also have only one of the first resistance adjusting circuit 112 and the second resistance adjusting circuit 122.

[0049] For the convenience of illustration and description, Figure 2 and Figure 5 In the first resistance adjusting circuit 112 and the second resistance adjusting circuit 122, R3 and R4 respectively denote the equivalent resistance of two resistance adjusting units 12 in the first resistance adjusting circuit 112, and R1 and R2 respectively denote the equivalent resistance of two resistance adjusting units 12 in the second resistance adjusting circuit 122.

[0050] The basic delay circuit 101 comprises a first NMOS transistor MN1, a gate of the first NMOS transistor MN1 receives the first signal, a drain of the first NMOS transistor MN1 is connected to the first output terminal, and a source of the first NMOS transistor MN1 is connected to a ground terminal via the second resistance adjusting circuit 122.

[0051] The second resistance adjusting circuit 122 constitutes a pull-down resistance connected between the source of the first NMOS transistor MN1 and the ground terminal. The greater the resistance value of the pull-down resistance, the smaller the current between the source of the first NMOS transistor MN1 and the ground terminal, the slower the voltage of the source of the first NMOS transistor MN1 is pulled down, the longer the time required for the first NMOS transistor MN1 to be turned on, and the longer the delay required for the first signal to be transmitted from the first input terminal to the first output terminal, i.e., the longer the delay of the delay circuit. The smaller the resistance value of the pull-down resistance, the greater the current between the source of the first NMOS transistor MN1 and the ground terminal, the faster the voltage of the source of the first NMOS transistor MN1 is pulled down, the shorter the time required for the first NMOS transistor MN1 to be turned on, and the shorter the delay required for the first signal to be transmitted from the first input terminal to the first output terminal, i.e., the shorter the delay of the delay circuit.

[0052] In the second resistance adjusting circuit 122, the first transistor can be a second NMOS transistor MN2, wherein the first end can be one of the source or the drain of the second NMOS transistor MN2, and the second end can be the other of the source or the drain of the second NMOS transistor MN2. The first switch S1 has one end connected to the source of the second NMOS transistor MN2 and the other end connected to the drain of the second NMOS transistor MN2. The preset voltage received by the second NMOS transistor MN2 is denoted as VDL Y. Generally, VDL Y is a high level.

[0053] The capacitance adjusting circuit 103 can comprise a first capacitance adjusting circuit 113 connected between the first output terminal and a working power supply VDD, and the first capacitance adjusting circuit 113 comprises at least two groups of parallel capacitance adjusting units 13. For any capacitance adjusting unit 13 in the first capacitance adjusting circuit 113, if the second switch S2 is closed and the third switch S3 is open, the capacitance adjusting unit 13 does not play a capacitance role; if the second switch S2 is open and the third switch S3 is closed, the capacitance adjusting unit 13 plays a capacitance role. The first capacitance adjusting circuit 113 serves as a pull-up capacitance in the basic delay circuit 101, and the capacitance value of the pull-up capacitance is adjustable.

[0054] For the first capacitance adjustment circuit 113, the more the number of the capacitance adjustment units 13, the more the equivalent capacitance adjustment levels between the basic delay circuit 101 and the working power supply VDD, that is, the more the capacitance value adjustment levels of the pull-up capacitance, and the more the delay adjustment levels of the basic delay circuit 101 by the first capacitance adjustment circuit 113. Therefore, the number of the capacitance adjustment units 13 in the first capacitance adjustment circuit 113 can be reasonably set according to the requirements.

[0055] Specifically, for the first capacitance adjustment circuit 113, the more the number of the capacitances in the capacitance adjustment unit 13, the greater the capacitance value of the pull-up capacitance.

[0056] In the first capacitance adjustment circuit 113, the second transistor can be a third PMOS tube MP3, and the third end, the fourth end and the substrate end are directly connected to the working power supply VDD. The third end can be one of the source or the drain, and the fourth end can be the other one of the source or the drain; one end of the second switch S2 is connected to the third end, and the other end is connected to the gate of the third PMOS tube MP3; one end of the third switch S3 is connected to the first output end, and the other end is connected to the gate of the third PMOS tube MP3. Wherein, the third end is one of the source or the drain of the third PMOS tube MP3, and the fourth end is the other one of the source or the drain of the third PMOS tube MP3.

[0057] It can be understood that in some embodiments, the first capacitance adjustment circuit 113 can also include only one capacitance adjustment unit 13, which is composed of the second transistor.

[0058] For the third PMOS tube MP3, when the second switch S2 is closed and the third switch S3 is opened, the third PMOS tube MP3 is not connected to the basic delay circuit 101, at this time, because the second switch S2 is closed, the gate of the third PMOS tube MP3 is prevented from floating, so that the gate of the third PMOS tube MP3 is connected to the working power supply VDD, thereby avoiding the adverse effects of the gate threshold on the delay circuit, for example, avoiding the disturbance of the third PMOS tube MP3 to the working power supply VDD. When the second switch S2 is opened and the third switch S3 is closed, the third PMOS tube MP3 is connected to the basic delay circuit 101, and the third PMOS tube MP3 constitutes a capacitance.

[0059] The capacitance adjusting circuit 103 can comprise a second capacitance adjusting circuit 123 connected between the first output end and the ground end, and the second capacitance adjusting circuit 123 comprises at least two groups of parallel-connected capacitance adjusting units 13. For any capacitance adjusting unit 13 in the second capacitance adjusting circuit 123, if the second switch S2 is closed and the third switch S3 is open, the capacitance adjusting unit 13 does not play a capacitance role; if the second switch S2 is open and the third switch S3 is closed, the capacitance adjusting unit 13 plays a capacitance role. The second capacitance adjusting circuit 123 serves as a pull-down capacitance in the basic delay circuit 101, and the capacitance value of the pull-down capacitance is adjustable.

[0060] For the second capacitance adjusting circuit 123, the more the number of the capacitance adjusting units 13 is, the more the adjustable levels of the equivalent capacitance between the basic delay circuit 101 and the ground end are, that is, the more the adjustable levels of the capacitance value of the pull-down capacitance are, and the more the adjustable levels of the delay of the basic delay circuit 101 by the second capacitance adjusting circuit 123 are. Therefore, the number of the capacitance adjusting units 13 in the second capacitance adjusting circuit 123 can be reasonably set according to requirements.

[0061] Specifically, for the second capacitance adjusting circuit 123, the more the number of the capacitance adjusting units 13 is, the greater the capacitance value of the pull-down capacitance is.

[0062] In the second capacitance adjusting circuit 123, the second transistor can be a third NMOS transistor MN3, and the third end, the fourth end and the substrate end are directly connected to the ground end. The third end can be one of the source or the drain of the third NMOS transistor MN3, and the fourth end can be the other of the source or the drain of the third NMOS transistor MN3; one end of the second switch S2 is connected to the third end, and the other end is connected to the gate of the third NMOS transistor MN3; one end of the third switch S3 is connected to the first output end, and the other end is connected to the gate of the third NMOS transistor MN3.

[0063] For the third NMOS transistor MN3, when the second switch S2 is closed and the third switch S3 is open, the third NMOS transistor MN3 is not connected to the basic delay circuit 101, and at this time, since the second switch S2 is closed, the gate of the third NMOS transistor MN3 is prevented from floating, so that the gate of the third NMOS transistor MN3 is connected to the ground end, thereby avoiding the adverse effects of the gate threshold on the delay circuit. When the second switch S2 is open and the third switch S3 is closed, the third NMOS transistor MN3 is connected to the basic delay circuit 101, and the third NMOS transistor MN3 constitutes a capacitance.

[0064] For the convenience of illustration and description, Figure 2 and Figure 5In the figure, C4, C5 and C6 respectively denote the equivalent capacitances of the three capacitive adjustment units 13 in the first capacitive adjustment circuit 113, and C1, C2 and C3 respectively denote the equivalent capacitances of the three capacitive adjustment units 13 in the second capacitive adjustment circuit 123.

[0065] Without considering the resistance adjustment voltage 102 and the capacitive adjustment circuit 103, the basic delay circuit 101 itself has a basic delay for the transmission of the first signal, and according to the adjustment of the closing and opening of the switches in the resistance adjustment circuit 102 and the capacitive adjustment circuit 103, the delay of the first signal from the first input end to the first output end can be further adjusted.

[0066] The delay circuit can include a plurality of cascaded basic delay circuits 101, and each basic delay circuit 101 is connected with a corresponding resistance adjustment circuit 102 and capacitive adjustment circuit 103. In this way, not only the actual delay of a single basic delay circuit 101 is adjustable due to the influence of the resistance adjustment circuit 102 and the capacitive adjustment circuit 103, but also the actual delays of different basic delay circuits 101 can be different, thereby making the adjustable range of the total delay of the delay circuit more flexible. Figure 3 and Figure 5 In the figure, IN1 denotes the first input end of the basic delay circuit 101 of the first stage, OUT1 denotes the first output end of the basic delay circuit of the first stage, IN2 denotes the first input end of the basic delay circuit 101 of the second stage, and OUT2 denotes the first output end of the basic delay circuit of the second stage.

[0067] In some embodiments, the basic delay circuit 101 can be an inverter, and the delay circuit includes an even number of cascaded basic delay circuits 101. In this way, it is ensured that the phase of the signal output by the output end of the last-stage basic delay circuit 101 is the same as that of the first signal.

[0068] The delay circuit provided by the above embodiments adopts a similar circuit structure, and by controlling the closing and opening of the first switch S1, the second switch S2 and the third switch S3, the requirement of different delays can be met.

[0069] Correspondingly, the disclosure also provides a layout, which can be the layout of the delay circuit provided by the above embodiments. The layout will be described in detail below, and it should be noted that the description of the above embodiments is also applicable to the embodiments of the layout, and to avoid repetition, the content mentioned in the above embodiments will not be described in detail below. In addition, the description of the layout and the delay circuit in the following embodiments is also applicable to the above embodiments of the delay circuit.

[0070] Figure 6 It is a schematic diagram of the layout.

[0071] In combination with reference to Figure 1 and Figure 6 The layout 300 of the delay circuit includes: a basic delay layout 201 for defining the basic delay circuit 101; a resistance adjustment layout 202 for defining the resistance adjustment circuit 102, including at least one set of resistance layout 32, each set of resistance layout 32 being used to define a set of resistance adjustment units 12, each set of resistance layout 32 including a first switch region A1 for defining a first switch S1, the first switch region A1 having a conductive layer so that the first switch S1 is closed, and the first switch region A1 not having a conductive layer so that the first switch S1 is opened; and a capacitance adjustment layout 203 for defining the capacitance adjustment circuit 103, including at least one set of capacitance layout 33, each set of capacitance layout 33 being used to define a set of capacitance adjustment units 13, each set of capacitance layout 33 including a second switch region A2 for defining a second switch S2 and a third switch region A3 for defining a third switch S3, the second switch region A2 having a conductive layer so that the second switch S2 is closed, and the second switch region A2 not having a conductive layer so that the second switch S2 is opened, the third switch region A3 having a conductive layer so that the third switch S3 is closed, and the third switch region A3 not having a conductive layer so that the third switch S3 is opened.

[0072] In some examples, the resistance adjustment layout 202 and the capacitance adjustment layout 203 can be located on opposite sides of the basic delay layout 201. In some examples, the resistance adjustment layout 202 and the capacitance adjustment layout 203 can also be located on the same side of the basic delay layout 201.

[0073] In addition, the second switch region A2 can have the same area as the third switch region A3, so that the area of the conductive layer required for the second switch S2 defined by the second switch region A2 to be closed is the same as the area of the conductive layer required for the third switch S3 defined by the third switch region A3 to be closed, and thus the same mask pattern can be used to form the conductive layers corresponding to the second switch region A2 and the third switch region A3, which is beneficial for reducing the number of mask patterns and reducing the process cost. Moreover, when the second switch S2 is switched between the closed and open states, and when the third switch S3 is switched between the closed and open states, the modification of the layout only affects the layer of the mask of the conductive layer on which the second switch S2 and the third switch S3 are located, and does not affect other layers, causing minimal changes, greatly reducing the process cost and the labor cost of drawing the layout.

[0074] Similarly, the area of the first switch region A1 can also be the same as the area of the second switch region A2, and can also be the same as the area of the third switch region A3. Thus, it is beneficial to further reduce the number of mask images and further reduce the process cost. Moreover, when the first switch S1 is switched between the closed and open states, the modification of the layout only affects the mask of the conductive layer where the first switch S1 is located, and does not affect other layers, causing the least change, greatly reducing the process cost and the labor cost of drawing the layout.

[0075] Figure 7 The enlarged structure diagram of the capacitor adjustment layout 203 in the capacitor transistor region 213 is shown in FIG. 13. Figure 7 The capacitor adjustment layout 203 can further include: a capacitor transistor region 213 for defining a second transistor, the capacitor transistor region 213 including a second gate region, a third terminal region, a fourth terminal region, and a substrate terminal region for defining a second gate, a third terminal, a fourth terminal, and a substrate terminal, respectively; a first connection region V1, a second connection region V2, a third connection region, and a fourth connection region for defining a first conductive column, a second conductive column, a third conductive column, and a fourth conductive column electrically connected to the second gate, the third terminal, the fourth terminal, and the substrate terminal, respectively; wherein the second switch region A2 and the first connection region V1 have an overlapping region, and the second connection region V2 has an overlapping region; the third switch region A3 and the first connection region V1 have an overlapping region.

[0076] It should be noted that, for the convenience of illustration and description, Figure 7 only the first connection region V1, the second connection region V2, the second switch region A2, and the third switch region A3 are shown in FIG. 13, the first connection region V1 is represented by a grid filling, and the second connection region V2 is represented by a grid filling.

[0077] Figure 8 The enlarged structure diagram of the resistance adjustment layout 202 in the resistance transistor region 212 is shown in FIG. 14. Figure 8 The resistance adjustment layout 202 can further include: a resistance transistor region 212 for defining a first transistor, the resistance transistor region 212 including a first gate region, a first terminal region, and a second terminal region for defining a first gate, a first terminal, and a second terminal, respectively, a fifth connection region, a sixth connection region V6, and a seventh connection region V7 for defining a fifth conductive column, a sixth conductive column, and a seventh conductive column connected to the first gate, the first terminal, and the second terminal, respectively; wherein the first switch region A1 and the sixth connection region V6 have an overlapping region, and the seventh connection region V7 has an overlapping region.

[0078] It should be noted that, for the convenience of illustration and description, Figure 8 only the sixth connection region V6, the seventh connection region V7, and the first switch region A1 are shown in FIG. 14, and the sixth connection region V6 and the seventh connection region V7 are both represented by a grid filling.

[0079] Figure 9 The layout includes two different basic layout structures, wherein the layout can further include: a first basic layout 401 used as a first switch region A1 with a conductive layer, a second switch region A2 with a conductive layer, or a third switch region A3 with a conductive layer; a second basic layout 402 used as a first switch region A1 without a conductive layer, a second switch region A2 without a conductive layer, or a third switch region A3 without a conductive layer.

[0080] In the delay circuit, when the first switch S1 is closed, the first basic layout 401 is used in the layout, and when the first switch S1 is open, the second basic layout 402 is used in the layout; when the second switch S2 is closed, the first basic layout 401 is used in the layout, and when the second switch S2 is open, the second basic layout 402 is used in the layout; when the third switch S3 is closed, the first basic layout 401 is used in the layout, and when the third switch S3 is open, the second basic layout 402 is used in the layout.

[0081] In this way, for whether the resistance adjustment unit 12 is connected to the basic delay circuit 101 as a resistance, only the first switch region A1 needs to be selected to use the first basic layout 401 or the second basic layout 402 in the layout design. For whether the capacitance adjustment unit 13 is connected to the basic delay circuit 101 as a capacitance, only the second switch region A2 needs to be selected to use the first basic layout 401 or the second basic layout 402, and the third switch region A3 needs to be selected to use the first basic layout 401 or the second basic layout 402 in the layout design.

[0082] In addition, in the manufacturing process corresponding to the layout, the conductive layer in the first basic layout 401 can be in the same layer as the first metal layer, that is, it can be manufactured in the same process step as the first metal layer. The first metal layer is usually referred to as M1 layer.

[0083] Figures 10 to 17 The delay circuit and its corresponding layout have four different schematic diagrams. Taking a two-stage delay circuit as an example, the first-stage delay circuit is denoted as L1 in the layout, and the second-stage delay circuit is denoted as L2, wherein each stage of the delay circuit includes a basic delay circuit 101 and corresponding resistance adjustment circuit 102 and capacitance adjustment circuit 103.

[0084] Reference Figure 10 and Figure 11For the first stage delay circuit: the first switch S1 corresponding to R4 is closed, and the first basic layout 401 is used accordingly; the first switches S1 corresponding to R1, R2 and R3 are all disconnected, and the second basic layout 402 is used accordingly; the second switches S2 corresponding to C1, C3, C4 and C6 are all disconnected, and the second basic layout 402 is used accordingly; the third switches S3 corresponding to C1, C3, C4 and C6 are all closed, and the first basic layout 401 is used accordingly; the second switches S2 corresponding to C2 and C5 are all closed, and the first basic layout 401 is used accordingly; the third switches S3 corresponding to C2 and C5 are all disconnected, and the second basic layout 402 is used accordingly. For the second stage delay circuit, the first switch area A1, the second switch area A2 and the third switch area A3 can have the same layout as those of the first stage delay circuit. Thus, the actual delay of the first stage delay circuit and the actual delay of the second stage delay circuit can be the same.

[0085] With reference to Figure 12 and Figure 13 For the first stage delay circuit: the first switches S1 corresponding to R1, R2, R3 and R4 are all disconnected, and the second basic layout 402 is used accordingly; the second switches S2 corresponding to C4, C6, C1 and C2 are all disconnected, and the second basic layout 402 is used accordingly; the third switches S3 corresponding to C4, C6, C1 and C2 are all closed, and the first basic layout 401 is used accordingly; the second switches S2 corresponding to C3 and C5 are all closed, and the first basic layout 401 is used accordingly; the third switches S3 corresponding to C3 and C5 are all disconnected, and the second basic layout 402 is used accordingly. For the second stage delay circuit 101: the first switches S1 corresponding to R1, R2, R3 and R4 are all disconnected, and the second basic layout 402 is used accordingly; the second switches S2 corresponding to C4 and C6 are all disconnected, and the second basic layout 402 is used accordingly; the third switches S3 corresponding to C4 and C6 are all closed, and the first basic layout 401 is used accordingly; the second switches S2 corresponding to C1, C2, C3 and C5 are all closed, and the first basic layout 401 is used accordingly; the third switches S3 corresponding to C1, C2, C3 and C5 are all disconnected, and the second basic layout 402 is used accordingly. That is, the actual delay of the first stage delay circuit and the actual delay of the second stage delay circuit can be different.

[0086] With reference to Figure 14 and Figure 15For the first stage of the delay circuit: the first switches S1 corresponding to R1 and R2 are both open, and the second basic layout 402 is used accordingly; the first switches S1 corresponding to R3 and R4 are both closed, and the first basic layout 401 is used accordingly; the second switches S2 corresponding to C1, C2 and C3 are all open, and the second basic layout 402 is used accordingly; the third switches S3 corresponding to C1, C2 and C3 are all closed, and the first basic layout 401 is used accordingly; the second switches S2 corresponding to C4, C5 and C6 are all closed, and the first basic layout 401 is used accordingly; the third switches S3 corresponding to C4, C5 and C6 are all open, and the second basic layout 402 is used accordingly. For the second stage of the delay circuit: the first switches S1 corresponding to R1, R2, R3 and R4 are all open, and the second basic layout 402 is used accordingly; the second switches S2 corresponding to C1, C2 and C3 are all closed, and the first basic layout 401 is used accordingly; the third switches S3 corresponding to C1, C2 and C3 are all open, and the second basic layout 402 is used accordingly; the second switches S2 corresponding to C4, C5 and C6 are all open, and the second basic layout 402 is used accordingly; the third switches S3 corresponding to C4, C5 and C6 are all closed, and the first basic layout 401 is used accordingly.

[0087] Reference is made to Figure 16 and Figure 17 For the first stage of the delay circuit: the first switches S1 corresponding to R1, R2, R3 and R4 are all open, and the second basic layout 402 is used accordingly; the second switches S2 corresponding to C1, C2, C3, C4, C5 and C6 are all open, and the second basic layout 402 is used accordingly; the third switches S3 corresponding to C1, C2, C3, C4, C5 and C6 are all closed, and the first basic layout 401 is used accordingly. For the second stage of the delay circuit: the first switches S1 corresponding to R1, R2, R3 and R4 are all open, and the second basic layout 402 is used accordingly; the second switches S2 corresponding to C1, C2, C3, C4, C5 and C6 are all open, and the second basic layout 402 is used accordingly; the third switches S3 corresponding to C1, C2, C3, C4, C5 and C6 are all closed, and the first basic layout 401 is used accordingly. That is, the actual delay of the first stage of the delay circuit and the actual delay of the second stage of the delay circuit can be different.

[0088] In some examples, Figures 10 to 17The four different layouts and corresponding delay circuits can realize different delay time, such as 8ns, 9ns, 10ns, 12ns. The four different delay circuits have little difference in layout, only in that the first switch area A1, the second switch area A2 and the third switch area A3 call the first basic layout 401 or the second basic layout 402 to adjust whether the corresponding resistance adjustment unit 12 and the capacitance adjustment unit 13 are connected with the basic delay circuit 101.

[0089] In other words, according to the need, whether the switch corresponding to the first switch area A1, the second switch area A2 and the third switch area A3 is opened or closed can be adjusted to adjust the RC time constant of the delay circuit, and then adjust the size of the delay. In the process of modifying the layout to meet different delay requirements, only whether the conductive layer is laid out in the first switch area A1, the second switch area A2 and the third switch area A3 needs to be adjusted, and the purpose of adjusting the delay can be achieved.

[0090] Therefore, under the premise of unchanged layout area, more delay size options can be provided, that is, delay circuits with different delay times can be designed, which is beneficial to improve the cost problem caused by layout modification and reduce the number of masks that need to be changed involved in layout modification.

[0091] In addition, the first transistor in the resistance adjustment unit 12 which is not connected to the basic delay circuit 101 can be used as a dummy transistor, which can increase the manufacturing accuracy of other transistors. Similarly, the second transistor in the capacitance adjustment unit 13 which is not connected to the basic delay circuit 101 can also be used as a dummy transistor.

[0092] In addition, it can be understood that each basic delay layout 201 and the corresponding resistance adjustment layout 202 and capacitance adjustment layout 203 can also be formed into a standard delay layout, and the actual delay time of the delay circuit corresponding to different standard delay layouts can be different. In this way, during the layout modification process, a standard delay layout with a first delay time can be used to replace a standard delay layout with a second delay time, thereby realizing the rapid modification of the layout. Alternatively, some standard delay layouts can be selected from N standard delay layouts for cascading.

[0093] Correspondingly, the embodiment of the disclosure also provides a method for realizing different delay times, which can use the delay circuit or layout provided by the above-mentioned embodiment. The method embodiment will be described in detail below. It should be noted that the description of the above-mentioned embodiment is also applicable to the method embodiment, and the above-mentioned embodiment will not be described in detail below to avoid repetition. In addition, the description of the method in the following embodiment is also applicable to the above-mentioned embodiment of the delay circuit and the layout.

[0094] In combination with referenceFigures 1 to 17 The layout is provided, and the layout is revised based on a preset delay requirement. It is selected whether to layout the first conductive layer in the first switch region A1 in each group of resistance layout 32, and it is selected to layout the second conductive layer in one of the second switch region A2 or the third switch region A3 in each group of capacitance layout 33. That is, the actual delay of the delay circuit corresponding to the revised layout meets the preset delay requirement.

[0095] In combination with reference Figures 9 to 17 In some embodiments, the providing the layout can include: providing a first basic layout 401 used as the first switch region A1 with the conductive layer, as the second switch region A2 with the conductive layer, or as the third switch region A3 with the conductive layer; providing a second basic layout 402 used as the first switch region A1 without the conductive layer, as the second switch region A2 without the conductive layer, or as the third switch region A3 without the conductive layer; selecting whether to layout the conductive layer in the first switch region A1 in each group of resistance layout 32 includes: calling one of the first basic layout 401 or the second basic layout 402; selecting to layout the conductive layer in one of the second switch region A2 or the third switch region A3 in each group of capacitance layout 33 includes: calling one of the first basic layout 401 or the second basic layout 402.

[0096] The relationship between the first switch region A1, the second switch region A2, and the third switch region A3 and the first basic layout 401 and the second basic layout 402 has been described in detail in the foregoing embodiments, and reference can be made to the description of the foregoing embodiments to avoid repetition.

[0097] In addition, each basic delay layout and the corresponding resistance adjustment layout 202 and capacitance adjustment layout 203 can constitute a standard delay layout, and the delay of the delay circuit corresponding to each standard delay layout can be different. The providing the layout includes: providing N standard delay layouts, and the delay circuits corresponding to different standard delay layouts have different delays; and the revising the layout includes: based on a preset delay requirement, selecting M standard delay layouts from the N standard delay layouts for cascading, where M is less than or equal to N. Both M and N are positive integers greater than 1.

[0098] In addition, the revising the layout can also include: replacing one or more standard delay layouts with a first delay in the layout with a standard delay layout with a second delay to constitute the layout. It can be understood that different standard delay layouts in a plurality of standard delay layouts with a first delay can have different first delays, and similarly, different standard delay layouts in a plurality of standard delay layouts with a second delay can also have different second delays.

[0099] The method for implementing different delays provided by the embodiments of the present disclosure can design a group of delay circuits with different delay sizes to have similar layouts, that is, a group of delay circuits with different delay sizes have similar circuit structures. In this way, by adjusting whether the first, second and third switch regions in the layout are laid out with the conductive layer, the RC parameters of the delay circuit corresponding to the layout can be adjusted, the requirement of different delays can be met by changing only one layer of conductive layer, and meanwhile, it is also beneficial to the rapid revision of the layout.

[0100] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A layout for a delay circuit, characterized in that, Used to define a delay circuit, the delay circuit comprising: A basic delay circuit is connected between the operating power supply and ground, and has a first input terminal and a first output terminal. The first input terminal is used to receive a first signal, and the first output terminal is used to output a second signal, wherein the second signal has a preset delay compared to the first signal. A resistor adjustment circuit, connected between the basic delay circuit and the operating power supply, and / or connected between the basic delay circuit and ground, includes at least one set of resistor adjustment units. Each set of resistor adjustment units includes a first transistor and a first switch. The first transistor has a first gate, a first terminal and a second terminal. The first gate receives a preset voltage, and the first switch is connected between the first terminal and the second terminal. A capacitor regulation circuit, connected between the first output terminal and the operating power supply, and / or connected between the first output terminal and the ground terminal, includes at least one set of capacitor regulation units. Each set of capacitor regulation units includes a second transistor, a second switch, and a third switch. The second transistor has a second gate, a third terminal, a fourth terminal, and a substrate terminal, wherein the third terminal, the fourth terminal, and the substrate terminal are directly connected. The second switch is connected between the second gate and the third terminal, and the third switch is connected between the second gate and the first output terminal. Wherein, when the first switch is open, the corresponding resistor adjustment unit constitutes an equivalent resistance connected to the basic delay circuit; when the second switch is open and the third switch is closed, the corresponding capacitor adjustment unit constitutes an equivalent capacitor connected to the basic delay circuit. The territory includes: A basic delay layout is used to define the basic delay circuit. A resistor adjustment layout is used to define the resistor adjustment circuit, including at least one set of resistor layouts. Each set of resistor layouts is used to define a set of resistor adjustment units. Each set of resistor layouts includes a first switching area, which is used to define a first switch. If the first switching area has a conductive layer, the first switch is closed. If the first switching area does not have a conductive layer, the first switch is open. A capacitor adjustment layout is used to define the capacitor adjustment circuit, including at least one set of capacitor layouts. Each set of capacitor layouts defines a set of capacitor adjustment units. Each set of capacitor layouts includes a second switching area and a third switching area. The second switching area defines a second switch, and the third switching area defines a third switch. If the second switching area has a conductive layer, the second switch is closed; if the second switching area does not have a conductive layer, the second switch is open. If the third switching area has the conductive layer, the third switch is closed; if the third switching area does not have a conductive layer, the third switch is open. The areas of the first switching area, the second switching area, and the third switching area are the same.

2. The layout as described in claim 1, characterized in that, The resistor adjustment layout and the capacitor adjustment layout are located on opposite sides of the basic delay layout.

3. The layout as described in claim 1, characterized in that, The capacitor regulation layout also includes: A capacitor transistor region is used to define the second transistor. The capacitor transistor region includes a second gate region, a third terminal region, a fourth terminal region, and a substrate region, respectively used to define the second gate, the third terminal, the fourth terminal, and the substrate terminal. The first connection region, the second connection region, the third connection region, and the fourth connection region are respectively used to define the first conductive pillar, the second conductive pillar, the third conductive pillar, and the fourth conductive pillar that are electrically connected to the second gate, the third terminal, the fourth terminal, and the substrate terminal. The second switching area overlaps with the first connection area and also overlaps with the second connection area; the third switching area overlaps with the first connection area.

4. A method for achieving different delays, characterized in that, include: Provide a layout as described in any one of claims 1-3; Based on the preset delay requirements, the layout is modified to select whether to lay a conductive layer in the first switching area of ​​each group of resistor layouts, and to lay a conductive layer in either the second switching area or the third switching area of ​​each group of capacitor layouts.

5. The method as described in claim 4, characterized in that, The map provided includes: A first basic layout is provided, which is used as a first switching region having a conductive layer, a second switching region having a conductive layer, or a third switching region having a conductive layer. A second basic layout is provided, which is used as a first switching region without a conductive layer, a second switching region without a conductive layer, or a third switching region without a conductive layer. The selection of whether to lay a conductive layer in the first switch area of ​​each group of resistor layouts includes: calling one of the first basic layout or the second basic layout; The step of selecting to lay out a conductive layer in either the second switching region or the third switching region in each set of capacitor layouts includes: calling one of the first basic layouts or the second basic layout.

6. The method as described in claim 4, characterized in that, Each of the basic delay layouts and the corresponding resistor adjustment layouts and capacitor adjustment layouts constitutes a standard delay layout; The map provided includes: N standard delay layouts are provided, and the delay circuits corresponding to different standard delay layouts have different delays; The modification of the map includes: Based on the preset delay requirement, M standard delay layouts are selected from N standard delay layouts and cascaded, where M is less than or equal to N.

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