Low complexity probability shaping distribution matching method based on fpga hardware implementation

Abstract

The application belongs to the technical field of optical fiber communication, and particularly relates to a low-complexity probability shaping distribution matching method based on FPGA hardware implementation. In the distribution matching method, the address of a read-only memory (ROM) is increased by 1 every clock cycle, and a clock internal data is read out, a second road and a fourth road data in a four-way parallel binary sequence are increased with a flag bit and a decision whether to flip the flag bit through an intra-symbol bit weight distribution matching operation, so that the probability of the appearance of a bit '1' in the second road and the fourth road is increased, and the expected transmission symbol is obtained through serial-parallel conversion and Gray mapping. In the application, no multiplier and divider are needed, only a small amount of registers are needed, the number of redundant bits is small, the calculation and hardware complexity are low, a reliable scheme is provided for an intensity modulation / direct detection (IM / DD) system, and the application can be used in an IM / DD transmission system short-distance optical interconnection of a future WDM scheme.

Description

Technical Field

[0001] This invention belongs to the field of optical fiber communication technology, specifically relating to a low-complexity probabilistic integer distribution matching method based on FPGA hardware implementation. Background Technology

[0002] With the rapid development of bandwidth-intensive applications such as cloud computing and big data, current communication systems face severe challenges in improving transmission rates and capacity. Quadrature amplitude modulation (QAM) and discrete multi-frequency modulation (DMT) in short-distance optical interconnects, intensity modulation, and direct detection systems have been widely studied due to their advantages such as cost savings, fiber dispersion tolerance, and spectral efficiency. Furthermore, to reduce the inherent peak-to-average power ratio (PAPR) problem of DMT and the resulting fiber nonlinearity, Discrete Fourier Transform Extension (DFT-S) technology has been introduced, offering low complexity and high efficiency. However, with the continuous increase in optical signal-to-noise ratio (OSNR), the fiber nonlinearity caused by the inherent power constraint problem in optical communication systems is becoming increasingly severe, leading to a significant deterioration in transmission performance.

[0003] In recent years, probabilistic shaping (PS) technology has attracted widespread attention in the field of optical communication due to its advantages in improving OSNR tolerance and supporting flexible spectral efficiency. A high-throughput real-time verification platform based on FPGA is needed to measure the bit error rate (BER) after forward error correction (approximately 10^6). -15 However, real-time implementation of the distribution matching method (DM) is challenging. In the initial schemes, Constant Component Distribution Matching (CCDM) based on Arithmetic Coding (AC) was proposed. With long DM codewords, the CCDM scheme suffers almost no rate loss, and therefore it is widely used in PS systems. However, CCDM requires very high-precision multiplication and division operations, which are very resource-intensive, and the AC algorithm used for CCDM is essentially a serial sequential method. These two characteristics determine that CCDM is difficult to implement in high-speed real-time hardware with high parallelism. Besides CCDM, there are many related works on DM algorithms, such as Multiset Partition Distribution Matching (MPDM), Multicomponent DM (MCDM), Framed Prefix-Free Code DM (PCDM), Enumerated Spherical Shape (ESS), Hierarchical DM (HiDM), and Huffman-Coded Spherical Shape (HCSS); however, most schemes are still in the validation stage. Summary of the Invention

[0004] The purpose of this invention is to provide a low-complexity probabilistic integer distribution matching method based on FPGA hardware, which has fewer redundant bits and lower computational and hardware complexity.

[0005] The low-complexity probabilistic integer distribution matching method proposed in this invention, implemented in FPGA hardware, increments the address of the read-only memory (ROM) by 1 after each clock cycle, reads out the data within one clock cycle, and increases the probability of '1' appearing in the data within one clock cycle by using a symbol-based bit weight distribution matching operation. The data within one clock cycle is converted from serial to parallel to generate four parallel binary sequences. Flag bits and decision bits for flipping the flag bits are added to the second and fourth data sequences. Specifically, the second and fourth data sequences are divided into several groups by bit. The bits in each group are summed, and a decision threshold is set. If the sum is greater than the decision threshold, the first bit, i.e., the flag bit, is defined as "1". The bits used for summation are then appended to the flag bit to obtain the shaped bit string. If the sum is less than the decision threshold, the flag bit is defined as "0", and the bits used for summation are flipped and appended to the flag bit. This operation greatly increases the probability of "1" appearing in the second and fourth data sequences. Finally, the desired transmission symbol is obtained by converting the four data sequences from serial to parallel and performing Gray mapping.

[0006] The present invention will be further explained below using a 16QAM signal as an example.

[0007] The low-complexity distribution matching method described in this invention specifically includes three parts: data preprocessing, intra-symbol bit weight distribution matching, and symbol mapping.

[0008] (1) Data preprocessing, the principle of which is shown in the appendix. Figure 1 As shown.

[0009] Assuming a shaping factor k, DMT modulation has n b First, data to be processed is generated offline and cached in a read-only memory (ROM). The width and depth of the ROM are determined by the size of the shaping factor k and the number of preprocessing steps. After each clock cycle, the ROM address is incremented by 1, and data for one clock cycle is read out. The length of the output data in one clock cycle is M bits. The M bits of data stream are then converted from serial to parallel according to bit arrangement to obtain four parallel data streams: G1, G2, G3, and G4. These four data streams are temporarily stored in four registers. The register length for temporarily storing G1 and G3 is g1, and the register length for temporarily storing G2 and G4 is g2. Intra-symbol bit weight distribution matching is performed on the G2 and G4 data streams. N is the bit length in each clock cycle after PS encoding. The width M of the read-only memory (ROM) is used to store G1, G2, G3, and G4. The register lengths g1 and g2 are shown below:

[0010] N = n b *log216 (1)

[0011]

[0012] g1 = N / 4 (3)

[0013] g2=(MN / 2) / 2 (4)

[0014] Here, [.] represents the floor function.

[0015] (2) Symbolic bit weight distribution matching:

[0016] As we know, the 16 points of 16QAM exhibit three amplitude distributions, which can be considered as three circles. However, the distance between the inner circle and the second circle is significantly greater than the distance between the second and third circles. This leads to most bit errors originating from the four constellation points of the outer circle. Probabilistic shaping reduces the bit error rate by increasing the probability of the inner circle constellation points. Furthermore, by increasing the probability of the inner circle constellation points, the average power of the shaped 16QAM signal is much lower than that of the original 16QAM signal with an equal probability distribution, thus saving transmission power. This is beneficial for reducing nonlinear transmission impairments caused by high transmission power in optical communication transmission systems. Intra-symbol bit weight distribution matching, by adding flag bits and bit flipping coding, changes the probability distribution of "0" and "1" bits in the original two-dimensional coding matrix with equal probability distribution, thereby mapping to a transmission symbol with a specific probability distribution.

[0017] The principle of intra-symbol bit weight distribution matching is as follows: Figure 2 As shown.

[0018] After the first part of data preprocessing, four data streams are obtained: G1, G2, G3, and G4. Intra-symbol bit weight distribution matching is then performed on the G2 and G4 data streams.

[0019] In the intra-symbol bit weight distribution matching, the G2 and G4 distributions are divided into i groups by bit, with a group size of k bits. Simultaneously, i summation registers S are constructed. i and i registers F that store the shaped data i F i The length is k+1. Summation is performed on the i groups, and the results are stored in S. i In the middle, if S i If the value is greater than k / 2, then F i The first bit, i.e., the flag bit, is defined as "1", while the k bits used for summation remain unchanged and are stored in F. i The last k bits are set to '0', otherwise the flag bit is set to '0', and the last k bits are inverted. Then, memories G'2 and G'4 are constructed to store the bits after the symbol weight distribution matching. The memory length is N / 4. After traversing i groups once, F is set to... i Reassemble the data bit by bit and store it in G'2 and G'4.

[0020] Therefore, through the intra-symbol bit weight distribution matching operation, the k-bit set will be changed to (k+1) bits, where the probability of "1" will be effectively increased. After intra-symbol bit weight distribution matching, the i-th data stream G... i The probability of getting "0" and "1" can be expressed as follows:

[0021]

[0022] in, and These represent operations on the smallest / largest integer that is greater than or less than its internal value.

[0023] (3) Symbolic mapping:

[0024] After matching the bit weight distribution within the symbol, G1, G'2, G3, and G'4 are rearranged bit-by-bit and reconverted from parallel to serial to restore the transmitted data sequence and mapped into a transmitted symbol. Gray mapping is used because the probability of the 16QAM signal being mapped to the inner circle of the constellation diagram after this transformation is significantly increased. This aligns with the expected outcome of the 16QAM signal constellation diagram after probability shaping. The symbol mapping rules used are as follows: Figure 3 As shown.

[0025] This invention utilizes flag bits added to specific channels and bit-flipping encoding techniques to design a low-complexity probabilistic shaping distribution matching method implemented in FPGA hardware. This effectively solves the problem of high average power in traditional 16QAM signals with high bit error rates. The main components of this invention are bit-level flipping and flag bit addition operations. Compared to other distribution matching methods, this method requires only a small number of registers and no multipliers or dividers during hardware implementation. It offers advantages such as fewer redundant bits and lower computational and hardware complexity, providing a low-complexity and reliable solution for direct modulation / detection (IM / DD) systems. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the principle of probabilistic integer coding.

[0027] Figure 2 The matching rule diagram for the bit weight distribution within the symbol.

[0028] Figure 3 It is a Gray mapping rule graph.

[0029] The labels in the diagram are as follows: 1 is the serial M-bit pseudo-random binary sequence (PRBS), 2 is the serial-to-parallel transformation, 3 is the parallel sequence G1, 4 is the parallel sequence G2, 5 is the parallel sequence G3, 6 is the parallel sequence G4, 7 is the length of parallel sequence G1 (N / 4 bits), 8 is the length of parallel sequence G2 ((MN / 2) / 2 bits), 9 is the length of parallel sequence G3 (N / 4 bits), 10 is the length of parallel sequence G4 ((MN / 2) / 2 bits), 11 is the intra-symbol bit weight distribution matching, 12 is the parallel-to-serial transformation, 13 is the probabilistic integer coding, 14 is the first time step, 15 is the N-bit Gray mapping, 16 is the J-th time step, 17 is the original bit stream a, 18 is the length of the original bit stream a (k bits), 19 is the summation of the original bit stream a (sum(a)), and 20 is the summation of the original bit stream (sum(a)) greater than k / 2 (>k / 2)? 21 is the flag bit = '0', 22 is the transformed bitstream b equal to the inverse of the original bitstream a: b = ~(a), 23 is the flag bit = '1', 24 is the transformed bitstream b equal to the original bitstream a: b = a, 25 is the length of the bitstream after matching the bit weight distribution within the symbol: k+1 bits, 26 is the flag bit, 27 is the transformed bitstream b, 28 is the length of the transformed bitstream b: k bits, 29 is the matching of the bit weight distribution within the symbol. Detailed Implementation

[0030] This invention proposes a novel distributed matching method. In hardware implementation, after each clock cycle, the address of the read-only memory (ROM) is incremented by 1, and data within one clock cycle is read. The probability of a '1' appearing in the data within one clock cycle is increased using a symbol-based bit weighted distributed matching operation. The data within one clock cycle is converted from serial to parallel to generate four parallel binary sequences. Flag bits and decision bits for whether to flip the flag bits are added to the second and fourth sequences to increase the probability of a '1' appearing in the second and fourth sequences. Finally, the desired transmission symbol is obtained through serial-to-parallel conversion and Gray mapping. Compared to other distributed matching methods, this method requires only a small number of registers and does not require multipliers and dividers in hardware implementation. This method has the advantages of fewer redundant bits and lower computational and hardware complexity, providing a low-complexity and reliable solution for direct modulation / detection (IM / DD) systems.

[0031] The invention will be further illustrated below using a 16QAM signal as an example. The low-complexity distribution matching method specifically includes three parts: data preprocessing, intra-symbol bit weight distribution matching, and symbol mapping, wherein:

[0032] (1) Data preprocessing, the principle of which is shown in the appendix. Figure 1 As shown.

[0033] Assuming a shaping factor k, DMT modulation has nb For each data subcarrier, the data to be processed is first generated offline and cached in a read-only memory (ROM). The width and depth of the ROM are determined by the integer factor k and the number of preprocessing steps. After each clock cycle, the ROM address is incremented by 1, and data for one clock cycle is read out. The length of the output data for one clock cycle is M bits. The M bits of data stream are then converted from serial to parallel according to bit arrangement to obtain four parallel data streams: G1, G2, G3, and G4. These four data streams are temporarily stored in four registers. The length of registers G1 and G3 is g1, and the length of registers G2 and G4 is g2. Intra-symbol bit weight distribution matching is performed on the G2 and G4 data streams. N is the bit length in each clock cycle after PS encoding. The width M of the ROM is used to store the lengths g1 and g2 of registers G1, G2, G3, and G4, as shown below, where [.] represents the floor function.

[0034] N = n b *log216 (1)

[0035]

[0036] g1 = N / 4 (3)

[0037] g2=(MN / 2) / 2 (4)

[0038] (2) Symbolic bit weight distribution matching:

[0039] We know that the 16 points of 16QAM exhibit three amplitude distributions, which can be considered as three circles. However, the distance between the inner circle and the second circle is significantly greater than the distance between the second and third circles. This leads to most bit errors originating from the four constellation points of the outer circle. Probabilistic shaping reduces the bit error rate by increasing the probability of the inner circle constellation points. Furthermore, by increasing the probability of the inner circle constellation points, the average power of the shaped 16QAM signal is much lower than that of the original 16QAM signal with an equal probability distribution, thus saving transmission power. This is beneficial for reducing nonlinear transmission impairments caused by high transmission power in optical communication transmission systems. Intra-symbol bit weight distribution matching, by adding flag bits and bit flipping coding, changes the probability distribution of "0" and "1" bits in the original two-dimensional coding matrix with equal probability distribution, thereby mapping to a transmission symbol with a specific probability distribution.

[0040] The principle of the symbolic bit weight distribution matching module is as follows: Figure 2 As shown.

[0041] After the first part of data preprocessing, four data streams are obtained: G1, G2, G3, and G4. Then, the intra-symbol bit weight distribution matching is performed on the G2 and G4 data.

[0042] In the intra-symbol bit weight distribution matching, the G2 and G4 distributions are divided into i groups by bit, with a group size of k bits. Simultaneously, i summation registers S are constructed. i and i registers F that store the shaped data i F i The length is k+1. Summation is performed on the i groups, and the results are stored in S. i In the middle, if S i If the value is greater than k / 2, then F i The first bit, i.e., the flag bit, is defined as "1", while the k bits used for summation remain unchanged and are stored in F. i The last k bits are set to '0', otherwise the flag bit is set to '0' and the last k bits are inverted. Then, memories G'2 and G'4 are constructed to store the bits after the symbol weight distribution matching. Both memories have a length of N / 4. After traversing i groups once, F... i Reassemble the data bit by bit and store it in G'2 and G'4.

[0043] Therefore, through the intra-symbol bit weight distribution matching operation, the k-bit set will be changed to (k+1) bits, where the probability of "1" will be effectively increased. After intra-symbol bit weight distribution matching, the i-th data stream G... i The probability of getting "0" and "1" can be expressed as follows:

[0044]

[0045] in and These represent operations on the smallest / largest integer that is greater than or less than its internal value.

[0046] (3) Symbolic mapping:

[0047] After matching the bit weight distribution within the symbol, G1, G'2, G3, and G'4 are rearranged bit-by-bit and reconverted from parallel to serial to restore the transmitted data sequence and mapped as a transmitted symbol. Gray mapping is used because the probability of the 16QAM signal being mapped to the inner circle of the constellation diagram after this transformation is significantly increased. This aligns with our expectations for the 16QAM signal constellation diagram after probability shaping. The symbol mapping rules used are attached. Figure 3 As shown.

[0048] Table 1 compares the on-chip resource usage of intra-symbol bit weight distribution matching with the other three reported distributed matching methods. It can be seen that, compared to the other three reported distributed matching methods, intra-symbol bit weight distribution matching requires only a few CLB LUTs and CLB registers. Compared to HiDM, intra-symbol bit weight distribution matching can save 88.6% of CLB LUTs and does not require Block RAM.

[0049] Table 1. Comparison of resource utilization rates

[0050] Resource usage HiDM PCDM(n=300, DM / inDM Symbolic bit weights CLB LUT 5458 2123523) 292546 621 CLB 4910 5455 544424 5248 RBloick 31 0 98 0 .

Claims

1. A low-complexity probabilistic shaping distribution matching method for 16QAM subcarrier modulation in discrete multi-tone (DMT) systems, characterized in that, In the FPGA hardware implementation, the address of the read-only memory ROM is incremented by 1 after each clock cycle. The data corresponding to a 16QAM-DMT symbol is read out within one clock cycle, and a probability shaping operation is performed on the bits inside the symbol within the cycle. The probability of '1' appearing in the data within one clock cycle is increased by using the bit weight distribution matching operation within the symbol. Within one clock cycle, data is converted from serial to parallel to generate four parallel binary sequences. Flag bits and decision bits for flipping the flag bits are added to the second and fourth data streams. Specifically, the second and fourth data streams are divided into several groups by bit, and the bits in each group are summed. A decision threshold is set. If the sum is greater than the decision threshold, the first bit, i.e., the flag bit, is defined as "1". At this time, the bit used for summation is appended to the flag bit to obtain the shaped bit string. If it is less than the decision threshold, the flag bit is defined as "0", and the bit used for summation is flipped and appended to the flag bit. This operation increases the probability of the bit "1" appearing in the second and fourth data streams. Finally, by converting the four data streams from serial to parallel and performing Gray mapping, the desired transmission symbol is obtained; Specifically, it includes three parts: data preprocessing, intra-symbol bit weight distribution matching, and symbol mapping. (1) Data preprocessing Assuming a shaping factor k, DMT modulation has n b The system uses several data subcarriers. First, the data to be processed is generated offline and cached in a read-only memory (ROM). The width and depth of the ROM are determined by the size of the shaping factor k and the number of preprocessing steps. After each clock cycle, the ROM address is incremented by 1, and data for one clock cycle is read out. The length of the output data for one clock cycle is M bits. The M bits data stream is then converted from serial to parallel according to bit arrangement to obtain four parallel data streams: G1, G2, G3, and G4. These four data streams are temporarily stored in four registers. The register length for temporarily storing G1 and G3 is g1, and the register length for temporarily storing G2 and G4 is g2. Intra-symbol bit weight distribution matching is performed on the G2 and G4 data streams. N is the bit length in each clock cycle after PS encoding. The width M of the read-only memory (ROM) is used to store the G1, G2, G3, and G4 registers. The register lengths g1 and g2 are shown below: N=n b *log216 (1) g1 = N / 4 (3) g2=(MN / 2) / 2 (4) Where [.] represents the floor function; (2) Symbolic bit weight distribution matching By adding flag bits and bit-flipping encoding, the probability distribution of "0" and "1" bits in the original two-dimensional encoding matrix with equal probability distribution of "0" and "1" bits is changed, so as to map a transmission symbol with a specific probability distribution; specifically, after the data preprocessing in the first part, four data channels are obtained: G1, G2, G3 and G4; the intra-symbol bit weight distribution matching is performed on the G2 and G4 data; Divide the distributions of G2 and G4 into i groups by bit, with each group consisting of k bits; simultaneously construct i summation registers S. i and i registers F that store the shaped data i F i The length is k+1; summation is performed on the i groups, and the results are stored in S. i In the middle, if S i If the value is greater than k / 2, then F i The first bit, i.e., the flag bit, is defined as "1", while the k bits used for summation remain unchanged and are stored in F. i The last k bits are set; otherwise, the flag bit is '0' and the last k bits are inverted; then, memories G'2 and G'4 are constructed to store the bits after the symbol weight distribution matching, both with a length of N / 4. After traversing i groups once, F is set... i Reassemble and store the data in G'2 and G'4 bit by bit; Therefore, through the intra-symbol bit weight distribution matching operation, the k-bit set will be changed to (k+1) bits, where the probability of "1" will be effectively enhanced; after the intra-symbol bit weight distribution matching, the i-th data stream G i The probability of getting "0" and "1" is expressed by the following formula: in, and These represent operations on the smallest / largest integer that is greater than or less than its internal value; (3) Symbolic mapping After completing the matching of bit weight distribution within the symbol, G1, G'2, G3, and G'4 are arranged bit by bit, re-converted from parallel to serial, restored to the transmission data sequence, and mapped to the transmission symbol; the mapping method adopts Gray mapping.

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