Cascade bottleneck testing method, device, equipment and medium between switching chips

Abstract

The embodiment of the present invention discloses a cascade bottleneck test method, device, equipment and medium between switching chips. The method includes: pairing the first switching chip and the second switching chip interconnected by the cascade port to be tested with two switching ports to form multiple switching port groups; when it is determined that the number of test ports of the tester does not meet the test requirements of all switching port groups, determining the number of outer rings and the number of inner rings; while realizing the inner ring bidirectional forwarding of full-load traffic on the first type of port group matching the number of inner rings, the tester performs a packet loss rate test of full-load traffic on the second type of port group matching the number of outer rings to obtain the bottleneck test result of the cascade port to be tested. The technical solution of the embodiment of the present invention achieves the effect of effective bottleneck testing by only a small number of tester ports by introducing the inner ring bidirectional forwarding mechanism in the cascade bottleneck test process, thereby reducing the dependence on test resources to the greatest extent.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a cascade bottleneck testing method between switching chips, a cascade bottleneck testing device between switching chips, an electronic device and a computer-readable storage medium. Background Art

[0002] In order to realize high-density and high-capacity switches, the switching capacity and port number of the switch are often expanded by cascading switching chips. However, the cascading ports between the switching chips usually become the bottleneck of the overall switching capacity of the switch.

[0003] In the prior art, after two switching chips are interconnected through a cascade port, it is necessary to first test whether the cascade port has a cascade bottleneck during line-speed forwarding. Figure 1 As shown. When performing the cascade bottleneck test, it is necessary to divide the two switching ports between the switching chips into a group and connect them to the two ports (transmitting port and receiving port) on the tester. After that, each transmitting port on the tester sends full-load traffic to the connected switching port, and at the same time, the packet loss rate test is performed based on the traffic data received by each receiving port from the connected switching port.

[0004] Obviously, the existing cascade bottleneck test method requires that all switch ports in the two interconnected switch chips be connected to corresponding tester ports. When the number of switch ports included in the switch chip is large, there may be insufficient tester ports, and effective cascade bottleneck testing cannot be achieved. Summary of the invention

[0005] The embodiments of the present invention provide a cascade bottleneck test method between switching chips, a cascade bottleneck test device between switching chips, an electronic device and a computer-readable storage medium, so as to realize effective cascade bottleneck test through a small number of tester ports.

[0006] According to one aspect of an embodiment of the present invention, a method for testing a cascade bottleneck between switching chips is provided, comprising:

[0007] Pairing the switch ports of the first switch chip and the second switch chip interconnected by the cascade port to be tested in pairs to form a plurality of switch port groups;

[0008] When it is determined that the number of test ports of the tester does not meet the test requirements for all switch port groups, the number of outer rings and the number of inner rings are determined;

[0009] While achieving bidirectional forwarding of full-load traffic in the inner ring on the first type port group that matches the number of inner rings, the tester performs a packet loss rate test of full-load traffic on the second type port group that matches the number of outer rings to obtain the bottleneck test result of the cascade port to be tested.

[0010] According to another aspect of an embodiment of the present invention, a cascade bottleneck testing device between switching chips is provided, comprising:

[0011] A switch port pairing module, used for pairing the switch ports of a first switch chip and a second switch chip interconnected by the cascade port to be tested in pairs, to form a plurality of switch port groups;

[0012] The inner and outer ring quantity determination module is used to determine the outer ring quantity and the inner ring quantity when it is determined that the number of test ports of the tester does not meet the test requirements of all switch port groups;

[0013] The bottleneck test module is used to realize bidirectional forwarding of full-load traffic on the first type port group that matches the number of inner rings, and at the same time, perform a packet loss rate test of full-load traffic on the second type port group that matches the number of outer rings through the tester to obtain the bottleneck test result of the cascade port to be tested.

[0014] According to another aspect of an embodiment of the present invention, an electronic device is provided, the electronic device comprising:

[0015] at least one processor; and

[0016] a memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the cascade bottleneck testing method between switching chips described in any embodiment of the present invention.

[0018] According to another aspect of an embodiment of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the cascade bottleneck testing method between switching chips described in any embodiment of the present invention when executed.

[0019] The technical solution of the embodiment of the present invention determines the number of outer rings and the number of inner rings when it is determined that the number of test ports of the tester does not meet the test requirements for all switch port groups, and implements full-load traffic inner ring bidirectional forwarding on the first type of port group that matches the number of inner rings. At the same time, the tester performs a full-load traffic packet loss rate test on the second type of port group that matches the number of outer rings to obtain the bottleneck test result of the cascade port to be tested. The technical solution of the embodiment of the present invention introduces an inner ring bidirectional forwarding mechanism in the cascade bottleneck test process, thereby achieving the effect of effective cascade bottleneck testing with only a small number of tester ports, thereby reducing the dependence on test resources to the greatest extent.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 It is a block diagram for realizing cascade bottleneck test between switching chips provided by the prior art;

[0023] Figure 2 This is a flow chart of a cascade bottleneck testing method between switching chips provided according to the first embodiment of the present invention;

[0024] Figure 3 is a flow chart of a cascade bottleneck testing method between switching chips provided according to Embodiment 2 of the present invention;

[0025] Figure 4 It is a block diagram for implementing a cascade bottleneck test between switching chips applicable to the technical solution of an embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of the structure of a cascade bottleneck testing device between switching chips provided according to Embodiment 3 of the present invention;

[0027] Figure 6 The invention is a structural schematic diagram of an electronic device for implementing a cascade bottleneck testing method between switching chips according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] Embodiment 1

[0031] Figure 2 This is a flow chart of a method for testing cascade bottlenecks between switching chips provided in the first embodiment of the present invention. This embodiment is applicable to the case of testing cascade bottlenecks on cascade ports between switching chips. The method can be performed by a cascade bottleneck testing device between switching chips. The cascade bottleneck testing device between switching chips can be implemented in the form of hardware and / or software, and can generally be configured in an electronic device with data processing functions and used in conjunction with a tester. Figure 2 As shown, the method includes:

[0032] S110 , pairing the switch ports of a first switch chip and a second switch chip interconnected by the cascade port to be tested in pairs to form a plurality of switch port groups.

[0033] In this embodiment, the cascade port to be tested is a cascade port between a first switch chip and a second switch chip that need to be cascaded and extended. After the cascade connection of the first switch chip and the second switch chip is completed, a cascade bottleneck test needs to be performed on the cascade port to be tested.

[0034] It can be understood that the switching chips for cascade expansion are generally the same type of switching chips, and therefore, the first switching chip and the second switching chip generally have the same number of switching ports.

[0035] The so-called cascade bottleneck test refers to testing whether the packet loss rate of all switch ports meets the preset packet loss rate tolerance condition when the cascade port to be tested is forwarding at line speed (maximum throughput data volume).

[0036] The specific cascade bottleneck test method is: divide the two switching ports between the switching chips into a group. If each switching chip contains N switching ports, a total of N groups of switching ports can be obtained. After that, one switching port in each group of switching ports is controlled to send traffic data to another switching port in each group of switching ports at full load, and the packet loss rate of the full-load traffic data at another switching port is counted. If the packet loss rate of all switching ports meets the packet loss rate tolerance condition, it can be determined that the cascade port to be tested can achieve line-speed forwarding.

[0037] Accordingly, in this embodiment, after determining that the first switching chip and the second switching chip are interconnected through the cascade port to be tested, the first switching chip and the second switching chip are first paired with each other in their switching ports to form a plurality of switching port groups, wherein the number of the switching port groups is consistent with the number of switching ports included in each switching chip.

[0038] In a specific example, if the first switching chip includes switching port a, switching port b, switching port c, switching port d and switching port e, the second switching chip includes switching port A, switching port B, switching port C, switching port D and switching port E. By pairing the switching ports in pairs, five switching port groups can be formed: switching port group 1 {switching port a, switching port A}, switching port group 2 {switching port b, switching port B}, switching port group 3 {switching port c, switching port C}, switching port group 4 {switching port d, switching port D} and switching port group 5 {switching port e, switching port E}.

[0039] S120: When it is determined that the number of test ports of the tester does not meet the test requirements for all switch port groups, determine the number of outer rings and the number of inner rings.

[0040] The number of test ports of the tester does not meet the test requirements for all switch port groups, which means that when only the tester is used to perform cascade bottleneck testing on each switch port group, all switch ports in each switch port group cannot be connected to the tester.

[0041] Optionally, determining that the number of test ports of the tester does not meet the test requirements for all switch port groups may include:

[0042] When the number of test ports of the tester is less than twice the number of the switch port groups, it is determined that the number of test ports of the tester does not meet the test requirements for all the switch port groups.

[0043] Continuing with the previous example, if 5 switch port groups can be formed by pairing the switch ports of the first switch chip and the second switch chip in pairs, the tester needs to have at least 2*5=10 test ports. Otherwise, it is impossible to truly perform full load traffic testing on the cascade ports to be tested through the cascade bottleneck testing technology of the existing technology.

[0044] Accordingly, in this embodiment, for the scenario where the number of test ports of the tester does not meet the test requirements for all switch port groups, a new method of cascade bottleneck testing is proposed.

[0045] Specifically, firstly, the number of outer rings and the number of inner rings are determined according to the number of switch port groups, that is, the sum of the number of outer rings and the number of inner rings is the number of the switch port groups.

[0046] Among them, the number of outer rings can be understood as the total number of first-class traffic transceiver paths formed by the tester and the switch port group. Specifically, each first-class traffic transceiver path is composed of a sending interface in the tester, any switch port group (for example, switch port group 1 {switch port a, switch port A}) and a receiving interface in the tester. A sending interface in the tester sends a full-load flow that matches the switch port a to the switch port a in the switch port group 1. The switch port a forwards the received flow data to the switch port A, and finally sends it from the switch port A to a receiving port in the tester.

[0047] Correspondingly, the number of inner rings can be understood as the total number of second-class traffic receiving and sending channels formed only by the switch port group. Specifically, each second-class traffic receiving and sending channel is composed of any switch port group (for example, switch port group 2 {switch port b, switch port B}) in the form of an inner ring. Among them, both switch port b and switch port B can be set to a self-transmitting and self-receiving state, and then, by interconnecting switch port b and switch port B, a simplest ring channel can be formed. By injecting full-load traffic for the switch port into the above-mentioned ring channel, it is possible to assist in performing full-load traffic testing on the cascade port to be tested.

[0048] In this embodiment, the number of outer rings and the number of inner rings can be preset according to actual conditions, as long as the number of test ports in the tester can build the first-class traffic receiving and sending paths of the outer ring number.

[0049] In an optional implementation of this embodiment, from the perspective of minimizing test resource usage, the number of outer rings can be fixed to 1, and the number of inner rings can be determined as the number of switch port groups minus the number of outer rings. That is, only two test ports in the tester need to be used, and cascade bottleneck testing can be finally achieved.

[0050] In a specific example, if the number of switch port groups is 5, the number of outer rings can be set to 1 and the number of inner rings to 4. At this time, it is necessary to select 5 switch port groups in sequence to respectively construct the first type of traffic receiving and sending paths, and by repeating the test 5 times, finally test the packet loss rates corresponding to the 5 switch port groups.

[0051] In another optional implementation of this embodiment, in order to minimize the test complexity, the number of outer loops can be set to the number of test ports of the tester divided by 2 and rounded down, and the number of inner loops can be determined as the number of switch port groups minus the number of outer loops. That is, by using as many ports in the tester as possible, the complexity of the cascade bottleneck test can be simplified.

[0052] In a specific example, if the number of switch port groups is 5 and the number of test ports in the tester is 6, the number of outer loops can be set to 3 and the number of inner loops can be set to 2. In this case, the packet loss rates corresponding to the three switch port groups can be tested simultaneously in the first test, and the packet loss rates corresponding to the remaining two switch port groups can be tested simultaneously in the second test.

[0053] In practical applications, technical personnel in this field can customize the number of outer rings within the integer range of [1, the number of test ports of the tester divided by 2 and rounded down] according to the dual requirements of test resources and test complexity in actual scenarios. This embodiment does not limit this.

[0054] S130. While implementing bidirectional forwarding of the inner ring at full load flow on the first type port group that matches the number of inner rings, a packet loss rate test of the full load flow is performed on the second type port group that matches the number of outer rings by a tester to obtain a bottleneck test result for the cascade port to be tested.

[0055] In this embodiment, in order to implement effective cascade testing between switch chips when the number of test ports of the tester is insufficient, all switch port groups need to be divided into two categories, namely, first-category port groups and second-category switch port groups.

[0056] The first type of port group is used to construct an inner loop path by self-transmission and self-reception, and to perform bidirectional forwarding on the inner loop path, so as to set the full load occupancy of the switch port for the cascade port to be tested.

[0057] The second type of port group is used to form an outer loop path in combination with a tester, so as to test the packet loss rate of each second type of port group when all the switch ports of the cascade ports to be tested are fully occupied by the tester.

[0058] By continuously updating the second type port group to perform a packet loss rate test of full load traffic, after obtaining the packet loss rate of all or part of the switching port groups, the bottleneck test result of the cascade port to be tested can be obtained.

[0059] The technical solution of the embodiment of the present invention determines the number of outer rings and the number of inner rings when it is determined that the number of test ports of the tester does not meet the test requirements for all switch port groups, and implements full-load traffic inner ring bidirectional forwarding on the first type of port group that matches the number of inner rings. At the same time, the tester performs a full-load traffic packet loss rate test on the second type of port group that matches the number of outer rings to obtain the bottleneck test result of the cascade port to be tested. The technical solution of the embodiment of the present invention introduces an inner ring bidirectional forwarding mechanism in the cascade bottleneck test process, thereby achieving the effect of effective cascade bottleneck testing with only a small number of tester ports, thereby reducing the dependence on test resources to the greatest extent.

[0060] Based on the above embodiments, while injecting full load traffic into one switch port in each second type port group through the tester, after another switch port in each second type port group receives traffic, the method may also include:

[0061] If any of the currently selected second-type port groups fails the packet loss rate test, it is determined that the cascade port to be tested does not meet the line-speed forwarding requirement; or

[0062] If it is determined that all the switch port groups pass the packet loss rate test, it is determined that the cascade port to be tested meets the line-speed forwarding requirement.

[0063] In this embodiment, if all the switching port groups between the switching chips have passed the packet loss rate test, it can be determined that when all the switching ports of the cascaded ports to be tested are fully occupied, the packet loss rate of each switching port meets the preset packet loss rate tolerance condition, and thus it can be indicated that the cascaded port to be tested meets the line-speed forwarding requirement; if any second-class port group between the switching chips fails the packet loss rate test, it can be determined that the cascaded port to be tested does not meet the line-speed forwarding requirement.

[0064] Furthermore, after obtaining the bottleneck test result of the cascading port to be tested, the cascading modes between different switch chips can be evaluated to obtain the optimal cascading mode between the switch chips.

[0065] Embodiment 2

[0066] Figure 3 This is a flow chart of a cascade bottleneck test method between switching chips provided in the second embodiment of the present invention. Based on the above embodiments, this embodiment concretizes the operation of "implementing bidirectional forwarding of the inner ring of full-load traffic on the first type of port group that matches the number of inner rings, and performing a packet loss rate test of the full-load traffic on the second type of port group that matches the number of outer rings through a tester". Figure 3 As shown, the method includes:

[0067] S210 , pairing the switch ports of a first switch chip and a second switch chip interconnected by the cascade port to be tested in pairs to form a plurality of switch port groups.

[0068] S220. When it is determined that the number of test ports of the tester does not meet the test requirements for all switch port groups, the number of outer rings is fixed to 1, and the number of inner rings is determined as the number of switch port groups minus the number of outer rings.

[0069] S230: Divide two switch ports in the same switch port group into the same virtual local area network.

[0070] The switch ports in different switch port groups belong to different virtual local area networks.

[0071] In this embodiment, in order to construct different traffic receiving and sending paths for different switch port groups and ensure that the data traffic between different switch port groups is not interoperable, an independent virtual local area network (Vlan) can be established for each switch port group. For example, if the number of switch port groups is 5, 5 different virtual local area networks can be established.

[0072] S240 . Select the second-type port groups that match the number of outer rings in the switch port groups in sequence, and determine the remaining switch port groups as the first-type port groups.

[0073] S250, two switch ports in each first-class port group form a media access control layer inner ring, and inject full-load traffic into the virtual local area network matching each first-class port group through a tester.

[0074] The media access control (MAC) inner ring refers to setting two switch ports to a state of self-transmission and self-reception to realize a ring-shaped data forwarding channel.

[0075] After the tester injects full-load traffic into the virtual LAN matching each first-class port group, each first-class port group can realize inner-loop bidirectional forwarding of the full-load traffic for the port on the cascade port to be tested.

[0076] S260. While injecting full-load traffic into one switch port in each second-class port group, the tester receives traffic at another switch port in each second-class port group to perform a packet loss rate test on each second-class port group.

[0077] Among them, Figure 4 FIG. 4 is a block diagram showing a cascade bottleneck test implementation between switching chips applicable to the technical solution of an embodiment of the present invention. Figure 4As shown, a switch is obtained by cascading a switch chip 1 and a switch chip 2 through a cascade port. The switch chip 1 and the switch chip 2 have the same structure and both have an even number of switch ports, n / 2. n is an even number greater than 2.

[0078] By pairing the switch ports in switch chip 1 and switch chip 2 in pairs, a total of n / 2 switch port groups can be formed, that is, switch port group 1 {switch port 1, switch port n / 2+1}, switch port group 2 {switch port 2, switch port n / 2+2}, ..., switch port n {switch port n / 2, switch port n}. Furthermore, n / 2 different virtual local area networks can also be constructed accordingly, that is, Vlan1 corresponding to switch port group 1, Vlan2 corresponding to switch port group 2, ..., Vlan(n) corresponding to switch port group n.

[0079] In this optional implementation, in order to minimize the occupation of test resources, only two test ports in the tester and one switch port group may be used to form an outer ring channel, and n / 2-1 switch port groups may be used to form an inner ring channel.

[0080] When actually conducting a cascade bottleneck test, two ports in the tester can be connected to each switch port group in turn, and full-load traffic can be injected into the remaining switch port groups. While the remaining switch port groups implement bidirectional forwarding of full-load traffic in the inner ring, the tester injects full-load traffic into one switch port in each second-class port group, and receives traffic at another switch port in each second-class port group, so as to conduct a packet loss rate test on each second-class port group.

[0081] S270, determine whether all currently selected second-type port groups pass the packet loss rate test, if so, execute S280, otherwise, execute S290.

[0082] S280, determine whether the test of all switch port groups is completed, if so, execute S2100; otherwise, return to execute S240.

[0083] S290: Determine that the cascade port to be tested does not meet the line-speed forwarding requirement.

[0084] S2100: Determine whether the cascade port to be tested meets line-speed forwarding requirements.

[0085] The technical solution of the embodiment of the present invention determines the number of outer rings and the number of inner rings when it is determined that the number of test ports of the tester does not meet the test requirements for all switch port groups, and implements full-load traffic inner ring bidirectional forwarding on the first type of port group that matches the number of inner rings. At the same time, the tester performs a full-load traffic packet loss rate test on the second type of port group that matches the number of outer rings to obtain the bottleneck test result of the cascade port to be tested. The technical solution of the embodiment of the present invention introduces an inner ring bidirectional forwarding mechanism in the cascade bottleneck test process, thereby achieving the effect of effective cascade bottleneck testing with only a small number of tester ports, thereby reducing the dependence on test resources to the greatest extent.

[0086] Embodiment 3

[0087] Figure 5 This is a schematic diagram of the structure of a cascade bottleneck test device between switching chips provided by the third embodiment of the present invention. Figure 5 As shown, the device includes: a switch port pairing module 310 , an inner and outer ring quantity determination module 320 , and a bottleneck testing module 330 .

[0088] The switch port pairing module 310 is used to pair the switch ports of the first switch chip and the second switch chip interconnected by the cascade port to be tested in pairs to form a plurality of switch port groups;

[0089] The inner and outer ring number determination module 320 is used to determine the number of outer rings and the number of inner rings when it is determined that the number of test ports of the tester does not meet the test requirements of all switch port groups;

[0090] The bottleneck test module 330 is used to implement bidirectional forwarding of full-load traffic in the inner ring on the first type port group that matches the number of inner rings, and at the same time, perform a packet loss rate test of full-load traffic on the second type port group that matches the number of outer rings through a tester to obtain the bottleneck test result of the cascade port to be tested.

[0091] The technical solution of the embodiment of the present invention determines the number of outer rings and the number of inner rings when it is determined that the number of test ports of the tester does not meet the test requirements for all switch port groups, and implements full-load traffic inner ring bidirectional forwarding on the first type of port group that matches the number of inner rings. At the same time, the tester performs a full-load traffic packet loss rate test on the second type of port group that matches the number of outer rings to obtain the bottleneck test result of the cascade port to be tested. The technical solution of the embodiment of the present invention introduces an inner ring bidirectional forwarding mechanism in the cascade bottleneck test process, thereby achieving the effect of effective cascade bottleneck testing with only a small number of tester ports, thereby reducing the dependence on test resources to the greatest extent.

[0092] Based on the above embodiments, the inner and outer ring quantity determination module 320 can be specifically used for:

[0093] When the number of test ports of the tester is less than twice the number of the switch port groups, it is determined that the number of test ports of the tester does not meet the test requirements for all the switch port groups.

[0094] Based on the above embodiments, the inner and outer ring quantity determination module 320 can be specifically used for:

[0095] The number of outer rings is fixed at 1, and the number of inner rings is determined as the number of switch port groups minus the number of outer rings.

[0096] Based on the above embodiments, the inner and outer ring quantity determination module 320 can be specifically used for:

[0097] Set the number of outer rings to the number of test ports on the tester divided by 2, rounded down, and determine the number of inner rings as the number of switch port groups minus the number of outer rings.

[0098] Based on the above embodiments, the bottleneck testing module 330 can be specifically used for:

[0099] Dividing two switch ports in the same switch port group into the same virtual local area network, wherein the switch ports in different switch port groups belong to different virtual local area networks;

[0100] Selecting second-type port groups that match the number of outer rings in the switch port groups in sequence, and determining the remaining switch port groups as first-type port groups;

[0101] Two switch ports in each first-class port group form a media access control layer inner ring, and inject full-load traffic into the virtual local area network matching each first-class port group through the tester;

[0102] The tester injects full load traffic into one switch port in each second-class port group, and receives traffic at another switch port in each second-class port group, so as to perform a packet loss rate test on each second-class port group;

[0103] If all currently selected second-type port groups pass the packet loss rate test, the operation of sequentially selecting second-type port groups matching the number of outer rings in the switch port groups is returned to execute until the test of all switch port groups is completed.

[0104] Based on the above embodiments, a first test result module may be further included, which is used to:

[0105] When the tester injects full load traffic into one switching port in each second-class port group and receives traffic at another switching port in each second-class port group, if any currently selected second-class port group fails the packet loss rate test, it is determined that the cascade port to be tested does not meet the line-speed forwarding requirements.

[0106] Based on the above embodiments, a second test result module may be further included, which is used to:

[0107] While implementing full-load traffic inner-ring forwarding on the first-class port group that matches the number of inner rings, the tester performs a packet loss rate test of full-load traffic on the second-class port group that matches the number of outer rings. If all switching port groups pass the packet loss rate test, it is determined that the cascade port to be tested meets the line-speed forwarding requirements.

[0108] The cascade bottleneck testing device between switching chips provided in the embodiment of the present invention can execute the cascade bottleneck testing method between switching chips provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0109] Embodiment 4

[0110] Figure 6 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0111] like Figure 6 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0112] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0113] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 11 executes the various methods and processes described above, such as a cascade bottleneck test method between switching chips described in any embodiment of the present invention.

[0114] The method includes:

[0115] Pairing the switch ports of the first switch chip and the second switch chip interconnected by the cascade port to be tested in pairs to form a plurality of switch port groups;

[0116] When it is determined that the number of test ports of the tester does not meet the test requirements for all switch port groups, the number of outer rings and the number of inner rings are determined;

[0117] While achieving bidirectional forwarding of full-load traffic in the inner ring on the first type port group that matches the number of inner rings, the tester performs a packet loss rate test of full-load traffic on the second type port group that matches the number of outer rings to obtain the bottleneck test result of the cascade port to be tested.

[0118] In some embodiments, the cascade bottleneck test method between switching chips as described in any embodiment of the present invention may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the cascade bottleneck test method between switching chips as described in any embodiment of the present invention described above may be executed. Alternatively, in other embodiments, the processor 11 may be configured to execute the cascade bottleneck test method between switching chips as described in any embodiment of the present invention by any other appropriate means (e.g., by means of firmware).

[0119] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0120] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0121] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0122] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0123] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0124] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0125] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0126] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A cascade bottleneck test method between switching chips, characterized in that: include: Pairing the switch ports of the first switch chip and the second switch chip interconnected by the cascade port to be tested in pairs to form a plurality of switch port groups; When it is determined that the number of test ports of the tester does not meet the test requirements for all switch port groups, the number of outer rings and the number of inner rings are determined; While achieving bidirectional forwarding of full-load traffic in the inner ring on the first type port group that matches the number of inner rings, the tester performs a packet loss rate test of full-load traffic on the second type port group that matches the number of outer rings to obtain the bottleneck test result of the cascade port to be tested.

2. The method according to claim 1, characterized in that Determine that the number of test ports on the tester does not meet the test requirements for all switch port groups, including: When the number of test ports of the tester is less than twice the number of switch port groups, it is determined that the number of test ports of the tester does not meet the test requirements for all switch port groups.

3. The method according to claim 2, characterized in that Determine the number of outer and inner rings, including: The number of outer rings is fixed at 1, and the number of inner rings is determined as the number of switch port groups minus the number of outer rings.

4. The method according to claim 2, characterized in that: Determine the number of outer and inner rings, including: Set the number of outer rings to the number of test ports on the tester divided by 2, rounded down, and determine the number of inner rings as the number of switch port groups minus the number of outer rings.

5. The method according to any one of claims 1 to 4, characterized in that: While implementing bidirectional forwarding of full-load traffic on the first-class port group that matches the number of inner rings, the tester performs a packet loss rate test of full-load traffic on the second-class port group that matches the number of outer rings, including: Dividing two switch ports in the same switch port group into the same virtual local area network, wherein the switch ports in different switch port groups belong to different virtual local area networks; Selecting second-type port groups that match the number of outer rings in the switch port groups in sequence, and determining the remaining switch port groups as first-type port groups; Two switch ports in each first-class port group form a media access control layer inner ring, and inject full-load traffic into the virtual local area network matching each first-class port group through the tester; The tester injects full load traffic into one switch port in each second-class port group, and receives traffic at another switch port in each second-class port group, so as to perform a packet loss rate test on each second-class port group; If all currently selected second-type port groups pass the packet loss rate test, the operation of sequentially selecting second-type port groups matching the number of outer rings in the switch port groups is returned to execute until the test of all switch port groups is completed.

6. The method according to claim 5, characterized in that After the tester injects full load traffic into one switch port in each second type port group and another switch port in each second type port group receives traffic, the tester also includes: If any currently selected second-category port group fails the packet loss rate test, it is determined that the cascade port to be tested does not meet the line-speed forwarding requirement.

7. The method according to claim 5, characterized in that While implementing full-load traffic inner-ring forwarding on the first-class port group that matches the number of inner rings, after the packet loss rate test of full-load traffic on the second-class port group that matches the number of outer rings is performed by the tester, it also includes: If all the switch port groups pass the packet loss rate test, it is determined that the cascade port to be tested meets the line-speed forwarding requirement.

8. A cascade bottleneck test device between switching chips, characterized in that: include: A switch port pairing module, used for pairing the switch ports of a first switch chip and a second switch chip interconnected by the cascade port to be tested in pairs, to form a plurality of switch port groups; The inner and outer ring quantity determination module is used to determine the outer ring quantity and the inner ring quantity when it is determined that the number of test ports of the tester does not meet the test requirements of all switch port groups; The bottleneck test module is used to realize bidirectional forwarding of full-load traffic on the first type port group that matches the number of inner rings, and at the same time, perform a packet loss rate test of full-load traffic on the second type port group that matches the number of outer rings through the tester to obtain the bottleneck test result of the cascade port to be tested.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the cascade bottleneck testing method between switching chips according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the cascade bottleneck testing method between switching chips according to any one of claims 1 to 7 when executed.

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