Electroplating controller with power-based margin control

Abstract

A method for controlling a margin voltage of a transistor stage of an electroplating system to maintain a target power dissipation across the transistor stage may include maintaining the margin voltage in the transistor stage for a load in the electroplating system. The method may also include: measuring an instantaneous power dissipation in the transistor stage; and generating a difference output representing a difference between the instantaneous power dissipation in the transistor stage and the target power dissipation in the transistor stage. The difference output may then be used to adjust a voltage across the transistor stage and the load such that the margin voltage in the transistor stage is adjusted to maintain the target power dissipation in the transistor stage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. non-provisional application No. 17 / 015,612, filed on September 9, 2020, entitled “ELECTROPLATING CONTROLLER WITH POWER BASED HEAD-ROOM CONTROL,” which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The present technology relates to cleaning operations in semiconductor processing. More particularly, the present technology relates to systems and methods for controlling voltage or current in electroplating systems. Background Art

[0004] Integrated circuits are made possible by processes that create intricately patterned layers of material on a substrate surface. After forming, etching, and other processes are performed on the substrate, metal or other conductive materials are typically deposited or formed to provide electrical connections between components. Because this metallization can be performed after many manufacturing operations, problems during metallization can waste expensive substrates or wafers.

[0005] During the formation of the metal material on the wafer or substrate, the substrate can be immersed in a plating bath, and then the metal is formed on the substrate through the electroplating process. Subsequently, the wafer can be raised or otherwise moved and then rinsed at the chamber. During this process, several problems may occur. For example, current electroplating controllers may use voltage-controlled head room to manage the heating of metal oxide semiconductor field effect transistors (MOSFETs) in the control circuit that controls the voltage and current during the electroplating process. Regardless of the power dissipated in the MOSFET, the generated head room voltage is controlled to the same value. This creates a dependency on the response rate of the variable voltage source used to generate the mains voltage for the current or voltage supply to the electroplating system.

[0006] Therefore, there is a need for improved systems and methods that can be used to more efficiently control the margin voltage in an electroplating controller. The present technology addresses these and other needs. Summary of the Invention

[0007] In some embodiments, a circuit for controlling a grace voltage of a transistor stage of an electroplating system to maintain a target power dissipation across the transistor stage may include a transistor stage that provides a grace voltage to a load in the electroplating system. The circuit may also include a power measurement circuit coupled to the transistor stage. The power measurement circuit may provide a signal representing the instantaneous power dissipation in the transistor stage. The circuit may additionally include a differential circuit that receives the signal representing the instantaneous power dissipation in the transistor stage from the power measurement circuit and receives a signal representing the target power dissipation in the transistor stage to generate a differential output. The circuit may further include an adjustable voltage source that provides a voltage across the transistor stage and the load. The adjustable voltage source may be configured to use the differential output to adjust the grace voltage to maintain the target power dissipation in the transistor stage.

[0008] In some embodiments, a method of controlling a margin voltage of a transistor stage of an electroplating system to maintain a target power dissipation across the transistor stage may include: maintaining the margin voltage in the transistor stage for a load in the electroplating system; and measuring the instantaneous power dissipation in the transistor stage. The method may also include: generating a differential output representing a difference between the instantaneous power dissipation in the transistor stage and the target power dissipation in the transistor stage. The method may further include: using the differential output to adjust a voltage across the transistor stage and the load such that the margin voltage in the transistor stage is adjusted to maintain the target power dissipation in the transistor stage.

[0009] In some embodiments, a circuit for controlling a grace voltage of a transistor stage to maintain a target power dissipation across the transistor stage may include a transistor stage that provides a grace voltage to a load. The circuit may also include a power measurement circuit coupled to the transistor stage. The power measurement circuit may provide a signal representative of the instantaneous power dissipation in the transistor stage. The circuit may additionally include an adjustable voltage source that provides a voltage across the transistor stage and the load. The adjustable voltage source may be configured to adjust the grace voltage in the transistor stage in response to the instantaneous power dissipation in the transistor stage to maintain the target power dissipation in the transistor stage.

[0010] In any embodiment, any and / or all of the following features may be implemented in any combination and without limitation. Other features described in this disclosure may also be added to any embodiment in any combination and without limitation. The power measurement circuit may include a voltage measurement circuit coupled to the transistor stage to provide a measurement representing the voltage across the transistor stage. The power measurement circuit may also include a current measurement circuit coupled to the transistor stage to provide a measurement representing the current through the transistor stage. The power measurement circuit may also include a multiplier circuit that receives the measurement representing the voltage across the transistor stage and the measurement representing the current through the transistor stage to generate the signal representing the instantaneous power dissipation in the transistor stage. The differential circuit may include an operational amplifier that provides an output to an AC-to-DC converter. The circuit may include a differential amplifier that receives a signal representing a target current through the transistor stage and receives the instantaneous current through the transistor stage. The differential amplifier may provide a gate voltage to the transistor stage to achieve the target current through the transistor stage. The signal representing the instantaneous power dissipation in the transistor stage may include a voltage proportional to the instantaneous power dissipation. The method / these operations may also include determining a voltage across the transistor stage and / or determining a current through the transistor stage. The method / these operations may also include multiplying the signal representing the voltage across the transistor stage with a signal representing the current through the transistor stage to determine the instantaneous power dissipation in the transistor stage. The method / these operations may also include reducing the margin voltage in the transistor stage as the current through the transistor stage increases. The method / these operations may also include scaling down the signal representing the instantaneous power dissipation in the transistor stage. The method / these operations may also include generating a transition in the voltage across the transistor stage and the load, the transition having a fall time of less than 10 ms. The target power dissipation may be represented by a plurality of series resistors forming a voltage divider. The adjustable voltage source may include an AC to DC power converter. The power measurement circuit may be implemented using a microprocessor or microcontroller. The circuit may also include a serial interface that receives serial commands from a controller and converts the serial commands into a plurality of analog and digital signals to control the circuit for controlling the margin voltage of the transistor stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A further understanding of the nature and advantages of the various embodiments may be realized by reference to the remainder of this specification and the accompanying drawings, wherein like reference numerals are used throughout the drawings to refer to like components. In some cases, a sub-label is associated with a reference numeral to indicate one of multiple like components. When a reference numeral is referenced without specifying the existing sub-label, all such multiple like components are intended to be referred to.

[0012] Figure 1 A schematic isometric view of an electroplating system is shown, in which the method and the cleaning system may be used and implemented according to embodiments.

[0013] Figure 2 A partial cross-sectional view of a chamber including aspects of an electroplating apparatus according to some embodiments is shown.

[0014] Figure 3 An electroplating apparatus is shown that may include a user interface computer according to some embodiments.

[0015] Figure 4 Shown according to some embodiments Figure 3 A block diagram of one of the one or more plating channels shown in FIG.

[0016] Figure 5 A circuit is shown for maintaining a margin voltage for power regulation in accordance with some embodiments.

[0017] Figure 6 An example circuit diagram of a voltage differential amplifier configured to generate a voltage representative of a current through a transistor stage is shown in accordance with some embodiments.

[0018] Figure 7 An example of fall time associated with a constant voltage margin control system is shown in accordance with some embodiments.

[0019] Figure 8 An example of fall time associated with a variable voltage margin to maintain constant power dissipation is shown in accordance with some embodiments.

[0020] Figure 9 A method of adjusting a margin voltage for constant power dissipation according to some embodiments is shown.

[0021] Figure 10 An exemplary computer system is shown in which various embodiments may be implemented. DETAILED DESCRIPTION

[0022] Electroplating is a process that uses an electric current or voltage signal to control the deposition of a metal or metal compound onto the surface of a substrate. Electroplating is used in many applications, including, for example, the manufacture of integrated circuits. In such applications, precise control of the metal deposition rate and geometry is required. This requires accurate control of the electroplating current, especially as microelectronic components on semiconductor substrates continue to shrink.

[0023] The plating current can advantageously be controlled digitally or via a programmable controller. Programmable outputs can be used to optimize the plating rate. Semiconductor manufacturing equipment can be used to manufacture a variety of products. Programmable controllers allow the equipment to be easily used to plate different products. Manufacturing equipment has two or more anodes, a cathode connected to a wafer or substrate, and an optional thief electrode. The programmable controller in this equipment controls multiple channels simultaneously, creating further engineering challenges.

[0024] Electroplating equipment may also preferably have the ability to accurately control the output current with a high dynamic range. It is generally desirable for an electroplating system to provide a wide range of output currents to provide effective control of the electroplating process. The current required for the electroplating process may vary over a wide range, for example, from a few milliamperes to tens of amperes.

[0025] Electroplating operations can be performed to provide conductive material into vias and other features on a substrate. Electroplating utilizes an electrolyte bath containing ions of the conductive material to electrochemically deposit the conductive material onto the substrate and into defined features on the substrate. The substrate on which the metal is being plated serves as a cathode. Electrical contacts (e.g., rings or pins) can allow current to flow through the system. During electroplating, the substrate can be clamped to a head and immersed in a plating bath to form a metallization. In a system such as that described below, the substrate can also be clamped in a seal that can be coupled to the head during processing. When the substrate is moved or raised after electroplating, it can be rinsed with water (e.g., deionized water) before being sent to another plating chamber or some other processing location.

[0026] The voltage and / or current provided to the electroplating process can be controlled by a digital controller. This controller can provide a variable voltage source across the electroplating load and the control transistor in series. A margin voltage can be maintained at the transistor level to provide a voltage buffer to adapt to the sudden change of the voltage distribution across the load. Conventional technology may use a constant margin voltage, which is maintained when the voltage across the load changes. However, these technologies limit the speed at which the voltage / current across the load can change. The rise time and fall time are of the order of 100ms, and usually discontinuity is produced in the output. Other technologies may use a very large voltage margin to adapt to faster rise times. However, these technologies produce very high power dissipation in the form of heat in the control system.

[0027] The present technology overcomes these issues by using dynamic margin voltages. These techniques maintain a target power dissipation level at the transistor level, rather than maintaining a constant margin voltage. During the initial stages of the electroplating process, when the current is very low, the margin voltage can be very large. This large margin voltage can accommodate very fast rise times. As the current through the transistor level increases, the margin voltage can be reduced to maintain a constant power dissipation level. These techniques balance power dissipation with maintaining sufficient margin voltage to achieve rise and / or fall times on the order of 1 ms.

[0028] Figure 1 A schematic isometric view of an electroplating system 100 is shown to which methods and cleaning systems may be used and implemented, depending on the embodiment. The electroplating system 100 may include a system head 110 and a basin 115. During the electroplating operation, a wafer may be clamped to the system head 110, inverted, and extended into the basin 115 to perform the electroplating operation. The electroplating system 100 may include a head lifter 120 that may be configured to raise and rotate the system head 110, or otherwise move or position the head within the system, including tilting operations. The head and basin may be attached to a deck 125 or to other structures that may be part of a larger system that incorporates multiple electroplating systems 100, and these electroplating systems may share electrolytes, voltage control systems, and / or other materials.

[0029] The rotor can allow a substrate clamped to the head to rotate within the basin, or rotate outside the basin in different operations. The rotor can include a contact ring that provides conductive contact with the substrate. A seal 130 can be connected to the system head 110. The seal 130 can contain the chucked wafer to be processed. Figure 1 The electroplating system 100 is shown as one that can include components to be cleaned directly on the platform. Other configurations are possible, including a platform on which the system head 110 moves to an additional module and on which the seals 130 or other components are cleaned. In addition, one or more components (e.g., seals 130) can be removed from the corresponding chamber and placed in a maintenance system or cleaning system for cleaning. Any number of other operations that provide or expose components for cleaning can be performed. An exemplary in-situ flushing system 135 is also shown with the system 100.

[0030] Figure 2 A partial cross-sectional view of a chamber including aspects of an electroplating apparatus 200 according to some embodiments is shown. The electroplating apparatus 200 can be incorporated into an electroplating system, including the electroplating system 100 described above. Figure 2As shown in FIG, a plating bath vessel 205 of an electroplating system is shown with a head 210 having a substrate 215 coupled thereto. In some embodiments, the substrate can be coupled to a seal 212 incorporated into the head 210. A rinse frame 220 can be coupled above the plating bath vessel 205 and can be configured to receive the head 210 within the plating bath vessel 205 during electroplating. The rinse frame 220 can include a rim 225 extending circumferentially around an upper surface of the plating bath vessel 205. A rinse channel 227 can be defined between the rim 225 and the upper surface of the plating bath vessel 205. For example, the rim 225 can include an inner sidewall 230 characterized by an inclined profile. As described above, rinsing fluid from the substrate can contact the sidewall 230 and can be received in a plenum 235 extending around the rim 225 for collecting the rinsing fluid from the electroplating apparatus 200. Weir 240 can extend around the plating bath vessel 205 and can be fluidly coupled to the plenum 235 or the rinse channel 227 to further restrict the rinse fluid from returning to the plating bath. Weir 240 can define a plane 245 across the plating apparatus 200 through which the head 210 can extend into the plating bath vessel 205 and through which the head 210 can return to perform a rinse operation.

[0031] Figure 3 An electroplating apparatus according to some embodiments is shown that may include a user interface computer 312. The user interface computer 312 can be coupled to an electroplating control computer 320 using, for example, an Ethernet interface 322. The Ethernet interface 322 can be used for communication with devices that are not time-critical, such as communication with the user interface computer 312. The individual electroplating control computers 320 can communicate with one or more electroplating subsystems 360 via, for example, an EtherCAT interface 324. Each of the one or more electroplating subsystems 360 can control one or more anodes in an electroplating chamber.

[0032] Each plating subsystem 360 can have one or more channels 330, each of which can be connected to a region in the plating chamber 370. Multiple plating chamber regions can be used to control radial plating uniformity on the substrate. For simplicity, the plating subsystem 360 components are referred to herein as PPS (plating power supply assembly). Figure 3 Three different sample PPS configurations are shown. The first PPS configuration shows four channels connected to support two plating chambers 370, with each plating chamber using two channels. The second example shows a PPS configuration with two channels supporting a single plating chamber. The third example shows a PPS configuration with three channels supporting a plating chamber with three channels per plating chamber.

[0033] Figure 4 Shown according to some embodiments Figure 3 . The plating channel 330 can be connected to the control board 440. Although for clarity, in Figure 4 , the control board 440 may be coupled to more than one plating channel. The control board 440 may include circuitry for interfacing between the AC to DC power block 432 and the EtherCAT interface 324. Operating the AC to DC power block 432 may include communicating control information from the plating control computer 320 via the EtherCAT interface 324 to control the operation of the AC to DC power block 432. The AC to DC power block 432 may include an AC to DC power converter. The control information may include digital control information specifying whether the output electrical control signal is a voltage or a current, and analog control information specifying a target output electrical control signal value and a corresponding duration.

[0034] The control board 440 may include one or more current sensors. To achieve a wider range of plating currents, a high-range current sensor 441 and a low-range current sensor 442 may be provided. However, in some embodiments, a single current sensor or more than two current sensors may be used without limitation to receive additional current measurements.

[0035] Control board 440 may also include one or more current-switching elements 443 to pass current through high-range current sensor 441. Current-switching elements 443 may include one or more MOSFETs controlled by digital signal DO2p, which hard-on the MOSFETs for low power dissipation in the one or more current-switching elements 443. Control board 440 may also include one or more current-switching elements 444 to pass current through low-range current sensor 442. These current-switching elements 444 may be controlled by analog output Olp and a control circuit that connects the current-switching elements 444 in series with the AC-to-DC power block 432. In some embodiments, the current-switching elements 444 may function as linear buck regulators.

[0036] The control board 440 may also include EtherCAT digital and analog input and output circuitry in an I / O interface 445. Software running in the electroplating control computer 320 may control the corresponding electroplating subsystem 360 by activating digital outputs, setting analog outputs to control electroplating current or voltage set points, and reading back digital and analog inputs to report and record electroplating process sensor measurements (e.g., current and voltage). The I / O interface 445 may be configured to distribute these analog and digital signals throughout the control board 440.

[0037] The control board 440 may also include an isolation circuit 446. The optional isolation circuit 446 may be used to prevent electrical interaction between the electroplating power delivery circuitry and the interface / control circuitry. Furthermore, the control board 440 may include an operational amplifier circuit (op amp circuit) 447 and / or an operational amplifier circuit 448 to provide closed-loop control. For example, the operational amplifier circuit 447 may control the AC to DC power block 432. The operational amplifier circuit 448 may control the one or more switching elements 444, which may include low-range transistors. The AC to DC power block 432 may typically have an on / off control that may be controlled by software running in the electroplating control computer 320 using a digital output DO1p.

[0038] The electroplating apparatus 310 may further include a blocking diode 433 to prevent interaction between the AC-to-DC power block 432 and other AC-to-DC power blocks in other channels when the AC-to-DC power block 432 is connected together in the electroplating chamber. For example, it may be necessary to perform electroplating in some areas and de-plating in different areas simultaneously. If a region is designed for de-plating, the diode 433 may be reversed, and the polarity of the voltage from the AC-to-DC power block 432 may be reversed.

[0039] To start an electroplating operation, the operator may input a desired or target electroplating process into the user interface computer 412. This may include a desired mode (e.g., voltage or current) to be used by the channels of the electroplating system, a desired set point (e.g., 2.5 A), and a desired duration (e.g., 1 minute). The input process parameters may be sent to the electroplating control computer 320, which may control the time-sensitive electroplating operations of the apparatus.

[0040] Next, the semiconductor processing equipment can bring the substrate to the electroplating chamber 370, typically via a robotic arm, and immerse it in the electroplating solution. Software in the electroplating control computer 320 can control the PPS 360 by sending EtherCAT commands to activate digital and analog outputs in the PPS 360 to transmit desired settings. The digital output DO controls the operating mode (e.g., current or voltage), range (e.g., high-range current or low-range current), and power delivery state (e.g., on or off). The analog output AO can represent the desired setpoint current or voltage that the PPS 360 should deliver. The electroplating control computer 320 can have calibration tables for each channel, mode, and range of each PPS 360. These calibration tables can be used to transmit the desired setpoint (e.g., electroplating current in amperes) based on the calibration results for each specific channel. The described method can include looking up the calibration table to obtain the corresponding operating point of the circuit that generates the output electrical control signal based on the control information received over the EtherCAT interface. Calibration tables stored in either the electroplating control computer 320 or the electroplating subsystem 360 can be used to convert user-programmed set points in amperes or volts to corresponding operating set points for the control circuitry. This conversion can be performed in the electroplating control computer 320, where the EtherCAT interface information is the calibrated set point (e.g., DAC counts), or in the electroplating subsystem, where the EtherCAT interface information is the target amperage or volts.

[0041] If the PPS 360 has multiple current sensors, software running in the electroplating control computer 320 can determine which range to use for each step of the process based on the desired set point and the minimum operating range of the AC to DC power block 432. For example, when it is appropriate to use the high range, the control input that passes current through the high range current sensor 441 can be selected, and the control input that passes current through the low range sensor 442 can be turned off.

[0042] Circuitry on the control board 440 can use established techniques, such as proportional-integral-derivative control (PID), to drive the control pins of the AC-to-DC power block 432 so that the feedback signal matches the setpoint signal. For example, to implement the I term of the PID control for the high-range current control mode, the operational amplifier circuit 447 can be configured to generate a control output O2i=k.sub.2f(A0-FBi), where FBi=FB2i, the high-range current feedback signal from the high-range current sensor 441, and A0 is the setpoint signal from the electroplating control computer 320. If the digital output (DO) signals that voltage control mode should be used instead of current mode, then FBi=FB3i, the voltage feedback signal FB3i from the feedback sensing circuit 450. The operational amplifier circuit 447 can use operational amplifiers and analog multiplexers to generate the desired control signals. The first and second current sensors (or the high-range and low-range current sensors) can generate feedback signals indicating the magnitude of the output electrical control signal during high-range and low-range operation, respectively.

[0043] Operational amplifier circuit 447 and operational amplifier circuit 448 may be implemented on either side of isolation circuit 446 .

[0044] When the PPS 360 is required to deliver a current mode having a current less than the minimum operating range of the AC-to-DC power block 432, or when the low-range current control circuit is desired to provide more accurate electroplating results, the PPS control signal is selected to pass the current through the low-range current sensor 442 and the control signal DO2p that passes the current through the high-range current sensor 441 is turned off. In this mode, two separate control loops can be used. One loop can include an operational amplifier circuit 447 that controls the AC-to-DC power block 432 to provide a fixed drain-to-source voltage (referred to as a "sweep voltage") to the low-range transistors in the one or more switching elements 444. In this mode, the operational amplifier circuit 447 can use the sweep voltage sensing circuit 449 to provide an output O2i = k.sub.hrf (k.sub.HRnorm-HRi) control signal to the AC-to-DC power block 432. The value of k.sub.HRnorm may be a desired margin voltage for normal operation of the one or more switching elements 444 , and HRi may be a measured margin voltage from the margin voltage sensing circuit 449 .

[0045] The second loop may include an operational amplifier circuit 448 that can control the low-range transistors in the one or more switching elements 444. The operational amplifier circuit 448 can act as a post-regulator for the AC-to-DC power block 432 to direct its output toward a current sensor optimized for lower currents. The operational amplifier circuit 448 can be controlled using established control techniques. For example, to implement the I term of the PID control for the low-range current control mode, O1i = k.sub.1f(A0-FBi), where FBi = FB1i, the low-range current sensor reading, and A0 is the setpoint signal from the electroplating control computer 420.

[0046] The control board may include circuitry designed to minimize transients when transitioning between ranges. For semiconductor electroplating, where the rate changes during the plating process, the process may typically begin with a lower plating current and then transition to a higher plating current later in the process. The AC-to-DC power block 432 can generate power for both ranges, but the one or more switching elements 444 may require a certain voltage drop ("margin") for proper operation. For example, the one or more switching elements 444 may be implemented by one or more transistors (e.g., MOSFET transistors). Therefore, for the purposes of this example, the one or more switching elements 444 may also be interchangeably referred to as low-range transistors. When operating in the low range, this allows the low-range transistors in the one or more switching elements 444 to adjust to regulate the current at the desired value, even when the AC-to-DC power block cannot operate accurately (or at all) at the desired output. The AC-to-DC power block 432 generally adjusts more slowly than the one or more switching elements 444, so when switching from the low range to the high range, the margin required for low-range operation may be set so that the AC-to-DC power block 432 generates a higher current than the current required for the subsequent high-range step. For example, if the low-range current is 2.0 amps and the high-range current is 2.5 amps, with a load of 1 ohm and a margin of 3 volts, the desired PPS output voltage is 2×1=2V. The output of the AC-to-DC power block 432 to achieve a 3V margin would be 2V+3V=5V. If the unit were to immediately switch to the high range, the expected current would be 5V / 1 ohm=5A, which is higher than the desired 2.5A setpoint. This would result in a current spike greater than the desired setpoint until the AC-to-DC power block 432 adjusts its output down to the level required for the high-range current step.

[0047] Many semiconductor electroplating processes are more sensitive to currents greater than the set point than to currents less than the set point. To reduce the likelihood of currents greater than the desired set point during range transitions, separate control DACs and circuits for current control in the high and low ranges can be used. Also, circuitry can be provided to select the desired margin for the low range mode. The normal margin setting, k.sub.HRnorm, provides more margin for the low range transistors to control the output. Just before changing to high range mode, a lower margin setting, k.sub.HRmin, can be selected. This reduces the output of the AC to DC power block 432 to a minimum margin level (reducing the margin of the low range transistors to control the output in response to load changes). Then, when the PPS controller changes to high range, the system is less likely to overshoot the desired set point.

[0048] In low-range mode, the low-range transistors can respond more quickly to changes than the AC-to-DC power block. The circuit can be designed to react more quickly to "greater than set point" conditions than to "less than set point" conditions, which is generally desirable from a process perspective and also to protect the low-range transistors from damage caused by power dissipation limitations. In addition, the control circuit's I term (integral term) response speed is automatically slowed when the margin decreases below a threshold level. This allows for a fast response when sufficient margin is available, but slows the response to follow the response of the AC-to-DC power block when margin is insufficient. This prevents the I term from accumulating in the low-range control circuit and the subsequent overshoot that would result without this feature.

[0049] Power-based margin voltage

[0050] Maintaining a generous voltage on the low-range transistor as described above allows the circuit to respond to changes in the voltage distribution across the load. For example, if the voltage distribution across the load starts at 2V and rises to 7V, maintaining a sufficiently generous voltage on the low-range transistor allows the circuit to respond by allowing the voltage across the load to increase faster than would normally be possible due to the additional voltage maintained in the margin of the low-range transistor. Thus, the generous voltage provides the benefit of allowing the voltage response curve to rise quickly.

[0051] If maintaining extra voltage within the margin of the low-range transistor is the only concern, the AC-to-DC power block 432 could simply set the voltage across the low-range transistor 444 to a maximum value (e.g., 24V), which would allow the voltage at the load to quickly rise to any voltage level within the range. However, operating the low-range transistor 444 at a very high voltage inevitably results in a significant amount of power being dissipated in the low-range transistor 444. For example, when the current through the low-range transistor 444 begins to increase, the power dissipated by the low-range transistor 444 can be defined as the instantaneous current multiplied by the instantaneous voltage. When the margin voltage across the low-range transistor 444 is always maximized, the resulting power dissipated by the low-range transistor 444 can be very high as the current increases. This power can be dissipated as heat in the control board 440. When the margin voltage is unnecessarily high, the heat dissipated by the low-range transistor 444 can damage the low-range transistor 444, the printed circuit board, and / or other nearby components.

[0052] In some embodiments, the margin voltage maintained across the low-range transistor is maintained at a constant level greater than the operating voltage across the load. For example, some embodiments may program the AC to DC power block 432 to maintain a margin voltage across the low-range transistor 444 that is at least 3V greater than the load voltage. If the voltage across the load is 2V, the voltage across the transistor may be maintained at approximately 5V to maintain a constant margin voltage of 3V. If the load voltage rises from 2V to 5V, a margin voltage of 3V may be sufficient to allow the voltage to increase without hysteresis for a rise time on the order of 100ms. By maintaining this minimum constant margin voltage, the power dissipated by the low-range transistor 444 may be minimized while still providing sufficient margin for a slow voltage increase across the load.

[0053] While maintaining a constant margin voltage reduces the power dissipated in low-range transistor 444, this generally does not provide a margin voltage sufficient to support a rapid increase in the voltage profile across the load. For example, the fixed margin voltage described above cannot support a rise time significantly less than 100 ms. The output of low-range transistor 444 may lag behind the desired voltage profile at the output, resulting in discontinuities in the output curve. Therefore, it is difficult to support a rapid rise time on the order of 1 ms while maintaining a constant margin voltage.

[0054] To overcome this technical challenge, the embodiments described herein maintain a constant power dissipation in the low-range transistor. The current through the low-range transistor and the voltage across the low-range transistor can be monitored in real time and multiplied to generate the instantaneous power dissipation in the low-range transistor. This power dissipation can be provided to a voltage differential amplifier used as a feedback input to an adjustable voltage source. Instead of maintaining a constant margin voltage, the margin voltage can be dynamically changed as the current through the low-range transistor changes. For example, at very low currents, a very high margin voltage can be maintained because the product of these two terms will result in relatively low power dissipation. As the current begins to rise, the margin voltage can be reduced to maintain this constant power dissipation. Because the initial voltage margin is large enough to support the rapid initial rise of the output voltage on the load, this solution provides a rise time on the order of 1 ms.

[0055] Figure 5 A circuit for maintaining a margin voltage for power regulation according to some embodiments is shown. This circuit can be operated as a standalone circuit in many different applications to regulate the margin voltage across a transistor or switch stage to maintain constant power dissipation in the transistor stage. In one specific embodiment, Figure 5 Certain components of this circuit depicted in FIG. 4 can be used to implement Figure 4 The circuit components of the control board 440 are shown in FIG. The circuit may include a transistor stage 544, and Figure 4 The one or more switching elements 444 in the transistor stage 544 can be implemented using one or more transistors in the transistor stage 544. For example, a transistor such as that from International Transistor stage 544 may be implemented using one or more transistors such as the IRFP3810 series Power MOSFET. Figure 5 The circuit in is configured to monitor the margin voltage maintained across this transistor stage 544 .

[0056] A voltage measurement circuit can be provided to measure the voltage across transistor stage 544. In some embodiments, the voltage measurement circuit can be implemented using a voltage differential amplifier 549 to measure the voltage across transistor stage 544. For example, voltage differential amplifier 549 can receive two inputs, with a first input coupled to the drain of the last transistor in transistor stage 544 and a second input coupled to the starting source of transistor stage 544. The output of voltage differential amplifier 549 can be a scaled value proportional to the voltage difference across transistor stage 544 and, therefore, representative of the voltage across transistor stage 544.

[0057] In addition to measuring the voltage across transistor stage 544, the circuit may also include a current measurement circuit that measures the current through transistor stage 544. The current measurement circuit may be implemented using a voltage differential amplifier 542 configured to generate a voltage proportional to the current through transistor stage 544. Figure 6 5 shows an example circuit diagram of a voltage differential amplifier 542 configured to generate a voltage representative of the current through a transistor stage 544 in accordance with some embodiments. A relatively small resistor 602 may be placed in series with the transistor stage 544. Figure 6 In an example embodiment, the resistor may have a value of approximately 0.1 ohms and may be made from a Y08560R10000F9W from Vishay. To measure the voltage across resistor 602, this example uses an amplifier 604 (e.g., from Texas Instruments). AMC1100 amplifier for current sensing) and amplifiers such as those from Texas Note that these components and component values ​​are provided by way of example only and are not meant to be limiting. Many other implementations of the current measurement circuit can be used with different components. Figure 6 The example of is shown only to provide a feasible disclosure and it represents only one of many possible implementations that fall within the scope of this disclosure. Also note that similar circuits can be used for Figure 5 For example, each of the voltage differential amplifiers 542 and 549 can use the same Figure 6 The circuit shown in FIG is similar to the circuit shown in FIG but with different input and component values. For the sake of simplicity, the circuit is not shown in this article. Figure 5 Each of these voltage differential amplifier implementations in Figure 6 circuit.

[0058] Back to Figure 5 , where the output of voltage differential amplifier 549 represents the instantaneous voltage across transistor stage 544, and the voltage output of voltage differential amplifier 542 represents the instantaneous current through transistor stage 544, the circuit has two components for measuring standard power. The voltage measurement and the current measurement can be provided to a multiplier circuit that produces the product of these two inputs. In this particular example, the multiplier circuit can be implemented by an analog multiplier 575. The analog multiplier 575 can use a digital multiplier such as from Analog This component can be implemented with a component such as the AD633 analog multiplier. This component can allow the output to be scaled down by a factor of 10 to keep the output product within the operating voltage range of the component. The output can be a signal representing the instantaneous power dissipation in transistor stage 544.

[0059] As used herein, a signal may "represent" a voltage, current, power, or other electrical characteristic of a circuit when the signal is proportional to, inversely proportional to, or can be otherwise converted into a voltage, current, power, or other electrical characteristic of the circuit. For example, the scaled voltage output of the analog multiplier 575 may be a voltage that can be converted into instantaneous power dissipation. In another example, the output of the voltage differential amplifier 549 may represent the voltage across the transistor stage 544. Even though the output of the voltage differential amplifier 549 will not be the exact voltage across the transistor stage 544, it is proportional to that voltage. Similarly, the output of the voltage differential amplifier 542 may represent the current through the transistor stage 544 as a voltage proportional to that current.

[0060] The voltage differential amplifiers 542, 549 and the analog multiplier 575 that measure the instantaneous voltage and current of the transistor stage 544 may be collectively referred to as a power measurement circuit 581. Figure 5 and Figure 6 The circuit elements shown in the figure for implementing the power measurement circuit 581 are provided by way of example only and are not meant to be limiting. Many other types of analog / digital circuits can be used to measure the instantaneous power dissipation in the transistor stage 544. For example, a microcontroller or microprocessor can receive analog voltage / current signals from the transistor stage 544 and convert those signals into digital values. The microcontroller or microprocessor can then generate an output signal to control the adjustable voltage source 532. In another example, a power measurement integrated circuit can receive a voltage signal and / or a current signal from the transistor stage 544 and can output a signal that can be used to directly control the adjustable voltage source 532. Other methods of implementing the power measurement circuit 581 are also within the scope of this disclosure.

[0061] As used herein, the term "coupled to" can describe circuit elements that send and receive electrical signals to each other. Two components can be electrically coupled when a signal based on the output of one component is provided as an input to the other component. For example, voltage differential amplifier 549 is coupled to transistor stage 544 by receiving a voltage signal from transistor stage 544. Similarly, voltage differential amplifier 542 is coupled to transistor stage 544 by receiving a current signal output from transistor stage 544. Note that two components can be coupled together through additional components. For example, voltage differential amplifier 549 is coupled to voltage differential amplifier 547, even if analog multiplier 575 processes the signal between the two components.

[0062] The output of the analog multiplier 575 can be provided to a differential circuit that calculates the difference between the two signals. A different circuit can be implemented using another voltage differential amplifier 547. Another input of the voltage differential amplifier 547 can receive a fixed voltage source 580. The fixed voltage source 580 can represent a target power dissipation to be maintained in the transistor stage 544. The target power dissipation can be expressed as a voltage scaled to correspond to the scaled output of the analog multiplier 575. Figure 4 In the example of FIG. 5 , the voltage differential amplifier 547 may represent an operational amplifier circuit 447 that provides a control signal to the AC to DC power block 432, which may implement Figure 5 The output of the voltage differential amplifier 547 can provide an error signal that is converted into an output DC voltage across the transistor stage 544 and the load 576. The voltage differential amplifier 547 can be configured using a rectifier such as that from Texas Instruments. Fixed voltage source 580 can be implemented using a component such as an LM358 operational amplifier. Fixed voltage source 580 can be implemented using any type of voltage source, such as a series resistor acting as a voltage divider from a known reference voltage or rail voltage. In some embodiments, voltage source 580 can be dynamically programmable by software in the system so that the power dissipated by transistor stage 544 can be set to any value.

[0063] The gate voltage applied to transistor stage 544 may be received from voltage differential amplifier 548. Voltage differential amplifier 548 may receive a command from I / O interface 445 representing a target current through load 576. The instantaneous current measurement received from voltage differential amplifier 542 may be provided to voltage differential amplifier 548, and the output of voltage differential amplifier 548 may provide the gate voltage of transistor stage 544. Adjusting the gate voltage on transistor stage 544 may regulate the amount of current through transistor stage 544 until it matches the target current value in the command. Figure 4 In the example of FIG. 5 , load 576 may represent the electroplating chamber described above.

[0064] Figure 7 An example of the fall time associated with a constant voltage margin control system according to some embodiments is shown. In this example, the margin of the voltage across the transistor can be maintained at a constant value, as described in the previous embodiments above. When dropping approximately 15V at 0.9A, the measured fall time 704 is approximately 52.9ms. Furthermore, the voltage drop produces a significant overshoot 702. The discontinuity of overshoot 702 can cause undesirable effects in the electroplating process.

[0065] Figure 8 An example of the fall time associated with a variable voltage margin to maintain constant power dissipation according to some embodiments is shown. In this example, the voltage margin above is used. Figure 5 The circuit described in

[15] is used to maintain the transistor's margin voltage at a constant power dissipation. In this case, when dropping approximately 15V at 1.0A, the fall time 804 is approximately 2.5ms. It is noteworthy that this faster voltage drop results in almost no noticeable overshoot. Therefore, the Figure 5 The constant power dissipation provided by the circuit can effectively reduce discontinuities in the electroplating process associated with fast rise / fall times.

[0066] Figure 9 A method 900 for adjusting a margin voltage for constant power dissipation according to some embodiments is shown. The method may include maintaining a margin voltage in a transistor stage for a load in an electroplating system (902). As described above, the transistor stage may include one or more switching elements, such as MOSFET transistors connected in series and / or parallel. The load may represent a voltage / current provided to the electroplating system to add a metal layer to a substrate or wafer. The margin voltage may represent a voltage across the transistor stage that is maintained at a voltage greater than a voltage across the load. The margin voltage may be maintained to allow the voltage across the load to rise / fall quickly with minimal rise time and / or fall time.

[0067] The method may also include measuring the instantaneous power dissipation in the transistor level (904). The instantaneous power dissipation in the transistor level may be measured using the method described above. Figure 5 and Figure 6 The instantaneous power dissipation can be measured using the power measurement circuitry described in detail in [1]. For example, the instantaneous power dissipation can be measured by measuring the voltage across the transistor stage, measuring the current through the transistor stage, and multiplying these values ​​to produce a signal representing the instantaneous power dissipation in the transistor stage. This signal can be a scaled voltage that can be mathematically converted into a value for the dissipated power. The instantaneous power dissipation can be measured / calculated using individual IC components, discrete board-level components, a microprocessor or microcontroller, and / or using other methods.

[0068] The method may additionally include generating a difference output (906) representing a difference between the instantaneous power dissipation in the transistor level and the target power dissipation in the transistor level. The different signals may be generated as described above in Figure 5 The target power dissipation can be represented by a fixed voltage source, which can be compared to a signal representing the instantaneous power dissipation. The target power dissipation can also be provided as a programmable input so that the instantaneous power dissipation can be changed at run time.

[0069] The method may further include using the differential output to adjust a voltage across the transistor stage and the load such that a margin voltage in the transistor stage is adjusted to maintain a target power dissipation in the transistor stage (908). The voltage may be adjusted by providing the differential output to a programmable AC-to-DC converter that generates a DC output across the load and the transistor stage as described above.

[0070] It should be understood that Figure 9 The specific steps shown in provide specific methods for controlling the margin voltage of the transistor level of the electroplating system to maintain target power dissipation according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps outlined above in a different order. Also, Figure 9 The individual steps shown in the figure may include multiple sub-steps, which may be performed in various sequences suitable for the individual steps. Moreover, additional steps may be added or removed depending on the specific application. Many variations, modifications, and alternatives are also within the scope of this disclosure.

[0071] The various components of the above-described system may be implemented by a computing system including a user interface computer 312 and / or an electroplating control computer 320 . Figure 10 An exemplary computer system 1000 is shown in which various components may be implemented. System 1000 may be used to implement any of the computer systems described above. As shown in the figure, computer system 1000 includes a processing unit 1004, which communicates with multiple peripheral subsystems via a bus subsystem 1002. These peripheral subsystems may include a processing acceleration unit 1006, an I / O subsystem 1008, a storage subsystem 1018, and a communication subsystem 1024. Storage subsystem 1018 includes tangible computer-readable storage media 1022 and system memory 1010.

[0072] The bus subsystem 1002 provides a mechanism for the various components and subsystems of the computer system 1000 to communicate with each other as expected. Although the bus subsystem 1002 is schematically shown as a single bus, alternative embodiments of the bus subsystem may also utilize multiple buses. The bus subsystem 1002 may be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. For example, such architectures may include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus, which may be implemented as a mezzanine bus manufactured according to the IEEE P1386.1 standard.

[0073] The processing unit 1004, which may be implemented as one or more integrated circuits (e.g., conventional microprocessors or microcontrollers), controls the operation of the computer system 1000. One or more processors may be included in the processing unit 1004. These processors may include single-core or multi-core processors. In some embodiments, the processing unit 1004 may be implemented as one or more independent processing units 1032 and / or 1034, each of which includes a single-core or multi-core processor. In other embodiments, the processing unit 1004 may be implemented as a quad-core processing unit formed by integrating two dual-core processors into a single chip.

[0074] In various embodiments, the processing unit 1004 can execute various programs in response to program code and can maintain multiple programs or processes executing in parallel. At any given time, some or all of the program code to be executed may reside in the processor 1004 and / or in the storage subsystem 1018. Through appropriate programming, the processor 1004 can provide the various functionalities described above. The computer system 1000 can additionally include a processing acceleration unit 1006, which can include a digital signal processor (DSP), a special purpose processor, and / or the like.

[0075] I / O subsystem 1008 may include user interface input elements and user interface output elements. User interface input elements may include a keyboard, a pointing element such as a mouse or trackball, a touchpad or touch screen incorporated into a display, a scroll wheel, a click wheel, a dial, buttons, switches, a keypad, an audio input element with a voice command recognition system, a speaker, and other types of input elements. User interface input elements may include, for example, a keyboard such as a Microsoft Motion sensing and / or gesture recognition elements such as motion sensors allow users to control input elements (e.g., Microsoft 360 game controller) and interact with the input element. User interface input elements may also include Google Eye gesture recognition components such as blink detectors detect eye activity from the user (e.g., a "wink" when taking a picture and / or making a menu selection) and convert eye gestures into input components (e.g., Google In addition, the user interface input element may also include a voice recognition sensing element, which allows the user to communicate with the voice recognition system (such as Navigator) interaction.

[0076] User interface input elements may also include, but are not limited to, three-dimensional (3D) mice, joysticks or pointing sticks, game controllers, and graphics tablets, as well as audio / visual elements such as speakers, digital cameras, digital camcorders, portable media players, webcams, image scanners, fingerprint scanners, barcode readers, 3D scanners, 3D printers, laser rangefinders, and eye tracking elements. Furthermore, user interface input elements may also include, for example, medical imaging input elements such as computed tomography, magnetic resonance imaging, positron emission tomography, and medical ultrasound scanning elements. User interface input elements may also include, for example, audio input elements such as MIDI keyboards, digital musical instruments, and the like.

[0077] User interface output elements may include, for example, a display subsystem, indicator lights, or non-visual displays such as audio output elements. The display subsystem may be a cathode ray tube (CRT), a flat panel element (e.g., one using a liquid crystal display (LCD) or plasma display), a projection element, a touch screen, or the like. In general, the use of the term "output element" is intended to include all possible types of elements and mechanisms for outputting information from the computer system 1000 to a user or another computer. For example, user interface output elements may include, but are not limited to, various display elements that visually convey text, graphics, and audio / video information, such as monitors, printers, speakers, headphones, car navigation systems, plotters, voice output elements, and modems.

[0078] Computer system 1000 may include a storage subsystem 1018, including software components shown as currently located within system memory 1010. System memory 1010 may store program instructions loadable and executable on processing unit 1004, as well as data generated during the execution of these programs.

[0079] Depending on the configuration and type of computer system 1000, system memory 1010 can be volatile (e.g., random access memory (RAM)) and / or non-volatile (e.g., read-only memory (ROM), flash memory, etc.). RAM generally contains data and / or program modules that are immediately accessible to and / or currently being operated on and executed by processing unit 1004. In some embodiments, system memory 1010 can include multiple different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some embodiments, a basic input / output system (BIOS), which contains basic routines that help transfer information between elements within computer system 1000, such as during startup, can generally be stored in ROM. By way of example and not limitation, system memory 1010 also shows application programs 1012 (which can include client applications, web browsers, middle-tier applications, relational database management systems (RDBMS), etc.), program data 1014, and an operating system 1016. By way of example, operating system 1016 can include various versions of Microsoft Apple and / or Linux operating system, various commercially available or UNIX-like operating systems (including but not limited to various GNU / Linux operating systems, Google OS, etc.) and / or such as iOS, Phone, OS, 10OS, and OS operating system such as mobile operating system.

[0080] The storage subsystem 1018 may also provide a tangible computer-readable storage medium for storing the basic programming and data structures that provide the functionality of some embodiments. Software (programs, code modules, instructions) that provide the above functionality when executed by the processor may be stored in the storage subsystem 1018. These software modules or instructions may be executed by the processing unit 1004. The storage subsystem 1018 may also provide a repository for storing data used in accordance with some embodiments.

[0081] Storage subsystem 1000 may also include a computer-readable storage medium reader 1020, which may be further connected to computer-readable storage media 1022. Together with system memory 1010, and optionally in combination with the system memory, computer-readable storage media 1022 may collectively represent remote, local, fixed, and / or removable storage elements plus storage media for temporarily and / or more permanently receiving, storing, transferring, and retrieving computer-readable information.

[0082] The computer-readable storage medium 1022 containing the code, or portions of the code, may also include any suitable media, including storage media and communication media, such as, but not limited to, volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing and / or transmitting information. This may include tangible computer-readable storage media such as RAM, ROM, electronically erasable programmable ROM (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage elements, or other tangible computer-readable media. This may also include intangible computer-readable media such as data signals, data transmissions, or any other medium that can be used to transmit the desired information and that can be accessed by the computing system 1000.

[0083] By way of example, computer readable storage media 1022 may include a hard drive that reads from or writes to non-removable, nonvolatile magnetic media, a magnetic disk drive that reads from or writes to a removable, nonvolatile magnetic disk, and a hard drive that reads from or writes to a removable, nonvolatile magnetic disk, such as a CD ROM, a DVD, and a DVD. Computer readable storage media 1022 may include, but is not limited to, a removable, non-volatile optical disk or other optical medium such as a disk or a CD-ROM drive that reads or writes to the optical disk or the optical medium. The computer readable storage medium 1022 may include a solid-state drive (SSD) based on a non-volatile memory, such as a flash memory-based solid-state drive (SSD), an enterprise flash drive, a solid-state ROM, and the like; and a volatile memory-based SSD, such as a solid-state RAM, a dynamic RAM, a static RAM, a DRAM-based SSD, a magnetoresistive RAM (MRAM) SSD, and a hybrid SSD using a combination of a DRAM-based SSD and a flash memory-based SSD. The disk drives and their associated computer-readable media may provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for the computer system 1000.

[0084] The communication subsystem 1024 provides an interface to other computer systems and networks. The communication subsystem 1024 serves as an interface for receiving data from other systems and transmitting data from the computer system 1000 to other systems. For example, the communication subsystem 1024 may allow the computer system 1000 to connect to one or more components via the Internet. In some embodiments, the communication subsystem 1024 may include a radio frequency (RF) transceiver component for accessing wireless voice and / or data networks (e.g., using cellular telephone technology, advanced data network technology (e.g., 3G, 4G, or EDGE (Enhanced Data Rates for Global Evolution)), WiFi (IEEE 802.11 family of standards), or other mobile communication technologies, or any combination thereof), a global positioning system (GPS) receiver component, and / or other components. In some embodiments, the communication subsystem 1024 may provide wired network connectivity (e.g., Ethernet) in addition to or in lieu of a wireless interface.

[0085] In some implementations, the communication subsystem 1024 may also receive incoming communications in the form of structured and / or unstructured data feeds 1026 , event streams 1028 , event updates 1030 , and the like on behalf of one or more users who may use the computer system 1000 .

[0086] By way of example, the communication subsystem 1024 may be configured to receive messages from users of a social network and / or a message such as feed, The data feed 1026 is received in real time by other communication services such as updates, web feeds such as Rich Site Summary (RSS) feeds, and / or real-time updates from one or more third-party information sources.

[0087] In addition, the communication subsystem 1024 can also be configured to receive data in the form of a continuous data stream, which can include an event stream 1028 of real-time events and / or event updates 1030. The data can be continuous or unbounded in nature and have no clear endpoint. Examples of applications that generate continuous data can include, for example, sensor data applications, financial stocks, network performance measurement tools (such as network monitoring and traffic management applications), click stream analysis tools, automobile traffic monitoring, etc.

[0088] The communication subsystem 1024 may also be configured to output structured and / or unstructured data feeds 1026 , event streams 1028 , event updates 1030 , etc. to one or more databases in computer communication with one or more streaming data sources coupled to the computer system 1000 .

[0089] Computer system 1000 can be one of various types, including a handheld portable device (e.g. cell phone, computing tablets, PDAs), wearable devices (such as Google head-mounted display), PC, workstation, mainframe, kiosk, server rack, or any other data processing system.

[0090] Due to the ever-changing nature of computers and networks, the description of the computer system 1000 depicted in the figure is intended only as a specific example. Many other configurations with more or fewer components than the system depicted in the figure are possible. For example, customized hardware can also be used and / or specific elements can be implemented with hardware, firmware, software (including applets) or a combination. Further, connections to other computing elements (such as network input / output elements) can be adopted. Based on the disclosure and teachings provided herein, other ways and / or methods of implementing various embodiments should be understood.

[0091] In the foregoing description, the term "about" can be interpreted as meaning within 10% of the stated value. For example, approximately 10.0 V can be interpreted as meaning a range between 9.0 V and 11.0 V. The term "substantially" can be interpreted as meaning at least approximately 90% of a value. For example, substantially filling an area can be interpreted as filling approximately 90% of the area.

[0092] In the foregoing description, for purposes of explanation, numerous specific details have been set forth to provide a thorough understanding of various embodiments. However, it will be appreciated that some embodiments may be practiced without some of these specific details. In other cases, well-known structures and components are shown in block diagram form.

[0093] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of various embodiments will provide a feasible disclosure for implementing at least one embodiment. It will be understood that various changes may be made to the function and arrangement of elements without departing from the spirit and scope of certain embodiments as set forth in the appended claims.

[0094] In the foregoing description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other elements may be shown as elements in block diagram form so as not to obscure the embodiments with unnecessary detail. In other cases, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail to avoid obscuring the embodiments.

[0095] Furthermore, it should be noted that individual embodiments may be described as processes, which are depicted as flow charts, data flow diagrams, structure diagrams, or block diagrams. While a flow chart may depict operations as a sequential process, many operations may be performed in parallel or in parallel. Furthermore, the order of the operations may be rearranged. When the operations of a process are completed, the process terminates, but may have additional steps not included in the diagram. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, the termination of the process may correspond to the function returning to the calling function or main function.

[0096] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage elements, optical storage elements, wireless channels, and various other media that can store, hold, or carry instructions and / or data. Code segments or machine-executable instructions can represent any combination of process, function, subroutine, program, routine, subroutine, module, software package, category, or instruction, data structure, or program statement. Code segments can be coupled to another code segment or hardware circuit by transmitting and / or receiving information, data, independent variables, parameters, or memory contents. Can be transmitted, delivered, or transmit information, independent variables, parameters, data, etc. via any suitable means including memory sharing, information transfer, token transfer, network transmission, etc.

[0097] Furthermore, embodiments may be implemented using hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented using software, firmware, middleware, or microcode, program code or code segments for performing the necessary tasks may be stored in a machine-readable medium. A processor may perform the necessary tasks.

[0098] In the foregoing description, features are described with reference to specific embodiments thereof, but it should be recognized that not all embodiments are limited thereto. Various features and aspects of some embodiments may be utilized individually or collectively. Furthermore, embodiments may be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the present specification. Accordingly, the present specification and drawings are to be regarded as illustrative rather than restrictive.

[0099] In addition, for the purpose of illustration, the method is described in a specific order. It should be understood that in an alternative embodiment, the method can be performed in a sequence different from the described order. It should also be understood that the above method can be performed by hardware components or can be implemented with a sequence of machine-executable instructions, which can be used to make a machine (such as a general-purpose or special-purpose processor or logic circuit programmed with instructions) perform the method. These machine-executable instructions can be stored on one or more machine-readable media (such as CD-ROM or other types of optical disks, floppy disks, ROM, RAM, EPROM, EEPROM, magnetic cards or optical cards, flash memory or other types of machine-readable media suitable for storing electronic instructions). Alternatively, the method can be performed by a combination of hardware and software.

Claims

1. A circuit for controlling a margin voltage of a transistor stage of an electroplating system to maintain a target power dissipation across the transistor stage, the circuit comprising: a transistor stage, wherein the transistor stage provides a broad voltage to a load in the electroplating system; a power measurement circuit coupled to the transistor stage, wherein the power measurement circuit provides a signal representative of instantaneous power dissipation in the transistor stage; a difference circuit that receives the signal representing the instantaneous power dissipation in the transistor stage and a signal representing the target power dissipation in the transistor stage from the power measurement circuit to generate a difference output; and an adjustable voltage source providing a voltage across the transistor stage and the load, wherein the adjustable voltage source is configured to use the differential output to adjust the margin voltage to maintain the target power dissipation in the transistor stage, The margin voltage in the transistor stage decreases as the current through the transistor stage increases.

2. The circuit of claim 1 , wherein the power measurement circuit further comprises: A voltage measurement circuit is coupled to the transistor stage to provide a measurement representative of the voltage across the transistor stage.

3. The circuit of claim 2 , wherein the power measurement circuit further comprises: A current measurement circuit is coupled to the transistor stage to provide a measurement representative of the current through the transistor stage.

4. The circuit of claim 3 , wherein the power measurement circuit further comprises: A multiplier circuit receives the measurement representing the voltage across the transistor stage and the measurement representing the current through the transistor stage to generate the signal representing instantaneous power dissipation in the transistor stage.

5. The circuit of claim 1 wherein the differential circuit comprises an operational amplifier that provides an output to an AC to DC converter.

6. The circuit of claim 1 further comprising a differential amplifier that receives a signal representative of a target current through the transistor stage and receives an instantaneous current through the transistor stage.

7. The circuit of claim 6, wherein the differential amplifier provides a gate voltage to the transistor stage to achieve the target current through the transistor stage.

8. The circuit of claim 1, wherein the signal representative of the instantaneous power dissipation in the transistor stage comprises a voltage proportional to the instantaneous power dissipation.

9. A method of controlling a margin voltage of a transistor stage of an electroplating system to maintain a target power dissipation across the transistor stage, the method comprising: maintaining a broad voltage in the transistor stage for a load in the electroplating system; measuring instantaneous power dissipation in the transistor stage; generating a difference output representing a difference between the instantaneous power dissipation in the transistor level and the target power dissipation in the transistor level; adjusting a voltage across the transistor stage and the load using the difference output such that the margin voltage in the transistor stage is adjusted to maintain the target power dissipation in the transistor stage; and As current through the transistor stage increases, the margin voltage in the transistor stage is decreased.

10. The method of claim 9, further comprising determining a voltage across the transistor stage.

11. The method of claim 9, further comprising determining a current through the transistor stage.

12. The method of claim 9, further comprising multiplying a signal representing a voltage across the transistor stage with a signal representing a current through the transistor stage to determine the instantaneous power dissipation in the transistor stage.

13. The method of claim 9, further comprising scaling down a signal representative of the instantaneous power dissipation in the transistor stage.

14. The method of claim 9, producing a transition of the voltage across the transistor stage and the load having a fall time of less than 10 ms.

15. A circuit for controlling a margin voltage of a transistor stage to maintain a target power dissipation across the transistor stage, the circuit comprising: a transistor stage, wherein the transistor stage provides a wide voltage for a load; a power measurement circuit coupled to the transistor stage, wherein the power measurement circuit provides a signal representative of instantaneous power dissipation in the transistor stage; and an adjustable voltage source providing a voltage across the transistor stage and a load, wherein the adjustable voltage source is configured to adjust the margin voltage in the transistor stage in response to the transient power dissipation in the transistor stage to maintain the target power dissipation in the transistor stage, The margin voltage in the transistor stage decreases as the current through the transistor stage increases.

16. The circuit of claim 15, wherein the target power dissipation is represented by a plurality of series resistors forming a voltage divider.

17. The circuit of claim 15, wherein the adjustable voltage source comprises an AC to DC power converter.

18. The circuit of claim 15, wherein the power measurement circuit is implemented using a microprocessor or a microcontroller.

19. The circuit of claim 15, further comprising a serial interface that receives a serial command from a controller and converts the serial command into a plurality of analog and digital signals to control the circuit for controlling the margin voltage of the transistor stage.

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