Dynamic scheduling method and system for physical memory protection mechanism under RISC-V architecture
By using the LRU algorithm in the RISC-V architecture to dynamically schedule memory access permissions, the problem of the limited number of PMP registers is solved, achieving more efficient memory access permission management and improving application running efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI TRUSTKERNEL INFORMATION TECH CO LTD
- Filing Date
- 2023-01-05
- Publication Date
- 2026-06-26
Smart Images
Figure CN115964312B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and more specifically, to a dynamic scheduling method and system for physical memory protection mechanisms under the RISC-V architecture. Background Technology
[0002] RISC-V is an open-source instruction set architecture (ISA) based on the principles of reduced instruction set computing. The RISC-V architecture provides three privileged modes: Machine (M), Supervisor (S), and User (U). Machine mode can access all memory addresses. To restrict untrusted applications to access only their own memory regions, RISC-V provides Physical Memory Protection (PMP).
[0003] The configuration of a PMP (Programmable Memory Manager) relies on two types of registers: the configuration register pmpcfg and the address register pmpaddr. One configuration register and one address register constitute a PMP entry. The configuration register stores information such as memory access permissions (read / write / execute), address calculation method, and whether the entry is locked (updates to a locked entry will not take effect). The address register stores the memory address range controlled by this PMP entry. The RISC-V architecture itself provides a limited number of PMP configuration and address registers (typically 8-16). To overcome this limitation and allow an application to allocate a larger number of memory regions, this invention proposes a dynamic scheduling method based on a physical memory protection mechanism. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention provides a dynamic scheduling method and system for physical memory protection mechanisms under the RISC-V architecture.
[0005] According to the present invention, a dynamic scheduling method and system for physical memory protection mechanism under RISC-V architecture is provided, the scheme of which is as follows:
[0006] Firstly, a dynamic scheduling method for physical memory protection mechanisms under the RISC-V architecture is provided, the method comprising:
[0007] Step S1: Access application memory supported by dynamic scheduling under the physical memory protection mechanism;
[0008] Step S2: Maintain the currently active application memory access permission configuration using the LRU algorithm.
[0009] Preferably, step S1 includes:
[0010] Step S1.1: Traverse and save the application memory access permission configurations through the security monitor to check if the configuration contains a memory access permission configuration that includes address A;
[0011] Step S1.2: Assume that the application memory access permission configuration contains a configuration that includes address A. Calculate the maximum range that satisfies the set conditions and covers address A within the entire memory region of the application configuration, and create a configuration R corresponding to this range. Insert R into the LRU cache.
[0012] Step S1.3: Recalculate the PMP entries based on the configuration in the LRU cache, and update the PMP configuration by modifying the control and status registers;
[0013] Step S1.4: Move the machine mode exception program counter to the location where the application accessed the error, and the application accesses address A again and gets the correct access result.
[0014] Preferably, in step S1.1, the system checks whether the configuration contains a memory access permission configuration for address A. If it is not found, it indicates that the application's access to address A is illegal, and an error message is printed to prompt the user and the execution of the application is terminated.
[0015] Preferably, step S2 includes:
[0016] Step S2.1: When the application is loaded for the first time, the maximum number of PMP configurations supported by the current architecture is set to N1, and the initialization of the LRU cache is handled according to different situations;
[0017] Step S2.2: For regions with overlapping memory, the LRU cache order needs to be adjusted according to execution permissions, with regions having higher execution permissions placed in a relatively earlier position;
[0018] Step S2.3: Let the address where the access error occurred be A. The security monitor calculates a maximum range that includes address A based on the application's configuration. Let the obtained configuration be R.
[0019] Step S2.4: Search for the last configuration without execution permission from the tail of the LRU cache. If all nodes have execution permission, select the configuration at the tail of the cache, delete the selected configuration, and insert the new configuration R into the cache.
[0020] Step S2.5: If the configuration R region obtained in step S2.3 overlaps with other configurations in the LRU cache set to R1 and has different permissions, then the configuration node with higher permissions needs to be placed in a relatively earlier position.
[0021] Step S2.6: Write the configurations saved in the LRU cache into the PMP registers in sequence.
[0022] Preferably, assuming the number of PMP entries in the application configuration is M, the initialization of the LRU cache in step S2.1 includes the following two different cases:
[0023] 1) If M < N1, insert the regions with execution permissions into the LRU cache in sequence, and then insert the first N1 - M entries of other regions into the LRU cache;
[0024] 2) If M >= N1, insert the first N1 entries of the regions with execution permissions into the LRU cache.
[0025] In a second aspect, a dynamic scheduling system for a physical memory protection mechanism under the RISC-V architecture is provided. The system includes:
[0026] Module M1: Access the application memory supported by the dynamic scheduling of the physical memory protection mechanism;
[0027] Module M2: Use the LRU algorithm to maintain the currently effective application memory access permission configuration.
[0028] Preferably, the module M1 includes:
[0029] Module M1.1: Traverse and save the application memory access permission configuration through the security monitor to find whether there is a memory access permission configuration containing the address A in the configuration;
[0030] Module M1.2: Assuming there is a configuration containing the address A in the application memory access permission configuration, calculate a maximum range that meets the set conditions and covers the address A within the entire range of the memory area of the application configuration, and create a configuration R corresponding to this range, and insert R into the LRU cache;
[0031] Module M1.3: Recalculate the PMP entries according to the configuration in the LRU cache, and update the PMP configuration by modifying the control and status registers;
[0032] Module M1.4: Move the machine mode exception program counter to the position where the application access error occurs, and the application accesses the address A again and gets the correct access result.
[0033] Preferably, if it is not found in module M1.1 whether there is a memory access permission configuration containing the address A, it means that the application's access to the address A is illegal, print an error message to prompt the user and end the execution of the application.
[0034] Preferably, the module M2 includes:
[0035] Module M2.1: When the application is first loaded, set the maximum number of PMP configurations supported by the current architecture to N1, and the initialization of the LRU cache is processed according to different situations;
[0036] Module M2.2: For memory overlapping regions, the LRU cache order needs to be adjusted according to the execution permissions, and the region with higher execution permissions is placed relatively in the front;
[0037] Module M2.3: Let the address where the access error occurs be A, and the security monitor calculates a maximum range containing the address A according to the application configuration, and let the obtained configuration be R;
[0038] Module M2.4: Search for the last configuration without execution permission from the tail of the LRU cache. If all nodes have execution permissions, select the configuration at the tail of the cache, delete the selected configuration, and insert the new configuration R into the cache;
[0039] Module M2.5: If the configuration R region obtained by Module M2.3 overlaps with other configurations R1 in the LRU cache and has different permissions, then the configuration node with higher permissions needs to be placed relatively in the front;
[0040] Module M2.6: Write the configurations saved in the LRU cache into the PMP registers in sequence.
[0041] Preferably, assume that the number of PMP entries in the application configuration is M, and the initialization of the LRU cache in Module M2.1 includes the following two different situations:
[0042] 1) If M < N1, insert the regions with execution permissions into the LRU cache in sequence, and then insert the first N1 - M items of other regions into the LRU cache;
[0043] 2) If M >= N1, insert the first N1 items of the regions with execution permissions into the LRU cache.
[0044] Compared with the prior art, the present invention has the following beneficial effects:
[0045] 1. The present invention uses a dynamic scheduling method to maintain the application's access permissions to memory, which can break through the limitation of the number of registers and configure more memory access regions for a single application;
[0046] 2. The present invention uses the Least Recently Used (LRU) algorithm to maintain the memory regions accessible by a single application. The memory regions with execution permissions have higher priorities, and when the cache is updated, the regions without execution permissions are preferentially replaced, which can greatly reduce the probability of updating the PMP configuration and improve the operation efficiency of the application.
[0047] Other beneficial effects of the present invention will be explained in detail through the introduction of specific technical features and technical solutions in specific embodiments. Those skilled in the art should be able to understand the beneficial technical effects brought about by these technical features and technical solutions through the introduction of these technical features and technical solutions. Attached Figure Description
[0048] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0049] Figure 1 This refers to the application memory access process supported by dynamic scheduling under the physical memory protection mechanism.
[0050] Figure 2 Design architecture for trusted execution environments;
[0051] Figure 3 For the pmpcfg register of RV32;
[0052] Figure 4 For the pmpcfg register of RV64;
[0053] Figure 5 For the pmpaddr register of RV32;
[0054] Figure 6 For the pmpaddr register of RV64;
[0055] Figure 7 It is a pmpcfg register structure. Detailed Implementation
[0056] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.
[0057] This invention provides a dynamic scheduling method for physical memory protection mechanisms under the RISC-V architecture, referring to... Figure 1 As shown, the method specifically includes:
[0058] Step S1: Access application memory supported by dynamic scheduling under the physical memory protection mechanism.
[0059] Step S1 includes:
[0060] Step S1.1: The security monitor traverses and saves the application memory access permission configuration to find out if there is a memory access permission configuration containing address A in the configuration. If not found, it means that the application's access to address A is illegal. Print an error message to prompt the user and end the execution of the application.
[0061] Step S1.2: Suppose there is a configuration containing address A in the application memory access permission configuration. Calculate a maximum range that meets the set conditions and covers address A within the entire range of the memory area configured by the application, and create a configuration R corresponding to this range. Insert R into the LRU cache.
[0062] Step S1.3: Recalculate the PMP table entries according to the configuration in the LRU cache, and update the PMP configuration by modifying the control and status registers.
[0063] Step S1.4: Move the machine mode exception program counter to the position where the application access error occurred. The application accesses address A again and gets the correct access result.
[0064] Step S2: Use the LRU algorithm to maintain the currently effective application memory access permission configuration.
[0065] This step S2 includes:
[0066] Step S2.1: When the application is first loaded, suppose the maximum number of PMP configurations supported by the current architecture is N1, and the number of PMP table entries in the application configuration is M. The initialization of the LRU cache includes the following two different situations:
[0067] 1) If M < N1, insert the areas with execution permission into the LRU cache in sequence, and then insert the first N1 - M items of other areas into the LRU cache.
[0068] 2) If M >= N1, insert the first N1 items of the areas with execution permission into the LRU cache.
[0069] Step S2.2: For overlapping memory areas, adjust the LRU cache order according to the execution permission, and place the areas with higher execution permission in relatively front positions.
[0070] Step S2.3: Suppose the address where the access error occurred is A. The security monitor calculates a maximum range containing address A according to the application's configuration, and suppose the obtained configuration is R.
[0071] Step S2.4: Search for the last configuration without execution permission from the tail of the LRU cache. If all nodes have execution permission, select the configuration at the tail of the cache, delete the selected configuration, and insert the new configuration R into the cache.
[0072] Step S2.5: If the configuration R region obtained in step S2.3 overlaps with other configurations in the LRU cache set to R1 and has different permissions, then the configuration node with higher permissions needs to be placed in a relatively earlier position.
[0073] Step S2.6: Write the configurations stored in the LRU cache into the PMP registers in sequence.
[0074] This invention also provides a dynamic scheduling system for a physical memory protection mechanism under a RISC-V architecture. This dynamic scheduling system can be implemented by executing the steps of the dynamic scheduling method for the physical memory protection mechanism under the RISC-V architecture. That is, those skilled in the art can understand the dynamic scheduling method for the physical memory protection mechanism under the RISC-V architecture as a preferred embodiment of the dynamic scheduling system for the physical memory protection mechanism under the RISC-V architecture. The system specifically includes the following:
[0075] Module M1: Accesses application memory supported by dynamic scheduling under physical memory protection mechanisms.
[0076] Module M1 includes:
[0077] Module M1.1: Iterates through the saved application memory access permission configurations via the security monitor, checks if the configuration contains a memory access permission configuration for address A. If not found, it means that the application's access to address A is illegal, prints an error message to prompt the user, and terminates the execution of the application.
[0078] Module M1.2: Suppose that the application memory access permission configuration contains a configuration that includes address A. Calculate the maximum range that meets the set conditions and covers address A within the entire memory region of the application configuration, and create a configuration R corresponding to this range. Insert R into the LRU cache.
[0079] Module M1.3: Recalculates PMP entries based on the configuration in the LRU cache, and updates the PMP configuration by modifying the control and status registers;
[0080] Module M1.4: Moves the machine mode exception program counter to the location where the application accessed the error, so that the application can access address A again and get the correct access result.
[0081] Module M2: Maintains the memory access permission configurations for currently active applications using the LRU algorithm.
[0082] Module M2 includes:
[0083] Module M2.1: When the application is first loaded, assume that the maximum number of PMP configurations supported by the current architecture is N1, and the number of PMP entries in the application configuration is M. The initialization of the LRU cache includes the following two different cases:
[0084] 1) If M < N1, insert the regions with execution permissions into the LRU cache in sequence, and then insert the first N1 - M items of other regions into the LRU cache;
[0085] 2) If M >= N1, insert the first N1 items of the regions with execution permissions into the LRU cache.
[0086] Module M2.2: For memory - overlapping regions, the LRU cache order needs to be adjusted according to the execution permissions, and the region with higher execution permissions is placed in a relatively forward position;
[0087] Module M2.3: Let the address where access error occurs be A, and the security monitor calculates a maximum range containing address A according to the application configuration, and assume the obtained configuration is R;
[0088] Module M2.4: Search for the last configuration without execution permission from the tail of the LRU cache. If all nodes have execution permissions, select the configuration at the tail of the cache, delete the selected configuration, and insert the new configuration R into the cache;
[0089] Module M2.5: If the configuration R region obtained by module M2.3 and other configurations in the LRU cache are set as R1, have an overlapping part and different permissions, then the configuration node with higher permissions needs to be placed in a relatively forward position;
[0090] Module M2.6: Write the configurations saved in the LRU cache into the PMP registers in sequence.
[0091] Next, a more specific description of the present invention will be given.
[0092] 1. Dynamic maintenance of the memory access permissions of applications in the RISC - V architecture trusted execution environment:
[0093] In the RISC - V architecture, the isolation property of the trusted execution environment needs to be implemented through the physical memory protection mechanism. A general trusted execution environment design includes the following components, as Figure 2 shown:
[0094] 1) The security monitor running in machine mode;
[0095] 2) The ordinary application running in user mode;
[0096] Physical memory protection mechanisms define whether applications in supervisory and user modes can read, write, or execute data or instructions within a specified range of physical memory. The behavior of physical memory protection mechanisms is affected by the configuration of the associated PMP hardware registers, which can only be modified in machine mode.
[0097] The security monitor constructs different isolation zones by configuring relevant hardware registers for the physical memory isolation mechanism, thereby isolating physical memory between ordinary applications in user mode. Once an application running in user mode attempts to access a physical memory region outside its accessible range, the system will trigger an exception, fall into machine mode, and jump to the entry point specified by the security monitor.
[0098] When an application in user mode performs memory access, the following two situations may occur:
[0099] (1) This address is within the scope of the memory access permission configuration that has been implemented, and the application can get the correct result when accessing it;
[0100] (2) This address is not within the scope of the memory access permission configuration that has been activated, which will trigger an access error and cause the user to fall into machine mode.
[0101] Regarding the second scenario above, assuming the application accesses memory address A, the security monitor will determine the application's access permissions to address A and take corresponding actions, such as... Figure 1 As shown, the steps are as follows:
[0102] 1) The security monitor first iterates through the saved application memory access permission configurations and checks whether there is a memory access permission configuration containing address A. If not found, it means that the application's access to address A is illegal. An error message is printed to prompt the user and the execution of the application is terminated.
[0103] 2) Assuming the application's memory access permission configuration includes address A, the RISC-V architecture has the following requirements regarding the address range of PMP table entries:
[0104] a. The starting address and length must be integer powers of 2;
[0105] b. The starting address must be divisible by the length;
[0106] Calculate the maximum range that satisfies the above conditions and covers address A within the entire memory region configured in the application. Create a configuration R corresponding to this range and insert R into the LRU cache (Note: For specific insertion methods, see the section on using LRU to maintain the application's memory access permission configuration later).
[0107] 3) Recalculate the PMP entries (i.e., pmpcfg and pmpaddr) based on the configuration in the LRU cache, and update the PMP configuration by modifying the Control and Status Register (CSR).
[0108] 4) Move the Machine Exception Program Counter (mepc) to the location where the application encountered an error, and the application accesses address A again and gets the correct access result.
[0109] 2. Use LRU to maintain application memory access permission configuration:
[0110] Memory access permission configuration records an application's access permissions to a specific memory region. It stores the starting address, length, and application permissions (read / write / execute) for that region. Assuming the current RISC-V architecture supports a maximum of N PMP entries, when an application is loaded, because the application's configured memory regions may not conform to the RISC-V specification, the regions need to be split. Assuming the number of split regions is M, the following three scenarios may occur:
[0111] (1) When the application is loaded for the first time and M is less than N: the security monitor will insert all memory access permission configurations of the application into the LRU cache (this case will not trigger dynamic maintenance of memory access permissions);
[0112] (2) When the application is loaded for the first time and M is greater than N: the security monitor will store part of the application's memory access permission configuration in the LRU cache, and the cache size is N;
[0113] (3) The application has been loaded before and the memory configuration of the application has been recorded in the security monitor: the security monitor will use the configuration in the LRU cache.
[0114] When M is greater than N, the application may trigger dynamic scheduling of the physical memory protection mechanism during execution. Reallocating memory access permissions for the application means needing to sink into machine mode, which is more time-consuming. To improve application performance and reduce the number of sinks, this invention uses the LRU algorithm to maintain the currently effective memory access permission configuration. When the memory access frequency is unavailable, and under the premise that "memory regions with access permissions have a higher access frequency," this invention proposes the following dynamic maintenance method for memory access permission configuration:
[0115] 1) When the application is first loaded, assuming the current architecture supports a maximum of N1 PMP configurations, the LRU cache initialization falls into the following two categories:
[0116] a. If M < N1, the regions with execution permission are inserted into the LRU cache in sequence, and then the first N1 - M items of the other (regions without execution permission) are inserted into the LRU cache.
[0117] b. If M >= N1, the first N1 items of the regions with execution permission are inserted into the LRU cache.
[0118] 2) Since the pmpaddr register has priority, and the priority decreases from pmpaddr0 to pmpaddr16, for the overlapping memory regions, the LRU cache order needs to be adjusted according to the execution permission, and the region with higher execution permission is placed in a relatively forward position;
[0119] 3) Assume the address where access error occurs is A, and the security monitor calculates a maximum range containing address A according to the application's configuration. Assume the obtained configuration is R;
[0120] 4) Search from the tail of the LRU cache for the last configuration without execution permission. If all nodes have execution permission, select the configuration at the tail of the cache, delete the selected configuration, and insert the new configuration R into the cache;
[0121] 5) If the region of the configuration R obtained in step 3) overlaps with other configurations (assumed as R1) in the LRU cache and the permissions are different, the configuration node with higher permission needs to be placed in a relatively forward position;
[0122] 6) Write the configurations saved in the LRU cache into the PMP registers in sequence.
[0123] Among them, the calculation method of the PMP entry:
[0124] In the RISC - V architecture, the memory access permissions of applications in non - machine mode are determined by two types of registers, pmpcfg and pmpaddr. Among them, there are usually 8 - 16 pmpaddr, and the length is architecture - related (32 - bit for RV32 and 64 - bit for RV64). There are 16 pmpcfg registers with a length of 8 bits. RISC - V usually combines several pmpcfg into one register, such as Figure 3 and Figure 4 shown:
[0125] The structures of the pmpaddr registers of RV32 and RV64 are as Figure 5 and Figure 6As shown (WARL, Write Any Values, Reads Legal Values, indicating that any value can be written to the register, but reading will return the last written legal value). In the RISC-V design's Sv32 paged virtual memory mode, the RV32 has a 34-bit physical address space. Therefore, for the RV32, the PMP must support 34-bit physical memory access management. Thus, bits 33 to 22 of the address data are stored in the 32-bit address register, while for the RV64, bits 55 to 22 are stored. The structure of the pmpcfg register is as follows... Figure 7 As shown.
[0126] The meanings of each digit are as follows:
[0127] R (bit 0): Whether it is readable;
[0128] W (1 bit): Whether it is writable;
[0129] X (2 bits): Whether it is executable;
[0130] A (3-4 bits): The address calculation method, which may have the following four values:
[0131] 0: This entry is not enabled and does not match any address;
[0132] 1: Assume the address matched by the previous entry is pmpaddr i-1 (If the previous item does not exist, the value is 0), the address value of this item is pmpaddr i Then it matches any address that satisfies the following condition: pmpaddr i-1 <=y <pmpaddr i .
[0133] 2: Assuming the address value is pmpaddr, then match the 4 bytes starting from pmpaddr;
[0134] 3: This configuration can be viewed as y...y01...1, where the first segment has any value, and the second segment consists of consecutive 1s. Assuming the last segment contains n consecutive 1s, this configuration matches 2s starting from y...y00...0. n+3 8 bytes, meaning the minimum is 8 bytes;
[0135] 0 (5-6 digits): Reserved, currently not used;
[0136] L (7 bits): Whether the PMP entry is locked. If locked, updates to pmpcfg and pmpaddr will be ignored.
[0137] This invention provides a dynamic scheduling method and system for physical memory protection mechanisms under the RISC-V architecture. It uses dynamic scheduling to maintain application access permissions to memory, which can overcome the limitation of the number of registers and configure more memory access areas for a single application. It uses the Least Recently Used (LRU) algorithm to maintain the memory areas accessible to a single application (updating the LRU data structure requires processing based on the specific permissions of the memory access areas). Memory areas with execution permissions have higher priority, and areas without execution permissions are replaced first when the cache is updated.
[0138] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.
[0139] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.
Claims
1. A dynamic scheduling method for physical memory protection mechanisms under a RISC-V architecture, characterized in that, including: Step S1: Access the application memory supported by the dynamic scheduling of the physical memory protection mechanism; Step S2: Use the LRU algorithm to maintain the currently effective application memory access permission configuration; The said Step S1 includes: Step S1.1: Traverse and save the application memory access permission configuration through the security monitor, and check whether the configuration contains the memory access permission configuration including address A; Step S1.2: Suppose there is a configuration including address A in the application memory access permission configuration. Calculate a maximum range that meets the set conditions and covers address A within the entire range of the memory area configured by the application, and create a configuration R corresponding to this range. Insert R into the LRU cache; Step S1.3: Recalculate the PMP table entries according to the configuration in the LRU cache, and at the same time update the PMP configuration by modifying the control and status registers; Step S1.4: Move the machine mode exception program counter to the position where the application access error occurs. The application accesses address A again and gets the correct access result; The said Step S2 includes: Step S2.1: When the application is first loaded, suppose the maximum number of PMP configurations supported by the current architecture is N1, and the initialization of the LRU cache is processed according to different situations; Step S2.2: For the overlapping memory areas, the LRU cache order needs to be adjusted according to the execution permissions. The areas with higher execution permissions are placed in relatively front positions; Step S2.3: Suppose the accessed error address is A. The security monitor calculates a maximum range including address A according to the application configuration, and suppose the obtained configuration is R; Step S2.4: Search for the last configuration without execution permission from the tail of the LRU cache. If all nodes have execution permissions, select the configuration at the tail of the cache, delete the selected configuration, and insert the new configuration R into the cache; Step S2.5: If the configuration R area obtained in Step S2.3 and other configurations in the LRU cache are set as R1, have an overlapping part and different permissions, then the configuration node with higher permissions needs to be placed in a relatively front position; Step S2.6: Write the configurations saved in the LRU cache into the PMP registers in sequence; Suppose the number of PMP table entries in the application configuration is M. The initialization of the LRU cache in the said Step S2.1 includes the following two different situations: 1) If M < N1, insert the areas with execution permissions into the LRU cache in sequence, and then insert the first N1 - M items of other areas into the LRU cache; 2) If M >= N1, insert the first N1 items of the areas with execution permissions into the LRU cache.
2. The dynamic scheduling method for physical memory protection mechanism under RISC-V architecture according to claim 1, characterized in that, In the said Step S1.1, check whether the configuration contains the memory access permission configuration including address A. If not found, it means that the application's access to address A is illegal. Print an error message to prompt the user and end the execution of the application.
3. A dynamic scheduling system with a physical memory protection mechanism under a RISC-V architecture, characterized in that, including: Module M1: Access the application memory supported by the dynamic scheduling of the physical memory protection mechanism; Module M2: Use the LRU algorithm to maintain the currently effective application memory access permission configuration; The said Module M1 includes: Module M1.1: Traverse and save the application memory access permission configuration through the security monitor, and check whether the configuration contains the memory access permission configuration including address A; Module M1.2: Assume that the application memory access permission configuration contains the configuration including address A. Calculate a maximum range that meets the set conditions and covers address A within the entire range of the memory area configured by the application, and create a configuration R corresponding to this range. Insert R into the LRU cache; Module M1.3: Recalculate the PMP table entries according to the configuration in the LRU cache, and at the same time update the PMP configuration by modifying the control and status registers; Module M1.4: Move the machine mode exception program counter to the position where the application access error occurs, and the application accesses address A again and obtains the correct access result; The module M2 includes: Module M2.1: When the application is first loaded, assume that the maximum number of PMP configurations supported by the current architecture is N1, and the initialization of the LRU cache is processed according to different situations; Module M2.2: For the overlapping memory areas, the order of the LRU cache needs to be adjusted according to the execution permissions, and the area with higher execution permissions is placed in a relatively forward position; Module M2.3: Assume that the address where the access error occurs is A, and the security monitor calculates a maximum range including address A according to the application configuration, and assume that the obtained configuration is R; Module M2.4: Search for the last configuration without execution permission from the tail of the LRU cache. If all nodes have execution permissions, select the configuration at the tail of the cache, delete the selected configuration, and insert the new configuration R into the cache; Module M2.5: If the configuration R area obtained by module M2.3 overlaps with other configurations (set as R1) in the LRU cache and has different permissions, then the configuration node with higher permissions needs to be placed in a relatively forward position; Module M2.6: Write the configurations saved in the LRU cache into the PMP registers in sequence; Assume that the number of PMP table entries in the application configuration is M. The initialization of the LRU cache in module M2.1 includes the following two different situations: 1) If M < N1, insert the areas with execution permissions into the LRU cache in sequence, and then insert the first N1 - M items of other areas into the LRU cache; 2) If M >= N1, insert the first N1 items of the areas with execution permissions into the LRU cache.
4. The dynamic scheduling system for physical memory protection mechanism under RISC-V architecture according to claim 3, characterized in that, In module M1.1, check whether the configuration contains the memory access permission configuration including address A. If not found, it means that the application's access to address A is illegal. Print an error message to prompt the user and end the execution of the application.