Automatically controlled input data buffer circuit

Abstract

The present invention discloses a self-controlled input data buffer circuit, comprising a first amplifier, a second amplifier, a feedback signal generator, and a gain control unit. The first amplifier comprises a first input terminal for receiving a data signal, a second input terminal for receiving a reference signal, a first output terminal, and a second output terminal. The second amplifier is coupled to the first output terminal of the first amplifier and the second output terminal of the first amplifier. The feedback signal generator is coupled to the second amplifier. The gain control unit is coupled to the feedback signal generator, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the second input terminal of the first amplifier.

Description

Technical Field

[0001] The present invention relates to a self-controlled input data buffer circuit, in particular to a self-controlled input data buffer circuit which automatically controls the system gain by utilizing a gain control unit. Background Art

[0002] With the rapid advancement of technology, various volatile and non-volatile memory types have been incorporated into computer systems. Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that falls under the volatile category. Its primary function is to use the amount of charge stored in a capacitor to represent a binary bit as a 1 or 0. DRAM is a short-term data storage area in a computer system, storing information currently in use for quick access.

[0003] DRAM can provide high-speed transmission and high bandwidth utilization. However, due to the high speed and high bandwidth utilization required of DRAM, its power consumption also increases. Therefore, developing an automatic gain control method to optimize power consumption is an important design issue. Summary of the Invention

[0004] An embodiment of the present invention provides an automatic input data buffer circuit. The automatic input data buffer circuit includes a first amplifier, a second amplifier, a feedback signal generator, and a gain control unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference signal, a first output terminal, and a second output terminal. The second amplifier is coupled to the first output terminal of the first amplifier and the second output terminal of the first amplifier. The feedback signal generator is coupled to the second amplifier. The gain control unit is coupled to the feedback signal generator, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the second input terminal of the first amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of an embodiment of the self-controlled input data buffer circuit of the present invention.

[0006] Figure 2 yes Figure 1 Schematic diagram of the first amplifier in the self-controlled input data buffer circuit.

[0007] Figure 3 yes Figure 1 FIG. 4 is a diagram showing the architecture of the second amplifier in the self-controlled input data buffer circuit.

[0008] Figure 4 yes Figure 1 Schematic diagram of the feedback signal generator in the automatic input data buffer circuit.

[0009] Figure 5 yes Figure 1 Schematic diagram of the gain control unit in the self-controlled input data buffer circuit.

[0010] The description of the accompanying drawings is as follows:

[0011] 100 Automatically controlled input data buffer circuit

[0012] 10 First Amplifier

[0013] 11 Second amplifier

[0014] 12 Feedback signal generator

[0015] 13 Gain Control Unit

[0016] POUTB First output signal

[0017] POUT second output signal

[0018] DIP data signal

[0019] DIN reference signal

[0020] PT third output signal

[0021] PB fourth output signal

[0022] P_FB feedback signal

[0023] V DD Operating voltage

[0024] BIAS bias signal

[0025] HF_EN start signal

[0026] T1 first transistor

[0027] T2 second transistor

[0028] T3 third transistor

[0029] T4 fourth transistor

[0030] T5 fifth transistor

[0031] T6 Sixth transistor

[0032] T7 seventh transistor

[0033] T8 eighth transistor

[0034] T9 Ninth transistor

[0035] INV1 first inverter DETAILED DESCRIPTION

[0036] Figure 1 This is a block diagram of an embodiment of an automatic input data buffer circuit 100 of the present invention. The automatic input data buffer circuit 100 automatically adjusts system gain based on the input data signal. This optimizes current consumption and automatically controls its gain. The automatic input data buffer circuit 100 is described below. The automatic input data buffer circuit 100 includes a first amplifier 10, a second amplifier 11, a feedback signal generator 12, and a gain control unit 13. The first amplifier 10 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is used to receive a data signal DIP. The second input terminal is used to receive a reference signal DIN. The second amplifier 11 is coupled to the first output terminal and the second output terminal of the first amplifier 10. The feedback signal generator 12 is coupled to the second amplifier 11. The gain control unit 13 is coupled to the feedback signal generator 12, the first output terminal and the second output terminal of the first amplifier 10, and the second input terminal of the first amplifier 10. In the architecture of the automatic input data buffer circuit 100, a first amplifier 10, a second amplifier 11, a feedback signal generator 12, and a gain control unit 13 form a circuit loop capable of automatically controlling its gain. For example, after amplification by the first and second amplifiers 10 and 11, the data signal DIP is input to the feedback signal generator 12 to generate the feedback signal P_FB. After receiving the feedback signal P_FB, the gain control unit 13 uses the two outputs (POUT and POUTB) of the first amplifier 11 to adjust the gain. The two outputs (POUT and POUTB) of the first amplifier 11 are related to the data signal DIP. In other words, because the gain control unit 13 can adjust the gain based on the data signal DIP, it can optimize energy consumption. The circuit details of the automatic input data buffer circuit 100 will be described in detail below.

[0037] Figure 2 FIG. 1 is a structural diagram of the first amplifier 10 in the self-controlled input data buffer circuit 100 . Figure 3 yes Figure 1 The first amplifier 10 and the second amplifier 11 of the self-controlled input data buffer circuit 100 are not limited by the circuit of the amplifier. For example, the first amplifier 10 and the second amplifier 11 can be a voltage amplifier, a current amplifier or a differential amplifier. Figure 2In the embodiment, the first amplifier 10 may be a differential amplifier. The first amplifier 10 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The first transistor T1 includes a transistor for receiving an operating voltage V DD The second transistor T2 includes a first terminal, a second terminal and a control terminal for receiving the working voltage V DD The first and second transistors T1 and T2 may be P-type metal-oxide-semiconductor field-effect transistors (P-type metal-oxide-semiconductor field-effect transistors (P-type metal-oxide-semiconductor field-effect transistors (P-type metal-oxide-semiconductor field-effect transistors (P-type metal-oxide-semiconductor field-effect transistors (N ... For example, when the fifth transistor T5 is an N-type metal oxide semiconductor field effect transistor, the voltage of the bias signal BIAS will affect the conduction state of the fifth transistor T5, so the current of the first amplifier 10 passing through the fifth transistor T5 can also be controlled by the bias signal BIAS. In addition, when the third transistor T3 and the fourth transistor T4 are in the linear region, and the first transistor T1 and the second transistor T2 are turned on, the two outputs of the first amplifier 10, namely the first output signal POUTB and the second output signal POUT will also be linearly amplified according to the data signal DIP and the reference signal DIN. It should be understood that the first output signal POUTB is located at the first end of the third transistor T3, and the second output signal POUT is located at the first end of the fourth transistor T4. In addition, the first output signal POUTB and the second output signal POUT are opposite to each other. Figure 3In the embodiment, the second amplifier 11 can also be a differential amplifier, whose inputs are the first output signal POUTB and the second output signal POUT, which are inversely proportional to each other. The second amplifier 11 includes a first input terminal coupled to the first output terminal of the first amplifier 10, a second input terminal coupled to the second output terminal of the first amplifier 10, a first output terminal coupled to the feedback signal generator 12, and a second output terminal. Therefore, after the first output signal POUTB and the second output signal POUT are operated by the second amplifier 11, they are amplified into a third output signal PT and a fourth output signal PB, respectively. The third output signal PT is output from the first output terminal. The fourth output signal PB is output from the second output terminal. Furthermore, the third output signal PT and the fourth output signal PB can be inversely proportional to each other.

[0038] Figure 4 1 is a schematic diagram of the feedback signal generator 12 in the self-controlled input data buffer circuit 100. The feedback signal generator 12 includes a plurality of first inverters INV1 connected in series. The plurality of first inverters INV1 connected in series are used to delay the signal at the first output end of the second amplifier 11 to output the feedback signal P_FB. In other words, the third output signal PT output by the second amplifier 11 can be delayed by the feedback signal generator 12 to generate the feedback signal P_FB. Figure 4 There is no limit to the number of inverters in the feedback signal generator 12. Moreover, since each inverter has its own time delay, the more inverters there are in the feedback signal generator 12, the greater the time delay will be.

[0039] Figure 51 is a block diagram of the gain control unit 13 in the self-controlled input data buffer circuit 100. The gain control unit 13 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The sixth transistor T6 is coupled to a first terminal (receiving the first output signal POUTB) and a second terminal of the first output terminal of the first amplifier 10, and a control terminal coupled to the feedback signal generator 12 for receiving the feedback signal P_FB. The seventh transistor T7 includes a first terminal coupled to the second output terminal of the first amplifier 10 (receiving the second output signal POUT), a second terminal coupled to the second terminal of the sixth transistor T6, and a control terminal for receiving the reference signal DIN. The eighth transistor T8 includes a first terminal coupled to the second terminal of the seventh transistor T7, a second terminal, and a control terminal for receiving the bias signal BIAS. The bias signal BIAS can be a user-defined or preset voltage value and is used to control the conduction state of the eighth transistor T8. The ninth transistor T9 includes a first terminal coupled to the second terminal of the eighth transistor T8, a second terminal coupled to ground, and a control terminal for receiving an enable signal HF_EN. In the gain control unit 13, when the eighth transistor T8 is an N-type metal-oxide-semiconductor field-effect transistor, the voltage of the bias signal BIAS affects the conduction state of the eighth transistor T8. Therefore, the current flowing through the eighth transistor T8 in the gain control unit 13 can also be controlled by the bias signal BIAS. In the gain control unit 13, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are N-type metal-oxide-semiconductor field-effect transistors. The enable signal HF_EN can be considered a switching signal for the gain control unit 13. For example, if the enable signal HF_EN is low, the ninth transistor T9 is turned off, and no current flows through the ninth transistor T9. Therefore, the gain control unit 13 does not adjust the voltage gain and is turned off. If the enable signal HF_EN is high, the ninth transistor T9 is turned on. The gain control unit 13 can adjust the voltage gain of the gain control unit 13 according to the bias signal BIAS, the reference signal DIN, and the feedback signal P_FB. Similar to the above, since the reference signal DIN is received by the control terminal of the seventh transistor T7, the cross voltage between the reference signal DIN and the second output signal POUT can control the conduction state of the seventh transistor T7. Similarly, since the feedback signal P_FB is received by the control terminal of the sixth transistor T6, the cross voltage between the feedback signal P_FB and the first output signal POUTB can control the conduction state of the sixth transistor T6. For example, when the seventh transistor T6 and the seventh transistor T7 are turned on, since the voltages of the first output signal POUTB and the second output signal POUT are opposite, a current will be generated between the first output signal POUTB and the second output signal POUT.Furthermore, because the voltage of the bias signal BIAS affects the conduction state of the eighth transistor T8, a portion of the current between the first output signal POUTB and the second output signal POUT can be directed to the ground terminal by the eighth transistor T8 and the ninth transistor T9. When the current magnitude changes, the gain control unit 13 can adjust the gain between the first output signal POUTB and the second output signal POUT.

[0040] In summary, the present invention describes an automatic input data buffer circuit that incorporates a gain control unit. Thus, the automatic input data buffer circuit can automatically adjust its gain based on the input data signal to optimize power consumption. Therefore, the automatic input data buffer circuit of the present invention is well-suited for use in high-speed dynamic random access memories.

[0041] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A self-controlled input data buffer circuit for use in a dynamic random access memory, characterized in that: include: A first amplifier comprising: A first input terminal for receiving a data signal; A second input terminal, for receiving a reference signal; a first output terminal; and a second output terminal; a second amplifier coupled to the first output terminal of the first amplifier and the second output terminal of the first amplifier; a feedback signal generator coupled to the second amplifier, the feedback signal generator comprising a plurality of first inverters connected in series, for delaying a signal at a first output terminal of the second amplifier to output a feedback signal; and The gain control unit is coupled to the feedback signal generator, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the second input terminal of the first amplifier.

2. The self-controlled input data buffer circuit according to claim 1, wherein: The first amplifier further includes: A first transistor comprising: A first terminal is used to receive an operating voltage; the second end; and Control terminal; A second transistor comprising: A first end is used to receive the operating voltage; the second end; and a control terminal coupled to the control terminal of the first transistor; A third transistor includes: a first terminal coupled to the second terminal of the first transistor; the second end; and A control terminal, configured to receive the data signal; a fourth transistor comprising: a first terminal coupled to the second terminal of the second transistor; A second terminal coupled to the second terminal of the third transistor; and A control terminal, configured to receive the reference signal; a fifth transistor comprising: a first terminal coupled to the second terminal of the fourth transistor; The second terminal is coupled to the ground terminal; and The control terminal is used to receive a bias signal.

3. The self-controlled input data buffer circuit according to claim 2, wherein: The first transistor and the second transistor are P-type metal oxide semiconductor field effect transistors, and the third transistor, the fourth transistor, and the fifth transistor are N-type metal oxide semiconductor field effect transistors.

4. The self-controlled input data buffer circuit according to claim 1, wherein: The gain control unit includes: a sixth transistor comprising: a first terminal coupled to a first output terminal of the first amplifier; the second end; and a control terminal coupled to the feedback signal generator and configured to receive the feedback signal; A seventh transistor comprising: a first terminal coupled to the second output terminal of the first amplifier; A second terminal coupled to the second terminal of the sixth transistor; and A control terminal, configured to receive the reference signal; an eighth transistor comprising: a first terminal coupled to the second terminal of the seventh transistor; the second end; and a control terminal for receiving a bias signal; and A ninth transistor comprising: and a first terminal coupled to the second terminal of the eighth transistor; The second terminal is coupled to the ground terminal; and The control terminal is used to receive a start signal.

5. The self-controlled input data buffer circuit according to claim 4, wherein: The sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are N-type metal oxide semiconductor field effect transistors.

6. The self-controlled input data buffer circuit according to claim 4, wherein: When the start signal turns on the ninth transistor, the gain control unit adjusts the voltage gain of the gain control unit according to the bias signal, the reference signal, and the feedback signal.

7. The self-controlled input data buffer circuit according to claim 4, wherein: When the start signal turns off the ninth transistor, the gain control unit is turned off.

8. The self-controlled input data buffer circuit according to claim 1, wherein: The first amplifier and the second amplifier are differential amplifiers.

9. The self-controlled input data buffer circuit according to claim 1, wherein: The two signals outputted by the first output terminal of the first amplifier and the second output terminal of the first amplifier are in opposite directions to each other.

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