Wafer level chip packaging method and packaging structure

Abstract

The embodiment of the present disclosure provides a wafer level chip packaging method and a packaging structure, the packaging method comprises the following steps: providing a carrier plate, a chip and a heat sink respectively; a first surface of the chip is provided with a conductive bump; a circuit layer is formed on a first surface of the carrier plate; the first surface of the chip is fixed to the first surface of the carrier plate, so that the conductive bump is electrically connected with the circuit layer; a plastic encapsulation layer is formed on the first surface of the carrier plate and a second surface of the chip; the heat sink is fixed to the second surface of the chip to form a packaging body; the packaging body is cut to form a plurality of independent chip packaging structures. The heat sink is fixed to the chip by using a wafer level packaging process, the mounting efficiency is high, the warping generated in the mounting process is reduced, and the yield of the chip packaging is increased; the heat sink is fixed to the chip, the packaging structure can be quickly cooled, the cooling effect is good, the cooling problem of the packaging structure is solved, and the reliability of the packaging structure is increased; no additional cooling device is needed, and the structure is simple.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a wafer-level chip packaging method and packaging structure. Background Technology

[0002] Traditional chip packaging primarily uses polymers and metals as heat dissipation tools or pathways. However, these traditional packaging methods have several shortcomings in heat dissipation: most polymer materials have poor moisture resistance, chemical stability, and thermal conductivity; metal heat sinks require individual placement on each chip, resulting in low placement efficiency and potential warping issues; and for chips with high heat generation, additional heat dissipation structures are needed, leading to complex chip packaging structures.

[0003] To address the aforementioned issues, it is necessary to propose a well-designed wafer-level chip packaging method and structure that can effectively solve these problems. Summary of the Invention

[0004] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a wafer-level chip packaging method and packaging structure.

[0005] One aspect of this disclosure provides a wafer-level chip packaging method, wherein...

[0006] Encapsulation methods include:

[0007] A carrier board, a chip, and a heat sink are provided respectively; wherein, the first surface of the chip is provided with conductive bumps;

[0008] A circuit layer is formed on the first surface of the carrier board;

[0009] The first surface of the chip is fixed to the first surface of the carrier board, so that the conductive bump is electrically connected to the circuit layer;

[0010] A molding layer is formed on the first surface of the carrier board and the second surface of the chip;

[0011] The heat sink is fixed to the second surface of the chip to form a package;

[0012] The package is cut to form multiple independent chip package structures.

[0013] Optionally, fixing the heat sink to the second surface of the chip includes:

[0014] The heat sink is fixed to a temporary carrier board, wherein the mounting position of the heat sink on the temporary carrier board is consistent with the mounting position of the chip on the carrier board;

[0015] A thermal adhesive layer is formed on the second surface of the chip;

[0016] The heat sink is fixed to the second surface of the corresponding chip in one step using the thermal adhesive layer through a wafer-to-wafer process.

[0017] Remove the temporary carrier plate.

[0018] Optionally, the heat sink can be made of metal or organic materials.

[0019] Optionally, the heat sink is made of indium.

[0020] Optionally, forming a circuit layer on the first surface of the carrier board includes:

[0021] A dielectric layer is formed on the first surface of the carrier plate;

[0022] The dielectric layer is patterned to form multiple openings, and conductive material is filled into the multiple openings to form metal pads;

[0023] Interconnect conductive bumps are formed on the surface of the metal pad facing the chip; wherein, a first end of the interconnect conductive bump is electrically connected to the metal pad, and a second end of the interconnect conductive bump is electrically connected to the conductive bump.

[0024] Optionally, before fixing the heat sink to the second surface of the chip to form a package structure, the method further includes:

[0025] The molding layer is thinned away from the surface of the carrier to expose the second surface of the chip.

[0026] Optionally, before cutting the package to form multiple independent chip package structures, the method further includes:

[0027] Remove the carrier board to expose the circuit layer.

[0028] Optionally, each heat sink corresponds to one chip, and the step of cutting the package to form multiple independent chip package structures includes:

[0029] Cut along the gap between two adjacent heat sinks to form multiple independent chip package structures.

[0030] Optionally, forming a molding layer on the first surface of the carrier and the second surface of the chip includes:

[0031] A molding process is used to form a molding layer on the first surface of the carrier board and the second surface of the chip, the molding layer encapsulating the chip and the circuit layer.

[0032] Another aspect of this disclosure provides a wafer-level chip packaging structure, which is formed by packaging using the packaging method described above.

[0033] This disclosure discloses a wafer-level chip packaging method and packaging structure. The packaging method combines the rapid heat dissipation effect of plastic ball array packaging with the high integration of wafer-level chip packaging. The first surface of the chip is fixed to the first surface of a carrier substrate. Then, a molding compound is formed on the first surface of the carrier substrate and the second surface of the chip. A wafer-level packaging process is used to fix a heat sink to the second surface of the chip in one step to form a package. Finally, the package is cut to form multiple independent chip packaging structures. Using a wafer-level packaging process to fix the heat sink to the chip in one step results in high mounting efficiency, reduces warpage during mounting, and increases the yield of chip packaging. Fixing the heat sink to the second surface of the chip allows for rapid heat dissipation of the packaging structure, providing good heat dissipation and solving the heat dissipation problem of the packaging structure, thus increasing the reliability of the packaging structure. No additional heat dissipation devices are required, resulting in a simple structure. Attached Figure Description

[0034] Figure 1 This is a schematic flowchart of a wafer-level chip packaging method according to one embodiment of the present disclosure;

[0035] Figures 2 to 11 This is a schematic diagram of the packaging process of a wafer-level chip packaging method according to another embodiment of the present disclosure;

[0036] Figure 12 This is a schematic diagram of a wafer-level chip packaging structure according to another embodiment of the present disclosure. Detailed Implementation

[0037] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0038] like Figure 1 As shown, one aspect of this disclosure provides a wafer-level chip packaging method S100, which includes:

[0039] S110, a carrier board, a chip, and a heat sink are provided respectively; wherein, the first surface of the chip is provided with conductive bumps.

[0040] Specifically, such as Figure 2 , Figure 3 and Figure 8As shown, a carrier board 110, a chip 120, and a heat sink 130 are provided. The first surface of the chip 120 is provided with conductive bumps 121. In this embodiment, there are multiple chips 120 and multiple heat sinks 130; the specific number is not specifically limited in this embodiment.

[0041] It should be understood that the first surface 122 of the chip 120 can be either the front or the back surface of the chip 120, and can be selected according to actual needs. In this embodiment, the first surface of the chip 120 is used as the front surface of the chip 120, and the second surface 123 of the chip 120 is used as the back surface for illustrative purposes. That is, in this embodiment, conductive bumps 121 are formed on the front surface of the chip 120.

[0042] It should be noted that the carrier plate 110 can be a glass carrier plate, a silicon wafer, or a carrier plate of other materials, which can be selected according to actual needs. In this embodiment, the carrier plate 110 can be a silicon wafer.

[0043] It should be noted that in this embodiment, the conductive bump 121 is made of copper, but it can also be made of other conductive metals; this embodiment does not impose any specific limitations. The conductive bump 121 can bring out the signals from the chip 120.

[0044] S120, A circuit layer is formed on the first surface of the carrier board.

[0045] like Figure 2 As shown, a circuit layer 140 is formed on the first surface of the carrier board 110. It should be understood that the first surface of the carrier board 110 can be either the front or back surface of the carrier board 110, and can be selected according to actual needs. In this embodiment, the first surface of the carrier board 110 is used as the front surface for illustrative purposes. That is, the circuit layer 140 is formed on the front surface of the carrier board 110.

[0046] In order to form such a shape on the first surface of the carrier plate 110 Figure 2 The circuit layer 140 shown can be constructed using the following two graphical methods.

[0047] The first type of graphic composition technique:

[0048] A dielectric layer 141 is formed on the front side of the substrate 110, a photoresist layer is formed on the dielectric layer 141, and a photomask is placed on the photoresist layer.

[0049] Using a photomask as a mask, the photoresist layer is exposed and developed to form the first opening on the photoresist layer.

[0050] An etching process is used to etch the dielectric layer 141 along the first opening to form multiple openings.

[0051] Metal pads 142 are formed by depositing metal material at multiple openings using deposition processes such as electroplating or sputtering, and then the photoresist layer is removed. The metal material can be copper or other metal materials, which can be selected according to actual needs.

[0052] Continuing with deposition processes, such as electroplating or sputtering, interconnect conductive bumps 133 are formed on the surface of the metal pad 142 facing the chip 120. The first end of the interconnect conductive bump 143 is electrically connected to the metal pad 142, and the second end of the interconnect conductive bump 143 is electrically connected to the conductive bump 121.

[0053] The second type of graphic composition technique:

[0054] A metal layer is formed on the front side of the carrier plate 110. The metal layer can be a copper layer or a metal layer of other materials; this embodiment does not impose any specific limitations.

[0055] A photoresist layer is formed on the metal layer, and a photomask is placed on the photoresist layer.

[0056] Using a photomask as a mask, the photoresist layer is exposed and developed to form multiple second openings on the photoresist layer.

[0057] An etching process is used to etch the metal layer along the second opening to form metal pads 142, and the photoresist layer is removed.

[0058] A dielectric layer 141 is formed on the metal pad 142 using a deposition process. The dielectric layer 141 protects the metal pad 142.

[0059] Continuing with deposition processes, such as electroplating or sputtering, interconnect conductive bumps 143 are formed on the surface of the metal pad 142 facing the chip 120. The first end of the interconnect conductive bump 143 is electrically connected to the metal pad 142, and the second end of the interconnect conductive bump 143 is electrically connected to the conductive bump 121.

[0060] It should be noted that, in this embodiment, the material of the dielectric layer 141 can be polyimide (PI), polybenzoxazole (PBO), etc., and the coating method is usually chip spin coating. This embodiment does not make specific limitations.

[0061] It should be noted that, in addition to using the two graphic patterning processes described above to form the circuit layer 140, those skilled in the art can also choose other graphic patterning methods according to actual needs, and this embodiment does not limit this.

[0062] S130. Fix the first surface of the chip to the first surface of the carrier board, so that the conductive bump is electrically connected to the circuit layer.

[0063] like Figure 3 As shown, the front faces of multiple chips 120 are fixed to the top surface of the carrier board 110, so that the conductive bumps 121 are electrically connected to the circuit layer 140. Specifically, as... Figure 4 As shown, multiple chips 120 are mounted one by one on the top surface of the carrier board 110. The multiple chips 120 are arranged in a matrix on the top surface of the carrier board 110. That is, the conductive bumps 121 are electrically connected to the second end of the interconnecting conductive protrusions 143.

[0064] S140, A molding layer is formed on the first surface of the carrier and the second surface of the chip.

[0065] Specifically, such as Figure 5 As shown, a molding process is used to form a molding compound 150 on the top surface of the carrier 110 and the back surface of the chip 120. The molding compound 150 encapsulates the chip 120 and the circuit layer 140. The molding compound 150 can protect the chip 120 and the circuit layer 140.

[0066] It should be noted that other molding processes can also be used to form the molding layer 150 on the first surface of the carrier 110 and the second surface of the chip 120. This embodiment does not impose specific limitations, and the appropriate process can be selected based on actual conditions. Furthermore, the molding material can be epoxy molding compound, such as epoxy resin, or other molding materials. This embodiment does not impose specific limitations, and the appropriate process can be selected based on actual needs.

[0067] S150. Fix the heat sink to the second surface of the chip to form a package.

[0068] Before fixing the heat sink 130 to the second surface of the chip 120 to form a package, the packaging method S100 further includes:

[0069] like Figure 6 As shown, the surface of the molding layer 150 facing away from the carrier 110 is thinned by processes such as grinding and chemical mechanical polishing to expose the back side of the chip 120.

[0070] To form such Figure 9 The package shown can be packaged using the following process.

[0071] First, such as Figure 7 As shown, multiple heat sinks 130 are fixed to a temporary carrier plate 160. The mounting positions of the multiple heat sinks 130 are consistent with the mounting positions of the multiple chips 120 on the carrier plate 110.

[0072] Secondly, such as Figure 8As shown, a thermal adhesive layer 170 is formed on the second surface of the chip 120. That is, the thermal adhesive layer 170 is coated and bonded onto the back of the plurality of chips 120.

[0073] In this embodiment, applying the thermal adhesive layer 170 to the back of multiple chips 120 not only significantly shortens the process time but also ensures good uniformity in appearance, preventing any adhesive overflow. This provides a good foundation for subsequently fixing the heat sink 130 to the back of the chips 120. The heat sink 130 is thus neatly arranged, essentially centered, with no obvious misalignment.

[0074] Next, the heat sink 130 is fixed to the second surface of the chip 120 using the thermal adhesive layer 170. Specifically, as shown... Figure 7 and Figure 9 As shown, a wafer-to-wafer (W2W) packaging process is used to fix multiple heat sinks 130 to the back of the corresponding chip 120 in one go using a thermal adhesive layer 170.

[0075] Finally, as Figure 9 As shown, the temporary carrier board 160 was removed, and the heat sink 130 was successfully mounted.

[0076] In this embodiment, a wafer-level packaging process is used to fix the heat sink to the chip in one go, which has high mounting efficiency, reduces warpage during the mounting process, and increases the yield of chip packaging.

[0077] For example, the heat sink 130 can be made of a metallic material or an organic material. More preferably, in this embodiment, the heat sink 130 is made of indium.

[0078] S160. The package is cut to form multiple independent chip package structures.

[0079] For example, before cutting the package 100 to form multiple independent chip package structures 100, the packaging method S100 further includes:

[0080] like Figure 10 As shown, the carrier substrate 110 is removed to expose the circuit layer 140. Specifically, if the carrier substrate 110 is a silicon wafer, the back side of the silicon wafer can be ground using processes such as polishing to expose the circuit layer 140. If the carrier substrate 110 is a glass carrier substrate, the glass can be removed from the carrier substrate using carrier plate separation technology. Separation methods can include thermal separation, laser separation, ultraviolet light separation, mechanical separation, etc. A suitable process can be selected to remove the carrier substrate 110 according to actual needs.

[0081] For example, each heat sink 130 corresponds to one chip 120. The package is cut to form multiple independent chip package structures 100, specifically including:

[0082] like Figure 11 As shown, multiple independent chip package structures 100 are formed by cutting along the gap between two adjacent heat sinks 130. That is, there is a cutting channel between two adjacent heat sinks 130, and the package is cut along the cutting channel to form multiple independent chip package structures 100.

[0083] The wafer-level chip packaging method of this disclosure combines the rapid heat dissipation effect of plastic ball array packaging with the high integration of wafer-level chip packaging. The first surface of the chip is fixed to the first surface of a carrier substrate; then, a molding compound is formed on the first surface of the carrier substrate and the second surface of the chip; a wafer-level packaging process is used to fix a heat sink to the second surface of the chip in one step to form a package; finally, the package is cut to form multiple independent chip package structures. Using a wafer-level packaging process to fix the heat sink to the chip in one step results in high mounting efficiency, reduces warpage during mounting, and increases the yield of chip packaging; fixing the heat sink to the second surface of the chip allows for rapid heat dissipation of the package structure, providing good heat dissipation and solving the heat dissipation problem of the package structure, thus increasing the reliability of the package structure; no additional heat dissipation devices are required, resulting in a simple structure.

[0084] Another aspect of this disclosure provides a wafer-level chip packaging structure 100, which is formed using the packaging method S100 described above. The specific packaging steps of the packaging method S100 have been described in detail above and will not be repeated here.

[0085] This wafer-level chip package structure 100 includes a chip 120, a heat sink 130, a circuit layer 140, and a molding compound 150. The first surface of the chip 120 is provided with conductive bumps 121.

[0086] The circuit layer 140 is disposed on the first surface of the chip 120. That is, in this embodiment, the circuit layer 140 is disposed on the front side of the chip 120, and the circuit layer 140 is electrically connected to the conductive bump 121.

[0087] Furthermore, in this embodiment, the circuit layer 140 includes a dielectric layer 141, metal pads 142, and interconnect conductive bumps 143. The dielectric layer 141 is disposed on the front side of the chip 120, the metal pads 142 are disposed on the dielectric layer 141, and the interconnect conductive bumps 143 are disposed on the side of the metal pads 142 facing the chip 120. The first end of the interconnect conductive bump 143 is electrically connected to the metal pads 142, and the second end of the interconnect conductive bump 143 is electrically connected to the chip 120.

[0088] The molding compound 150 encapsulates the chip 120 and the circuit layer 140, providing protection for the chip 120 and the circuit layer 140.

[0089] A heat sink 130 is disposed on the second surface of the chip 120. That is, the heat sink 130 is disposed on the back side of the chip 120 and serves to dissipate heat from the chip 120. A thermal adhesive layer 170 is sandwiched between the heat sink 130 and the chip 120. The thermal adhesive layer 170 serves to fix the heat sink 130 to the back side of the chip 120 through the thermal adhesive layer 170.

[0090] The wafer-level chip packaging structure of this disclosure fixes the heat sink to the second surface of the chip through a thermal adhesive layer, resulting in good heat dissipation and a simple structure.

[0091] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A wafer-level chip packaging method, characterized in that, The encapsulation method includes: A carrier board, a chip, and a heat sink are provided respectively; wherein, the first surface of the chip is provided with conductive bumps; A circuit layer is formed on the first surface of the carrier board; The first surface of the chip is fixed to the first surface of the carrier board, so that the conductive bump is electrically connected to the circuit layer; A molding layer is formed on the first surface of the carrier board and the second surface of the chip; Fixing the heat sink to the second surface of the chip to form a package specifically includes: fixing the heat sink to a temporary carrier board, wherein the mounting position of the heat sink on the temporary carrier board is consistent with the mounting position of the chip on the carrier board; forming a thermal adhesive layer on the second surface of the chip; fixing the heat sink to the corresponding second surface of the chip in one step through the thermal adhesive layer using a wafer-to-wafer process to improve mounting efficiency; and removing the temporary carrier board. The package is cut to form multiple independent chip package structures; wherein... Each heat sink corresponds to one chip, and the process of cutting the package to form multiple independent chip package structures includes: Cut along the gap between two adjacent heat sinks to form multiple independent chip package structures.

2. The packaging method according to claim 1, characterized in that, The heat sink is made of metal or organic materials.

3. The packaging method according to claim 2, characterized in that, The heat sink is made of indium.

4. The packaging method according to any one of claims 1 to 3, characterized in that, The formation of a circuit layer on the first surface of the carrier board includes: A dielectric layer is formed on the first surface of the carrier plate; The dielectric layer is patterned to form multiple openings, and conductive material is filled into the multiple openings to form metal pads; Interconnect conductive bumps are formed on the surface of the metal pad facing the chip; wherein, a first end of the interconnect conductive bump is electrically connected to the metal pad, and a second end of the interconnect conductive bump is electrically connected to the conductive bump.

5. The packaging method according to any one of claims 1 to 3, characterized in that, Before fixing the heat sink to the second surface of the chip to form a package, the method further includes: The molding layer is thinned away from the surface of the carrier to expose the second surface of the chip.

6. The packaging method according to any one of claims 1 to 3, characterized in that, Before cutting the package to form multiple independent chip package structures, the method further includes: Remove the carrier board to expose the circuit layer.

7. The packaging method according to any one of claims 1 to 3, characterized in that, The process of forming a molding compound layer on the first surface of the carrier and the second surface of the chip includes: A molding process is used to form a molding layer on the first surface of the carrier board and the second surface of the chip, the molding layer encapsulating the chip and the circuit layer.

8. A wafer-level chip packaging structure, characterized in that, The encapsulation structure is formed by encapsulation using the encapsulation method described in any one of claims 1 to 7.

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