Semiconductor structures, their formation methods, and semiconductor devices

Abstract

This invention provides a method for forming a semiconductor structure, comprising forming a second stopper material layer filling trenches on a source / drain contact metal layer, wherein the top surface of the second stopper material layer is higher than the top surface of a first stopper material layer covering the top surface of a gate structure. This facilitates greater freedom in material selection for different stopper material layers, allowing the gate and source / drain contacts to use only one stopper material, thereby simplifying the fabrication process. This invention also provides a semiconductor structure obtained by the described method and a semiconductor device including the described semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to semiconductor structures, methods of forming them, and semiconductor devices. Background Technology

[0002] One of the research and development hotspots in standard complementary metal-oxide-semiconductor (CMOS) design is how to increase chip integration density by reducing device area.

[0003] In existing technologies, to improve integration density, the top surface heights of the stopper material layer located on top of the gate structure and the stopper material layer located on top of the source / drain contact metal layers are often made the same. However, to control the accuracy of subsequent processes, such as using materials with different compositions to form different stopper material layers, the requirements for operational control precision are high; if the same material is used to form different stopper material layers, the processing of one stopper material layer can easily affect the subsequent processing control of the other stopper material layer.

[0004] Therefore, it is necessary to develop a novel method for forming semiconductor structures to solve the aforementioned problems in existing technologies. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor structure and a method for forming the same, as well as a semiconductor device including the semiconductor structure, to expand the freedom of material selection for different stopper material layers and simplify the processing technology.

[0006] To achieve the above objectives, the method for forming the semiconductor structure of the present invention includes the following steps:

[0007] S0: A substrate is provided, wherein a gate structure is formed on the substrate, a source / drain epitaxial layer is formed in the substrate located on at least one side of the gate structure, an initial dielectric layer is covered on top of the gate structure, a trench is formed in the initial dielectric layer and exposes the source / drain epitaxial layer, and the initial dielectric layer includes a first stopper material layer covering the top surface of the gate structure.

[0008] S1: A source / drain contact metal layer that is electrically in contact with the source / drain epitaxial layer is formed in the trench, and a second stopper material layer that fills the trench is formed on the source / drain contact metal layer, and the top surface of the second stopper material layer is higher than the top surface of the first stopper material layer.

[0009] S2: A second medium layer is formed on the first medium layer, which is jointly formed by the second stopper material layer and the initial medium layer;

[0010] S3: A source / drain contact via penetrating the first dielectric layer and the second dielectric layer is formed on the source / drain contact metal layer, and a gate contact via penetrating the first dielectric layer and the second dielectric layer is formed on the gate structure;

[0011] S4: A source / drain contact hole plug electrically connected to the source / drain contact metal layer is formed in the source / drain contact via, and a gate contact hole plug electrically connected to the gate structure is formed in the gate contact via.

[0012] The beneficial effect of the semiconductor structure formation method of the present invention is that: by forming a second stopper material layer that fills the trench on the source and drain contact metal layer through step S1, and making the top surface of the second stopper material layer higher than the top surface of the first stopper material layer that covers the top surface of the gate structure, even if the first stopper material layer and the second stopper material layer are made of the same material, the processing of either the first stopper material layer or the second stopper material layer, especially the etching process, will not easily affect the other, thereby expanding the freedom of material selection for different stopper material layers and simplifying the processing technology.

[0013] Preferably, the method for forming the semiconductor structure further includes removing a portion of the initial dielectric layer from the trench sidewalls to increase the window diameter of the trench, and then performing step S1. Its advantages include increasing the operating window for subsequent processes, which is beneficial for improving integration density.

[0014] More preferably, step S1 further includes: forming a protective layer on top of the source / drain epitaxial layer before removing a portion of the initial dielectric layer on the trench sidewalls, and removing the protective layer after removing a portion of the initial dielectric layer on the trench sidewalls. The advantage of this is that it protects the gate structure and the source / drain epitaxial layer from damage during the side-pushing process.

[0015] Preferably, in step S3, a first dielectric material layer and a second dielectric material layer are sequentially deposited on the top surface of the first dielectric layer to form the second dielectric layer, wherein the etch rate ratio between the constituent materials of the second dielectric material layer and the constituent materials of the first dielectric material layer is not less than 50:1. Its beneficial effect is that, combined with the removal of part of the sidewalls of the trench through a side-pushing process, it increases the process operation window for subsequent formation of source / drain contact vias and gate contact vias.

[0016] Preferably, in step S1, the initial dielectric layer thickness of the removed trench sidewall is 5 nm to 10 nm. This has the advantage of increasing the operating process window while avoiding the risk of short circuits due to excessive lateral thrust.

[0017] Preferably, after step S3 is completed, a pad layer is formed covering the sidewalls of the source / drain contact vias and the sidewalls of the gate contact vias, and then step S4 is performed. Its advantage is that it avoids the risk of short circuits.

[0018] More preferably, the step of forming the pad layer includes: forming an initial pad layer covering the top of the second dielectric layer, the sidewall of the source / drain contact via, the sidewall of the gate contact via, the bottom of the source / drain contact via, and the bottom of the gate contact via, and then etching away the initial pad layer to form the pad layer.

[0019] Preferably, in step S1, the top surface of the source / drain contact metal layer formed in the trench and electrically contacting the source / drain epitaxial layer is controlled to be higher than the top surface of the gate structure. This has the advantage of reducing the amount of processing required for subsequent source / drain contact vias and avoiding situations where the source / drain contact metal layer cannot be exposed during the formation of source / drain contact vias.

[0020] The semiconductor structure of the present invention includes:

[0021] Substrate;

[0022] A gate structure is located on the substrate;

[0023] The source / drain epitaxial layer is located within the substrate on at least one side of the gate structure;

[0024] The source / drain contact metal layer covers the top of the source / drain epitaxial layer and is electrically connected to the source / drain epitaxial layer;

[0025] A dielectric layer covering the top of the gate structure and the source / drain contact metal layer, the dielectric layer including a second stopper material layer covering the top surface of the source / drain contact metal layer and a first stopper material layer covering the top surface of the gate structure, the top surface of the second stopper material layer being higher than the top surface of the first stopper material layer;

[0026] The source / drain contact hole plug is electrically connected to the source / drain contact metal layer;

[0027] A gate contact hole plug is electrically connected to the gate structure.

[0028] The beneficial effects of the semiconductor structure described in this invention are as follows: Since the dielectric layer includes a second stopper material layer covering the top surface of the source / drain contact metal layer and a first stopper material layer covering the top surface of the gate structure, and the top surface of the second stopper material layer is higher than the top surface of the first stopper material layer, the processing of either the first stopper material layer or the second stopper material layer, especially the etching process, is less likely to affect the other, thereby expanding the freedom of material selection for different stopper material layers and simplifying the processing technology.

[0029] Preferably, the constituent materials of the first stopper material layer are the same as or different from those of the first stopper material layer. This has the advantage of increasing the freedom of material selection for different stopper material layers.

[0030] Preferably, the cross-sectional area of ​​the top of the second stopper material layer is larger than the cross-sectional area of ​​the source / drain contact metal layer. This has the advantage of increasing the operating window for subsequent processes, which is beneficial for improving integration density.

[0031] Preferably, both the sidewalls of the source / drain contact hole plug and the sidewalls of the gate contact hole plug are formed with a padding layer. This has the advantage of avoiding the risk of short circuits.

[0032] More preferably, the thickness of the padding layer is 1 nanometer to 5 nanometers.

[0033] More preferably, the liner layer is composed of silicon nitride or silicon carbide.

[0034] Preferably, the top surface of the source / drain contact metal layer is higher than the top surface of the gate structure. This has the advantage of avoiding the risk of short circuits between the source / drain contact hole plugs and the gate structure.

[0035] Preferably, the gate structure further includes sidewalls on both sides.

[0036] The semiconductor device of the present invention includes the semiconductor structure. Attached Figure Description

[0037] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the substrate structure according to an embodiment of the present invention;

[0039] Figure 3 To Figure 2 A schematic diagram of the structure formed after coating and etching back;

[0040] Figure 4 To Figure 3The diagram shows the structure after lateral thrust treatment and removal of the protective layer.

[0041] Figure 5 To Figure 4 The diagram shows the structure formed after depositing the first conductive material and performing the first planarization process.

[0042] Figure 6 To Figure 5 The diagram shows the structure formed after the initial metal layer is etched back and the stopper material is deposited and then subjected to a second planarization process.

[0043] Figure 7 To Figure 6 The diagram shows the structure formed after the deposition of the second dielectric layer.

[0044] Figure 8 To Figure 7 A schematic diagram of the structure formed after the etching process is performed on the structure shown.

[0045] Figure 9 To Figure 8 The diagram shows the structure formed after the initial liner layer is deposited.

[0046] Figure 10 To remove Figure 9 A schematic diagram of the structure formed after the initial liner layer is shown;

[0047] Figure 11 To Figure 10 The diagram shows the structure formed after selective metal deposition and a third planarization process. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0049] This invention provides a method for forming a semiconductor structure to simplify the processing technology, increase the process operation window, and reduce the short-circuit risk between the gate contact hole plug and the source / drain contact hole plug.

[0050] In this embodiment of the invention, a gate structure is formed on the substrate for forming the semiconductor structure, and a source / drain epitaxial layer is formed in the substrate located on at least one side of the gate structure. An initial dielectric layer covers the top of the gate structure, and a trench is formed in the initial dielectric layer to expose the source / drain epitaxial layer. The initial dielectric layer includes a first stopper material layer covering the top surface of the gate structure.

[0051] Reference Figure 1 The method for forming the semiconductor structure according to embodiments of the present invention includes:

[0052] S0: Provide the substrate;

[0053] S1: A source / drain contact metal layer that is electrically in contact with the source / drain epitaxial layer is formed in the trench, and a second stopper material layer that fills the trench is formed on the source / drain contact metal layer, and the top surface of the second stopper material layer is higher than the top surface of the first stopper material layer that covers the top surface of the gate structure.

[0054] S2: A second medium layer is formed on the first medium layer, which is jointly formed by the second stopper material layer and the initial medium layer;

[0055] S3: A source / drain contact via penetrating the first dielectric layer and the second dielectric layer is formed on the source / drain contact metal layer, and a gate contact via penetrating the first dielectric layer and the second dielectric layer is formed on the gate structure;

[0056] S4: A source / drain contact hole plug electrically connected to the source / drain contact metal layer is formed in the source / drain contact via, and a gate contact hole plug electrically connected to the gate structure is formed in the gate contact via.

[0057] Embodiments of the present invention also provide a semiconductor structure obtained by the formation method and a semiconductor device including the semiconductor structure.

[0058] The semiconductor structure includes:

[0059] Substrate;

[0060] A gate structure is located on the substrate;

[0061] The source / drain epitaxial layer is located within the substrate on at least one side of the gate structure;

[0062] The source / drain contact metal layer covers the top of the source / drain epitaxial layer and is electrically connected to the source / drain epitaxial layer;

[0063] A dielectric layer that covers the top of the gate structure and the source / drain contact metal layer;

[0064] The source / drain contact hole plug is electrically connected to the source / drain contact metal layer;

[0065] A gate contact hole plug is electrically connected to the gate structure.

[0066] The dielectric layer includes a second stopper material layer covering the top surface of the source / drain contact metal layer and a first stopper material layer covering the top surface of the gate structure, wherein the top surface of the second stopper material layer is higher than the top surface of the first stopper material layer.

[0067] In some embodiments of the present invention, the cross-sectional area of ​​the top of the second stopper material layer is larger than the cross-sectional area of ​​the source / drain contact metal layer.

[0068] The following reference Figures 2-11 The method for forming the semiconductor structure is described in detail.

[0069] Figure 2 This is a schematic diagram of the substrate structure according to some embodiments of the present invention.

[0070] Reference Figure 2 A gate structure 23 is formed on the substrate 21. A source / drain epitaxial layer 22 is formed in the substrate on one side of the gate structure 23. An initial dielectric layer (not shown in the figure) covering the top of the gate structure 23 is formed on the exposed substrate of the gate structure 23. A trench is formed in the initial dielectric layer (not shown in the figure) and exposes the source / drain epitaxial layer 22.

[0071] The initial dielectric layer 24 at the top of the gate structure includes a first stopper material layer 241, an intermediate dielectric layer 242, and a top dielectric layer 243 stacked sequentially.

[0072] In some specific embodiments of the present invention, the substrate 21 is composed of any one of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ionide.

[0073] The gate structure 23 controls the opening or closing of the conductive channel during the operation of the semiconductor device. In some specific embodiments of the present invention, the gate structure 23 is an HKMG gate composed of a metal gate and a high-k dielectric insulating layer.

[0074] The source / drain epitaxial layer 22 contains either N-type or P-type doped ions, thereby improving the carrier mobility of the formed semiconductor structure. In some specific embodiments of the present invention, when the semiconductor structure is an NMOS transistor, the N-type doped source / drain epitaxial layer 22 is phosphorus ions, arsenic ions, or antimony ions; when the semiconductor structure is a PMOS transistor, the P-type doped source / drain epitaxial layer 22 is boron ions, gallium ions, or indium ions.

[0075] In some embodiments of the present invention, the first stopper material layer 241, the intermediate medium layer 242 and the top medium layer 243 may be composed of the same or different materials, and the materials are any one of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate and silicon carbonitride.

[0076] Reference Figure 2 Sidewalls 25 are also formed on both sides of the gate structure 23 to serve as part of the initial dielectric layer on top of the gate structure 23. The sidewalls 25 define the formation region of the source / drain epitaxial layer 22 and protect the gate structure 23 during the semiconductor structure formation process.

[0077] In some embodiments of the present invention, the sidewall 25 is a single-layer structure or a multilayer structure formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride.

[0078] In some more specific embodiments of the present invention, the sidewall 25 is an oxide-nitride-oxide (ONO) structure, consisting of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked sequentially.

[0079] Figure 3 To Figure 2 The diagram shows the structure formed after coating and etching.

[0080] In some embodiments of the present invention, step S1 further includes: forming a protective layer on top of the source / drain epitaxial layer before removing a portion of the initial dielectric layer on the trench sidewall, and removing the protective layer after removing a portion of the initial dielectric layer on the trench sidewall. The process of removing a portion of the initial dielectric layer on the trench sidewall is a side-pushing process.

[0081] Specifically, refer to Figure 3 First, a protective layer 31 is formed on top of the source / drain epitaxial layer 22 to prevent the gate structure 23 and the source / drain epitaxial layer 22 from being etched and damaged during the side push process.

[0082] Specifically, refer to Figure 2 and Figure 3 After filling the trenches on top of the source / drain epitaxial layer 22 with coating material and covering part of the initial dielectric layer 24 on top of the gate structure to complete the coating, the coating material is etched back to form the protective layer 31, and the top of the protective layer 31 is controlled to be higher than the top of the gate structure 23.

[0083] In some specific embodiments of the present invention, the coating material is spin-coated carbon, and the coating method is spin coating. The specific implementation methods of spin coating and etch-back are conventional technical means for those skilled in the art.

[0084] Figure 4 To Figure 3 The diagram shows the structure after lateral thrusting and removal of the protective layer.

[0085] Reference Figure 3 and Figure 4 After the protective layer 31 is formed, a trench (not shown in the figure) is formed between the initial dielectric layer 24 on top of the gate structure and the protective layer 31 on top of the source drain epitaxial layer 22. After the sidewall of the trench (not shown in the figure) is removed by the side push process, the window diameter of the trench (not shown in the figure) is increased.

[0086] Specifically, the window diameter of the trench is Figure 2 The horizontal distance between the opposing sidewalls of the two top dielectric layers 243 shown.

[0087] Furthermore, after the side-pushing process is completed, the protective layer 31 on the top of the source / drain epitaxial layer 22 is removed, exposing the top of the source / drain epitaxial layer 22.

[0088] In some embodiments of the present invention, a side-pushing process is performed to remove part of the sidewall of the initial dielectric layer covering the top of the gate structure 23, thereby increasing the window diameter of the trench and providing a larger operating window for subsequent process operations.

[0089] Specifically, in the initial dielectric layer covering the top of the gate structure 23, the sidewalls of the initial dielectric layer at the top are removed by a side-pushing process, thereby increasing the window diameter of the trench.

[0090] In some specific embodiments of the present invention, see [reference needed]. Figure 2 and Figure 4 The sidewalls of the top dielectric layer 243 were removed by a side-pushing process.

[0091] In some specific embodiments of the present invention, reference is made to Figure 2 The side-pushing process removed part of the sidewall of the top dielectric layer 243 and part of the sidewall of the middle dielectric layer 242.

[0092] The degree of removal of a portion of the sidewalls of the top dielectric layer 243 may be the same as or different from the degree of removal of a portion of the sidewalls of the intermediate dielectric layer 242.

[0093] Where the degree of removal of a portion of the sidewalls of the top dielectric layer 243 is different from the degree of removal of a portion of the sidewalls of the intermediate dielectric layer 242, the horizontal distance between adjacent top dielectric layers 243 is greater than the horizontal distance between adjacent intermediate dielectric layers 242, so as to ensure that the window diameter of the trench (not shown in the figure) is increased.

[0094] The degree of removal described in this embodiment of the invention is measured by the thickness of the initial medium layer removed; the greater the thickness of the initial medium layer removed, the higher the degree of removal.

[0095] In some embodiments of the present invention, the initial dielectric layer thickness of the removed trench sidewall is 5 nanometers to 10 nanometers, which increases the operating process window while avoiding the risk of short circuit due to excessive lateral push.

[0096] In some embodiments of the present invention, the side-pushing process is completed by an etching process. Specifically, the etching process is wet etching.

[0097] In some embodiments of the present invention, after the lateral pushing process is completed, the protective layer 31 is removed. Specifically, the protective layer 31 is removed by sequentially performing ashing and wet stripping.

[0098] In some embodiments of the present invention, since the sidewalls 25 are also formed on both sides of the gate structure 23, after the side push process is completed, the initial dielectric layer covering the top of the source drain epitaxial layer 22, i.e. the protective layer 31, is removed, and the top of the source drain epitaxial layer 22 and part of the surface of the sidewalls 25 are exposed.

[0099] Figure 5 To Figure 4 The diagram shows the structure formed after depositing the first conductive material and performing the first planarization process.

[0100] Reference Figure 5 After filling the trench at the top of the source / drain epitaxial layer 22 with the first conductive material and covering the initial dielectric layer 24 on the top surface of the gate structure, a first planarization process is performed with the portion of the initial dielectric layer 24 at the top of the gate structure as the stopping position to form the initial metal layer 51.

[0101] In some specific embodiments of the present invention, the process of filling the first conductive material is an electroplating deposition process, and the first conductive material used is cobalt metal.

[0102] In some specific embodiments of the present invention, the first planarization process is a chemical mechanical planarization process.

[0103] Figure 6 To Figure 5 The diagram shows the structure formed after the initial metal layer is etched back and the stopper material is deposited and then subjected to a second planarization process.

[0104] Reference Figure 5 and Figure 6After etching back the initial metal layer 51, a source / drain contact metal layer 61 is formed that is electrically in contact with the source / drain epitaxial layer 22. Then, a stopper material is deposited on top of the source / drain contact metal layer 61 to fill the trench on top of the source / drain contact metal layer 61 and cover the surface of a portion of the initial dielectric layer 24 on top of the gate structure. A second planarization process is then performed with the portion of the initial dielectric layer 24 on top of the gate structure as the stop position to form a second stopper material layer 62.

[0105] In some embodiments of the present invention, the top surface of the source / drain contact metal layer 61 is controlled to be higher than the top surface of the gate structure 23.

[0106] Specifically, the top surface of the source / drain contact metal layer 61 is higher than the top surface of the gate structure 23. In the subsequent process of forming source / drain contact vias through etching, the amount of etching of the source / drain contact vias can be effectively reduced, thereby avoiding the situation where the source / drain contact metal layer 61 cannot be exposed during the process of forming source / drain contact vias.

[0107] In some embodiments of the present invention, the composition of the second stopper material layer 62 is the same as or different from the composition of the first stopper material layer 241.

[0108] Furthermore, the top surface of the second stopper material layer 62 is higher than the top surface of the first stopper material layer 241. Even if the first stopper material layer and the second stopper material layer are made of the same material, processing, especially etching, on either the first stopper material layer 241 or the second stopper material layer 62 will not easily affect the other. This expands the freedom of material selection for different stopper material layers and simplifies the processing technology.

[0109] Because the side-pushing process was performed in step S1, the cross-sectional area of ​​the top of the second stopper material layer 62 is larger than the cross-sectional area of ​​the source-drain contact metal layer 61.

[0110] The cross-sectional range described in this embodiment of the invention refers to the range defined by the cross-sectional edge formed along the top surface direction of the substrate 22 by either the second stopper material layer 62 or the source / drain contact metal layer 61.

[0111] Furthermore, the second stopper material layer 62 and the initial dielectric layer 24 on top of the gate structure together constitute the first dielectric layer.

[0112] In some embodiments of the present invention, the top of the source / drain contact metal layer 61 formed by back etching is not lower than the top of the gate structure 23, so as to avoid the risk of short circuit in the subsequently formed source / drain contact hole plug and gate structure.

[0113] In some embodiments of the present invention, the stopper material is deposited by atomic layer deposition, and the stopper material is specifically silicon nitride.

[0114] Figure 7 To Figure 6 The diagram shows the structure formed after the deposition of the second dielectric layer.

[0115] In step S3 of some embodiments of the present invention, a first dielectric material layer and a second dielectric material layer are sequentially deposited on the top surface of the first dielectric layer to form the second dielectric layer.

[0116] Specifically, refer to Figure 7 A second dielectric layer 71 is deposited on top of the initial dielectric layer 24 at the top of the gate structure and the second stopper material layer 62.

[0117] More specifically, a first dielectric material layer 711 and a second dielectric material layer 712 are deposited sequentially to form the second dielectric layer 71.

[0118] In some embodiments of the present invention, the etching rate ratio between the constituent materials of the second dielectric material layer 712 and the constituent materials of the first dielectric material layer 711 is not less than 50:1. Combined with the removal of part of the sidewall of the trench by the side push process, the process operation window for subsequent formation of source / drain contact vias and gate contact vias is increased.

[0119] In some specific embodiments of the present invention, the second dielectric layer 71 is formed by atomic layer deposition.

[0120] In some specific embodiments of the present invention, the first dielectric material and the second dielectric material are silicon nitride and silicon oxide, respectively.

[0121] Figure 8 To Figure 7 The diagram shows the structure formed after the etching process.

[0122] Reference Figure 8 A source / drain contact via 81 is formed on the source / drain contact metal layer 61, exposing a portion of the top surface of the source / drain contact metal layer 61; a gate contact via 82 is formed on the gate structure 23, exposing a portion of the top surface of the gate structure 23.

[0123] In some embodiments of the present invention, a source / drain contact via 81 is first formed on the source / drain contact metal layer 61, and then a gate contact via 82 is formed on the gate structure 23.

[0124] In some other embodiments of the present invention, a gate contact via 82 is first formed on the gate structure 23, and then a source / drain contact via 82 is formed on the source / drain contact metal layer 61.

[0125] Specifically, the source / drain contact via 81 and the gate contact via 82 both penetrate the second dielectric layer 71, which is composed of the first dielectric material layer 711 and the second dielectric material layer 712, and the first dielectric layer, which is composed of the second stopper material layer 62 and the initial dielectric layer 24 at the top of the gate structure.

[0126] In some specific embodiments of the present invention, the source / drain contact vias 81 and the gate contact vias 82 are formed using a standard photolithography etching process. The standard photolithography etching process is a conventional technique in the art.

[0127] Figure 9 To Figure 8 The diagram shows the structure formed after the initial liner layer is deposited.

[0128] Reference Figure 8 and Figure 9 An initial pad layer 91 is formed by atomic layer deposition, covering the top of the second dielectric layer 71, the sidewalls of the source / drain contact via 81, the sidewalls of the gate contact via 82, and the bottoms of the source / drain contact via 81 and the gate contact via 82, so that the top of the source / drain contact metal layer 61 and the top of the gate structure 23 are covered.

[0129] Figure 10 To remove Figure 9 The diagram shows a partial structural representation of the structure formed after the initial liner layer.

[0130] Reference Figure 8 and Figure 9 After etching away the initial pad layer 91 at the top of the second dielectric material layer 712, the bottom of the source / drain contact via 81, and the bottom of the gate contact via 82, a pad layer 101 is formed.

[0131] In some specific embodiments of the present invention, the thickness of the padding layer 101 is 1 nanometer to 5 nanometers.

[0132] Figure 11 To Figure 10 The diagram shows the structure formed after selective metal deposition and a third planarization process.

[0133] Reference Figure 8 , Figure 10 and Figure 11 A source / drain contact plug 111 electrically connected to the source / drain contact metal layer 61 is formed in the source / drain contact via 81 whose sidewall is covered by the pad layer 101; and a gate contact plug 112 electrically connected to the gate structure 23 is formed in the gate contact via 82.

[0134] In some embodiments of the present invention, a second conductive material is deposited simultaneously into the source / drain contact vias 81 and 82, which are covered by the pad layer 101 on the sidewall, using a selective metal deposition process to fill the trenches on the top of the source / drain contact metal layer 61 and the gate structure 23 and cover the top of the pad layer 101 and the second dielectric material layer 712. Since the top of the pad layer 101 and the top of the second dielectric material layer 712 are flush, a third planarization process is performed with the top of the pad layer 101 and the top of the second dielectric material layer 712 as the stopping position, thereby forming the source / drain contact hole plug 111 and the gate contact hole plug 112.

[0135] In some embodiments of the present invention, a source / drain contact hole plug 111 electrically connected to the source / drain contact metal layer 61 is first formed in the source / drain contact via 81, and then a gate contact hole plug 112 electrically connected to the gate structure 23 is formed in the gate contact via 82.

[0136] In some embodiments of the present invention, a gate contact hole plug 112 electrically connected to the gate structure 23 is first formed in the gate contact via 82, and then a source / drain contact hole plug 111 electrically connected to the source / drain contact metal layer 61 is formed in the source / drain contact via 81.

[0137] In some embodiments of the present invention, the process of forming a gate contact hole plug 112 electrically connected to the gate structure 23 in the gate contact via 82 is performed simultaneously with the process of forming a source / drain contact hole plug 111 electrically connected to the source / drain contact metal layer 61 in the source / drain contact via 81.

[0138] In some specific embodiments of the present invention, the second conductive material is tungsten metal. The third planarization treatment is a chemical mechanical planarization treatment.

[0139] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including the following steps: S0: A substrate is provided, wherein a gate structure is formed on the substrate, a source / drain epitaxial layer is formed in the substrate located on at least one side of the gate structure, an initial dielectric layer is covered on top of the gate structure, a trench is formed in the initial dielectric layer and exposes the source / drain epitaxial layer, and the initial dielectric layer includes a first stopper material layer covering the top surface of the gate structure. S1: A source / drain contact metal layer that is electrically in contact with the source / drain epitaxial layer is formed in the trench, and a second stopper material layer that fills the trench is formed on the source / drain contact metal layer, and the top surface of the second stopper material layer is higher than the top surface of the first stopper material layer. S2: A second medium layer is formed on the first medium layer, which is jointly formed by the second stopper material layer and the initial medium layer; S3: A source / drain contact via penetrating the first dielectric layer and the second dielectric layer is formed on the source / drain contact metal layer, and a gate contact via penetrating the first dielectric layer and the second dielectric layer is formed on the gate structure; S4: A source / drain contact hole plug electrically connected to the source / drain contact metal layer is formed in the source / drain contact via, and a gate contact hole plug electrically connected to the gate structure is formed in the gate contact via.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, It also includes removing part of the initial medium layer from the sidewall of the trench to increase the window diameter of the trench, and then performing step S1.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, Also includes: A protective layer is formed on top of the source / drain epitaxial layer before removing a portion of the initial dielectric layer on the trench sidewalls, and the protective layer is removed after removing a portion of the initial dielectric layer on the trench sidewalls.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, In step S2, a first dielectric material layer and a second dielectric material layer are sequentially deposited on the top surface of the first dielectric layer to form the second dielectric layer, wherein the etch rate ratio between the constituent materials of the second dielectric material layer and the constituent materials of the first dielectric material layer is not less than 50:

1.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, After step S3 is completed, a pad layer is formed covering the sidewalls of the source / drain contact via and the sidewalls of the gate contact via, and then step S4 is performed.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The steps for forming the liner layer include: After forming an initial pad layer covering the top of the second dielectric layer, the sidewalls of the source / drain contact via, the sidewalls of the gate contact via, the bottom of the source / drain contact via, and the bottom of the gate contact via, the pad layer is formed by removing the initial pad layer covering the top of the second dielectric layer, the bottom of the source / drain contact via, and the bottom of the gate contact via.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, In step S1, the top surface of the source / drain contact metal layer formed in the trench and electrically in contact with the source / drain epitaxial layer is controlled to be higher than the top surface of the gate structure.

8. A semiconductor structure, characterized in that, include: Substrate; A gate structure is located on the substrate; The source / drain epitaxial layer is located within the substrate on at least one side of the gate structure; The source / drain contact metal layer covers the top of the source / drain epitaxial layer and is electrically connected to the source / drain epitaxial layer; A dielectric layer covering the top of the gate structure and the source / drain contact metal layer, the dielectric layer including a second stopper material layer covering the top surface of the source / drain contact metal layer and a first stopper material layer covering the top surface of the gate structure, the top surface of the second stopper material layer being higher than the top surface of the first stopper material layer; The source / drain contact hole plug is electrically connected to the source / drain contact metal layer; A gate contact hole plug is electrically connected to the gate structure.

9. The semiconductor structure according to claim 8, characterized in that, The cross-sectional area of ​​the top of the second stopper material layer is larger than the cross-sectional area of ​​the source / drain contact metal layer.

10. The semiconductor structure according to claim 8, characterized in that, Both the sidewalls of the source / drain contact hole plug and the sidewalls of the gate contact hole plug are formed with a padding layer.

11. The semiconductor structure according to claim 8, characterized in that, The top surface of the source / drain contact metal layer is higher than the top surface of the gate structure.

12. A semiconductor device, characterized in that, Including the semiconductor structure as described in any one of claims 8-11.

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