A semiconductor structure and a method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate; a first dielectric layer covering an upper surface of the substrate; a first conductive layer comprising at least a first sub-layer, the first sub-layer covering a part of the upper surface of the first dielectric layer; a second conductive layer covering the first conductive layer; wherein a diffusion coefficient of the first conductive layer in a solid is less than a diffusion coefficient of the second conductive layer in a solid; a conductive via extending from a lower surface opposite to the substrate to the first sub-layer and exposing the first sub-layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] A semiconductor structure, such as a memory, generally includes a substrate and a dielectric layer on the substrate, and a metal layer or the like structure is generally formed in the dielectric layer. In actual processes, a through silicon via (TSV) can be formed in the semiconductor structure to realize vertical interconnection between multiple semiconductor structures. The through silicon via can be formed by a via first process, a via middle process or a via last process. Among them, the conventional via last process generally etches from the lower surface of the substrate to the metal layer in the dielectric layer to form a through hole exposing the metal layer, and then fills a conductive layer in the through hole to connect the conductive layer and the metal layer.

[0003] However, when performing the etching process to form the through hole, damage to the metal layer is easy to occur, which causes the conductive material in the metal layer to diffuse to the surrounding area, thereby reducing the performance of the semiconductor structure. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure, comprising:

[0005] a substrate;

[0006] a first dielectric layer covering an upper surface of the substrate;

[0007] a first conductive layer including at least a first sub-layer, the first sub-layer covering a part of an upper surface of the first dielectric layer;

[0008] a second conductive layer covering the first conductive layer; wherein a diffusion coefficient of the first conductive layer in a solid is less than a diffusion coefficient of the second conductive layer in a solid;

[0009] a conductive via extending from a lower surface opposite to the substrate to the first sub-layer and exposing the first sub-layer.

[0010] In some embodiments, the semiconductor structure further comprises at least one contact hole in the first dielectric layer; the first conductive layer further comprises a second sub-layer and a third sub-layer, the second sub-layer filling the contact hole, and the third sub-layer being on the first dielectric layer and connected to the second sub-layer.

[0011] In some embodiments, an upper surface of the third sub-layer is flush with an upper surface of the first sub-layer, and the first sub-layer and the third sub-layer are arranged separately from each other.

[0012] In some embodiments, the material of the first conductive layer comprises tungsten.

[0013] In some embodiments, the first conductive layer comprises a tungsten layer, the tungsten layer comprising a tungsten seed layer and a tungsten bulk layer covering the tungsten seed layer.

[0014] In some embodiments, the semiconductor structure further comprises: a second dielectric layer on the first dielectric layer, the second dielectric layer having a plurality of openings therein, the plurality of openings comprising at least a first opening, a bottom of the first opening exposing the first sub-layer, the second conductive layer covering the first sub-layer exposed by the first opening and filling the first opening.

[0015] In some embodiments, the plurality of openings further comprises at least a second opening, a bottom of the second opening exposing the third sub-layer, the second conductive layer covering the third sub-layer exposed by the second opening and filling the second opening.

[0016] In some embodiments, the second conductive layer comprises a seed layer and a bulk layer, the seed layer covering sidewalls of the openings and the first sub-layer and the third sub-layer exposed by bottoms of the openings, the bulk layer filling the openings.

[0017] In some embodiments, the semiconductor structure further comprises: a third conductive layer between sidewalls of the second conductive layer and the second dielectric layer; wherein a diffusion coefficient of the third conductive layer in solid is less than a diffusion coefficient of the second conductive layer in solid.

[0018] In some embodiments, the semiconductor structure further comprises: a fourth conductive layer in the conductive via.

[0019] Embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising:

[0020] providing a substrate;

[0021] forming a first dielectric layer on the substrate, the first dielectric layer covering an upper surface of the substrate; forming a first conductive layer, the first conductive layer comprising at least a first sub-layer covering a portion of an upper surface of the first dielectric layer;

[0022] forming a second conductive layer, the second conductive layer covering the first conductive layer; wherein a diffusion coefficient of the first conductive layer in solid is less than a diffusion coefficient of the second conductive layer in solid.

[0023] etching the substrate and the first dielectric layer from a lower surface opposite to the upper surface of the substrate to form a conductive via exposing the first sub-layer.

[0024] In some embodiments, forming the first conductive layer comprises:

[0025] etching the first dielectric layer to form at least one contact hole;

[0026] forming a first conductive material layer, the first conductive material layer filling the contact hole and covering an upper surface of the first dielectric layer; wherein the first conductive material layer filling the contact hole defines a second sub-layer;

[0027] etching a portion of the first conductive material layer covering the upper surface of the first dielectric layer to form the first sub-layer and a third sub-layer, the third sub-layer being on the first dielectric layer and connected to the second sub-layer, the first sub-layer being on a peripheral region of the contact hole.

[0028] In some embodiments, forming the second conductive layer comprises:

[0029] forming a second dielectric layer, the second dielectric layer covering the first sub-layer, the third sub-layer and the first dielectric layer;

[0030] etching the second dielectric layer to form a plurality of openings, the plurality of openings comprising at least one first opening exposing the first sub-layer and at least one second opening exposing the third sub-layer;

[0031] forming a seed material layer, the seed material layer covering sidewalls of the openings, the first sub-layer and the third sub-layer exposed by the openings and an upper surface of the second dielectric layer;

[0032] forming a bulk material layer, the bulk material layer covering the seed material layer and filling the openings;

[0033] removing a portion of the bulk material layer and the seed material layer to a level of an upper surface of the bulk material layer and the seed material layer being flush with an upper surface of the second dielectric layer to form a bulk layer and a seed layer respectively, the seed layer and the bulk layer constituting the second conductive layer.

[0034] In some embodiments, before forming the seed material layer, further comprising:

[0035] forming a third conductive layer, the third conductive layer covering sidewalls of the openings; wherein a diffusion coefficient of the third conductive layer in a solid is less than a diffusion coefficient of the second conductive layer in a solid.

[0036] In some embodiments, after etching the substrate and the first dielectric layer from a lower surface opposite to an upper surface of the substrate to form a conductive via exposing the first sub-layer, further comprising: forming a fourth conductive layer in the conductive via.

[0037] The semiconductor structure and the manufacturing method thereof provided by the embodiments of the present disclosure, wherein the semiconductor structure comprises: a substrate; a first dielectric layer covering an upper surface of the substrate; a first conductive layer comprising at least a first sub-layer, the first sub-layer covering part of the upper surface of the first dielectric layer; a second conductive layer covering the first conductive layer; wherein a diffusion coefficient of the first conductive layer in solid is less than a diffusion coefficient of the second conductive layer in solid; and a conductive via extending from a lower surface opposite to the substrate to the first sub-layer and exposing the first sub-layer. In the embodiments of the present disclosure, the first conductive layer is formed below the second conductive layer, and when the etching process causes damage to the first sub-layer in the process of forming the conductive via, the conductive material in the first conductive layer is difficult to diffuse to the surrounding area due to the diffusion coefficient of the first conductive layer being less than the diffusion coefficient of the second conductive layer, thereby reducing the influence on the semiconductor structure. Meanwhile, due to the protection of the first conductive layer, the etching process causes damage to the second conductive layer is avoided or mitigated. Even if the second conductive layer is exposed and damaged when the conductive via is formed, the conductive material in the second conductive layer is also difficult to diffuse to the surrounding area due to the blocking effect of the first conductive layer.

[0038] The details of one or more embodiments of the present disclosure are presented in the accompanying drawings and description below. Other features and advantages of the present disclosure will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0040] Figure 1 A schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure;

[0041] Figure 2 A schematic diagram of the semiconductor structure provided by another embodiment of the present disclosure;

[0042] Figure 3 A schematic diagram of the semiconductor structure provided by another embodiment of the present disclosure;

[0043] Figure 4 A flow chart of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure;

[0044] Figures 5 to 14 A process flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is provided.

[0045] Figures 15 to 16 A process flow chart of a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure is provided.

[0046] Figures 17 to 18 A process flow chart of a method for manufacturing a semiconductor structure according to yet another embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0047] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be embodied in various forms without being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0048] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate this disclosure. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate this disclosure. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate this disclosure.

[0049] In the drawings, the size of layers, regions, elements, and the relative sizes of the same can be exaggerated for clarity. Like reference numbers in different drawings can indicate the same or similar elements.

[0050] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0051] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] Semiconductor structures, such as memories, usually include a substrate and a dielectric layer on the substrate, and a metal layer or the like structure is usually formed in the dielectric layer. In actual processes, a through silicon via (TSV) can be formed in the semiconductor structure to realize vertical interconnection between a plurality of semiconductor structures. The through silicon via can usually be formed by a via first process, a via middle process or a via last process. Among them, the conventional via last process usually etches from the lower surface of the substrate to the metal layer in the dielectric layer to form a through hole exposing the metal layer, and then fills a conductive layer in the through hole to connect the conductive layer and the metal layer.

[0054] However, when the etching process is performed to form the through hole, the metal layer is easily damaged, causing the conductive material in the metal layer to diffuse to the surrounding area, reducing the performance of the semiconductor structure.

[0055] Based on this, the following technical scheme of the embodiments of the present disclosure is proposed:

[0056] The semiconductor structure provided by the embodiments of the present disclosure includes: a substrate; a first dielectric layer covering the upper surface of the substrate; a first conductive layer including at least a first sub-layer, the first sub-layer covering part of the upper surface of the first dielectric layer; a second conductive layer covering the first conductive layer; wherein the diffusion coefficient of the first conductive layer in a solid is less than the diffusion coefficient of the second conductive layer in a solid; and a conductive via extending from the lower surface opposite to the substrate to the first sub-layer and exposing the first sub-layer.

[0057] In the embodiments of the present disclosure, the first conductive layer is formed below the second conductive layer. In the process of forming the conductive via, when the etching process damages the first conductive layer, since the diffusion coefficient of the first conductive layer is less than that of the second conductive layer, the conductive material in the first conductive layer is difficult to diffuse to the surrounding area, reducing the influence on the semiconductor structure. At the same time, due to the protection of the first conductive layer, the damage of the etching process to the second conductive layer is avoided or reduced. Even if the second conductive layer is exposed and damaged when the conductive via is formed, due to the blocking effect of the first conductive layer, the conductive material in the second conductive layer is also difficult to diffuse to the surrounding area.

[0058] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of the present disclosure, the schematic diagram will be partially enlarged without general proportion for the convenience of description, and the schematic diagram is only an example, which should not limit the protection scope of the present disclosure herein.

[0059] Figure 1 The schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure is shown in the following figure: Figure 2A schematic diagram of a semiconductor structure according to another embodiment of the present disclosure is provided. Figure 3 A schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure is provided. The following description is made in conjunction with Figures 1 to 3 The method of manufacturing the semiconductor structure according to the embodiments of the present disclosure is further described in detail.

[0060] Optionally, the semiconductor structure according to the embodiments of the present disclosure can be a dynamic random access memory (DRAM), but is not limited thereto, and can be any semiconductor structure.

[0061] As shown, the semiconductor structure includes a substrate 10, a first dielectric layer 13 covering an upper surface of the substrate 10, a first conductive layer 14 including at least a first sub-layer 141 covering a portion of the upper surface of the first dielectric layer 13, a second conductive layer 16 covering the first conductive layer 14, wherein the first conductive layer 14 has a diffusion coefficient in a solid that is less than a diffusion coefficient in a solid of the second conductive layer 16, and a conductive via T extending from a lower surface opposite the substrate 10 to the first sub-layer 141 and exposing the first sub-layer 141.

[0062] The substrate can be a semiconductor substrate and can include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II- VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the substrate is a silicon substrate, which can be doped or undoped.

[0063] Optionally, the substrate 10 has device structures such as word lines, bit lines, memory arrays, peripheral circuits, etc. formed thereon. In one embodiment, a transistor 12 is formed on the substrate 10, which includes a gate 121 covering a portion of the upper surface of the substrate 10, a gate dielectric layer 122 between the gate 121 and the substrate 10, and source / drain doped regions 123 on both sides of the gate 121. In some embodiments, an isolation structure 11 is also formed in the substrate 10, which can be a shallow trench isolation structure for electrically isolating the transistor 12 from other device structures in the substrate 10.

[0064] The first dielectric layer 13 covers the upper surface of the substrate 10 and covers device structures (e.g., the transistor 12) formed on the substrate 10. The material of the first dielectric layer 13 can be an oxide, for example, silicon oxide.

[0065] In an embodiment, the semiconductor structure further comprises at least one contact hole V in the first dielectric layer 13; the first conductive layer 14 further comprises a second sub-layer 142 and a third sub-layer 143, the second sub-layer 142 fills the contact hole V, and the third sub-layer 143 is located on the first dielectric layer 13 and connected to the second sub-layer 142. In some embodiments, the upper surface of the third sub-layer 143 is flush with the upper surface of the first sub-layer 141, and the first sub-layer 141 and the third sub-layer 143 are arranged separately from each other.

[0066] In an embodiment, the third sub-layer 143 is electrically connected to the device structure on the substrate 10 through the second sub-layer 142 in the contact hole V to transmit an electrical signal to the device structure. In a specific embodiment, the bottom of the contact hole V exposes the source / drain doped region 123 of the transistor 12, and the third sub-layer 143 is electrically connected to the source / drain doped region 123 through the second sub-layer 142 in the contact hole V.

[0067] In some embodiments, the contact hole can further have at least one metal layer and at least one contact plug located in the first dielectric layer and alternately distributed in a direction perpendicular to the substrate plane, and the third sub-layer is electrically connected to the device structure on the substrate through the second sub-layer and the alternately distributed at least one metal layer and at least one contact plug.

[0068] Optionally, the first conductive layer 14 can be formed in the following manner: first, etching the first dielectric layer 13 to form at least one contact hole V; then, forming a material layer of the first conductive layer 14, the material layer of the first conductive layer 14 filling the contact hole V and covering the upper surface of the first dielectric layer 13; wherein the material layer of the first conductive layer 14 filling the contact hole V defines the second sub-layer 142; then, etching the part of the material layer of the first conductive layer 14 covering the upper surface of the first dielectric layer 13 to form the first sub-layer 141 and the third sub-layer 143, the third sub-layer 143 being located on the first dielectric layer 13 and connected to the second sub-layer 142, and the first sub-layer 141 being located in the peripheral region of the contact hole V. In the embodiment of the present disclosure, the first sub-layer 141, the second sub-layer 142 and the third sub-layer 143 are formed in the same step, simplifying the process.

[0069] In an embodiment, the semiconductor structure further comprises a second dielectric layer 15 on the first dielectric layer 13, the second dielectric layer 15 having a plurality of openings S therein, the plurality of openings S comprising at least one first opening S1, the bottom of the first opening S1 exposing the first sub-layer 141, and the second conductive layer 16 covering the first sub-layer 141 exposed by the first opening S1 and filling the first opening S1

[0070] In one embodiment, the plurality of openings S further comprises at least one second opening S2, a bottom of the second opening S2 exposes the third sub-layer 143, and the second conductive layer 16 covers the third sub-layer 143 exposed by the second opening S2 and fills the second opening S2.

[0071] In one embodiment, the second conductive layer 16 comprises a seed layer 161 and a bulk layer 162, the seed layer 161 covers the sidewalls of the openings S and the first sub-layer 141 and the third sub-layer 143 exposed by the bottoms of the openings S, and the bulk layer 162 fills the openings S. Alternatively, the second conductive layer 16 can be formed in the following manner: first, a second dielectric layer 15 is formed, the second dielectric layer 15 covers the first sub-layer 141, the third sub-layer 143 and the first dielectric layer 13; then, the second dielectric layer 15 is etched to form a plurality of openings S exposing the first conductive layer 14; then, a material layer of the seed layer 161 is formed, the material layer of the seed layer 161 covers the inner walls of the openings S and the upper surface of the second dielectric layer 15; then, a material layer of the bulk layer 162 is formed, the material layer of the bulk layer 162 covers the material layer of the seed layer 161 and fills the openings S; then, part of the material layer of the bulk layer 162 and the material layer of the seed layer 161 are removed until the upper surfaces of the material layer of the bulk layer 162 and the material layer of the seed layer 161 are flush with the upper surface of the second dielectric layer 15, to form the bulk layer 162 and the seed layer 161 respectively, the seed layer 161 and the bulk layer 162 constitute the second conductive layer 16.

[0072] The material of the second dielectric layer 15 can be the same as or different from the material of the first dielectric layer 13. In one specific embodiment, the material of the second dielectric layer 15 is the same as the material of the first dielectric layer 13, and both are oxides. The material of the second conductive layer 16 comprises copper.

[0073] The conductive via T is formed by etching the substrate 10 and the first dielectric layer 13 from the lower surface opposite the upper surface of the substrate 10 towards the first sublayer 141. In one embodiment, the bottom surface of the conductive via T exposes the first sublayer 141, while the first sublayer 141 still covers the lower surface of the second conductive layer 16. However, it is not limited to this; the conductive via T may also penetrate the first sublayer 141 and expose the second conductive layer 16. In this embodiment, a first conductive layer 14 is formed below the second conductive layer 16. During the process of forming the conductive via T, when the etching process damages the first sub-layer 141 of the first conductive layer 14, the conductive material in the first sub-layer 141 is difficult to diffuse into the surrounding area, especially the substrate 10 below it, because the diffusion coefficient of the first conductive layer 14 in the solid is less than that of the second conductive layer 16 in the solid, thus reducing the impact on the semiconductor structure. Simultaneously, the protection of the first sub-layer 141 avoids or mitigates damage to the second conductive layer 16 caused by the etching process. Furthermore, even if the second conductive layer 16 is exposed and damaged during the formation of the conductive via T, the conductive material in the second conductive layer 16 is difficult to diffuse into the surrounding area due to the protection and blocking effect of the first sub-layer 141, thus expanding the process window for forming the conductive via T. Simultaneously, due to the blocking effect of the first conductive layer 14, the conductive material in the second conductive layer 16 is also difficult to diffuse into the surrounding area during the formation of the second conductive layer 16.

[0074] Here, the diffusion coefficient of the first conductive layer and the second conductive layer refers to the diffusion coefficient of the first conductive layer and the second conductive layer in the same solid, which can be a semiconductor material, such as silicon.

[0075] In one embodiment, the material of the first conductive layer 14 includes tungsten, which has a small diffusion coefficient in solids and is difficult to diffuse into the surrounding area, thus reducing the impact on the semiconductor structure.

[0076] The first conductive layer 14 can have a single-layer or multi-layer structure. For example... Figure 1 As shown, in one embodiment, the first conductive layer 14 includes a tungsten layer L2, which includes a tungsten seed layer L21 and a tungsten body layer L22 covering the tungsten seed layer L21. Specifically, the tungsten seed layer L21 covers the inner wall of the contact hole V and part of the upper surface of the first dielectric layer 13, and the tungsten body layer L22 covers the tungsten seed layer L21 and fills the contact hole V. The tungsten body layer L22 can be formed by performing processes such as electroplating, electroless plating, or sputtering on the tungsten seed layer L21.

[0077] like Figure 2As shown, in one embodiment, the first conductive layer 14 further includes a titanium nitride layer L1, and a tungsten layer L2 covers the titanium nitride layer L1. Specifically, the titanium nitride layer L1 covers the sidewalls and bottom surface of the contact hole V, as well as part of the upper surface of the first dielectric layer 13, and the tungsten layer L2 covers the titanium nitride layer L1 and fills the contact hole V. However, it is not limited to this; in some embodiments, the titanium nitride layer L1 may also fill the contact hole V and cover part of the upper surface of the first dielectric layer 13, and the tungsten layer L2 may cover the titanium nitride layer L1.

[0078] In this embodiment, a titanium nitride layer L1 and a tungsten layer L2 are used as the first conductive layer 14, which can increase the adhesion between the first conductive layer 14 and the first dielectric layer 13 and improve the performance of the semiconductor structure. Optionally, the ratio of the thickness of the titanium nitride layer L1 to the thickness of the tungsten layer L2 in the first sub-layer 141 is in the range of 0.1-0.5, for example, 0.1, 0.2, 0.3, 0.4, 0.5, which has both good adhesion and barrier effect, and helps to improve the performance of the device structure.

[0079] like Figure 3 As shown, in one embodiment, the semiconductor structure further includes a third conductive layer 19, which is located between the sidewall of the second conductive layer 16 and the second dielectric layer 15. The diffusion coefficient of the third conductive layer 19 in the solid is less than that of the second conductive layer 16 in the solid. Here, the diffusion coefficients of the third conductive layer 19 and the second conductive layer 16 refer to the diffusion coefficients of the third conductive layer 19 and the second conductive layer 16 in the same solid, which can be a semiconductor material, such as silicon. In this embodiment, the third conductive layer 19 is formed between the sidewall of the second conductive layer 16 and the second dielectric layer 15. Due to the protective effect of the third conductive layer 19, the diffusion of conductive material in the second conductive layer 16 to the surrounding area can be further avoided or mitigated. Simultaneously, the smaller diffusion coefficient of the third conductive layer 19 makes it difficult for the third conductive layer 19 itself to diffuse to the surrounding area, reducing its impact on the performance of the semiconductor structure.

[0080] The third conductive layer 19 may have a single-layer or multi-layer structure. In one embodiment, the third conductive layer 19 may be a tungsten layer, which may include a tungsten seed layer and a tungsten body layer covering the tungsten seed layer. In some embodiments, the third conductive layer 19 may also be a combination of a tungsten layer and a titanium nitride layer, with the tungsten layer located between the titanium nitride layer and the second conductive layer 16. However, it is not limited to this; any material that meets the above-described conditions regarding the diffusion coefficient can be used as the material of the third conductive layer 19.

[0081] like Figures 1 to 3As shown, in an embodiment, the semiconductor structure further comprises a fourth conductive layer 18 located in the conductive via T. The fourth conductive layer 18 is used to transmit signals between different semiconductor structures. In some embodiments, the semiconductor structure further comprises an insulating layer 17 covering the sidewall of the conductive via T, used to electrically isolate the substrate 10 and the fourth conductive layer 18. The material of the fourth conductive layer 18 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof, such as copper and titanium nitride. The material of the insulating layer 17 includes oxide, for example, silicon oxide.

[0082] The embodiments of the present disclosure further provide a manufacturing method of a semiconductor structure, as shown in Figure 4 As shown, the manufacturing method comprises the following steps:

[0083] Step S101, providing a substrate;

[0084] Step S102, forming a first dielectric layer on the substrate, the first dielectric layer covering the upper surface of the substrate;

[0085] Step S103, forming a first conductive layer, the first conductive layer at least comprising a first sub-layer covering part of the upper surface of the first dielectric layer;

[0086] Step S104, forming a second conductive layer, the second conductive layer covering the first conductive layer; wherein the diffusion coefficient of the first conductive layer in solid is less than the diffusion coefficient of the second conductive layer in solid;

[0087] Step S105, etching the substrate and the first dielectric layer from the lower surface opposite to the upper surface of the substrate to the first sub-layer, to form a conductive via exposing the first sub-layer.

[0088] Figures 5 to 14 A process flow chart of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure is shown in Figures 15 to 16 A process flow chart of the manufacturing method of the semiconductor structure provided by another embodiment of the present disclosure is shown in

[0089] Figures 17 to 18 A process flow chart of the manufacturing method of the semiconductor structure provided by yet another embodiment of the present disclosure is shown in Figures 5 to 18 The manufacturing method of the semiconductor structure of the embodiments of the present disclosure is further explained in detail.

[0090] First, step S101 is performed, as shown in Figure 5 The substrate 10 is provided.

[0091] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0092] Optionally, the substrate 10 has device structures such as word lines, bit lines, memory arrays, and peripheral circuits. In one specific embodiment, a transistor 12 is formed on the substrate 10. The transistor 12 includes a gate 121 covering a portion of the upper surface of the substrate 10, a gate dielectric layer 122 located between the gate 121 and the substrate 10, and source / drain doped regions 123 located on both sides of the gate 121. In some embodiments, an isolation structure 11 is also formed within the substrate 10. The isolation structure 11 can be, for example, a shallow trench isolation structure, for electrically isolating the transistor 12 from other device structures within the substrate 10.

[0093] Next, proceed to step S102, as follows: Figure 6 As shown, a first dielectric layer 13 is formed on the substrate 10, and the first dielectric layer 13 covers the upper surface of the substrate 10.

[0094] The first dielectric layer 13 covers the upper surface of the substrate 10 and the device structure (such as transistor 12) located on the substrate 10. In practice, the first dielectric layer 13 can be formed on the substrate 10 using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The material of the first dielectric layer 13 can be an oxide, such as silicon oxide.

[0095] Next, proceed to step S103, as follows: Figures 7 to 9 As shown, a first conductive layer 14 is formed, and the first conductive layer 14 includes at least a first sublayer 141 covering a portion of the upper surface of the first dielectric layer 13.

[0096] Specifically, forming the first conductive layer 14 includes:

[0097] The first dielectric layer 13 is etched to form at least one contact hole V;

[0098] A first conductive material layer 14′ is formed, which fills the contact hole V and covers the upper surface of the first dielectric layer 13; wherein, the first conductive material layer 14′ that fills the contact hole V is defined as the second sublayer 142.

[0099] The first conductive material layer 14' covering the upper surface of the first dielectric layer 13 is etched to form the first sub-layer 141 and the third sub-layer 143, the third sub-layer 143 is located on the first dielectric layer 13 and connected with the second sub-layer 142, and the first sub-layer 141 is located in the peripheral region of the contact hole V.

[0100] Before etching the first conductive material layer 14' covering the upper surface of the first dielectric layer 13, a patterned mask layer (not shown) can also be formed on the first conductive material layer 14', and then the first conductive material layer 14' is etched with the patterned mask layer (not shown) as a mask. The material of the patterned mask layer (not shown) can be a negative photoresist.

[0101] In an embodiment, the material of the first conductive layer 14 includes tungsten, which has a small diffusion coefficient in a solid and is difficult to diffuse to the peripheral region by itself, thereby reducing its impact on the semiconductor structure.

[0102] The first conductive layer 14 can have a single-layer or multi-layer structure. In an embodiment, the first conductive layer 14 includes a tungsten layer L2, which includes a tungsten seed layer L21 and a tungsten bulk layer L22 covering the tungsten seed layer L21. Again referring to Figures 8 to 9 The first conductive layer 14 is formed by: forming a tungsten seed layer L21 covering the inner wall of the contact hole V and the upper surface of the first dielectric layer 13; forming a tungsten bulk layer L22 covering the tungsten seed layer L21 and filling the contact hole V, the tungsten seed layer L21 and the tungsten bulk layer L22 located in the contact hole V constitute the second sub-layer 142; etching the tungsten bulk layer L22 and the tungsten seed layer L21 covering the upper surface of the first dielectric layer 13 to form the first sub-layer 141 and the third sub-layer 143, respectively. The tungsten bulk layer L22 and the tungsten seed layer L21 can be formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, etc. For example, the tungsten seed layer L21 is first formed by a chemical vapor deposition process, and then the tungsten bulk layer L22 is formed by an electroplating process.

[0103] In some embodiments, the upper surface of the third sub-layer 143 is flush with the upper surface of the first sub-layer 141, and the first sub-layer 141 and the third sub-layer 143 are arranged separately from each other. In the embodiments of the present disclosure, the first sub-layer 141, the second sub-layer 142 and the third sub-layer 143 are formed in the same step, which simplifies the process.

[0104] The third sub-layer 143 is electrically connected with the device structure on the substrate 10 through the second sub-layer 142 located in the contact hole V, and is used for transmitting electrical signals to the device structure. In a specific embodiment, the bottom of the contact hole V exposes the source / drain doped region 123 of the transistor 12, and the third sub-layer 143 is electrically connected with the source / drain doped region 123 of the transistor 12 on the substrate 10 through the second sub-layer 142 located in the contact hole V.

[0105] In some embodiments, before forming the contact hole, at least one metal layer and at least one contact plug can also be formed in the first dielectric layer, the at least one metal layer and the at least one contact plug are alternately distributed along the direction perpendicular to the substrate plane, and the third sub-layer is electrically connected with the device structure on the substrate through the second sub-layer and the alternately distributed at least one metal layer and at least one contact plug.

[0106] Next, step S104 is performed, as shown in Figures 10 to 13 , a second conductive layer 16 is formed, the second conductive layer 16 covers the first conductive layer 14; wherein the diffusion coefficient of the first conductive layer 14 in a solid is less than the diffusion coefficient of the second conductive layer 16 in a solid.

[0107] Specifically, forming the second conductive layer 16 includes:

[0108] A second dielectric layer 15 is formed, the second dielectric layer 15 covers the first sub-layer 141, the third sub-layer 143 and the first dielectric layer 13 (as shown in Figure 10 );

[0109] The second dielectric layer 15 is etched to form a plurality of openings S exposing the first conductive layer 14, the plurality of openings S include at least one first opening S1 exposing the first sub-layer 141, and at least one second opening S2 exposing the third sub-layer 143 (as shown in Figure 11 );

[0110] A seed material layer 161' is formed, the seed material layer 161' covers the sidewalls of the openings S, the first sub-layer 141 and the third sub-layer 143 exposed by the openings S, and the upper surface of the second dielectric layer 15;

[0111] A bulk material layer 162' is formed, the bulk material layer 162' covers the seed material layer 161' and fills the openings S;

[0112] Part of the bulk material layer 162' and the seed material layer 161' are removed to the upper surfaces of the bulk material layer 162' and the seed material layer 161' flush with the upper surface of the second dielectric layer 15, to form a bulk layer 162 and a seed layer 161 respectively, the seed layer 161 and the bulk layer 162 constitute the second conductive layer 16.

[0113] Here, the second dielectric layer 15 can be formed using a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or the like. The material of the second dielectric layer 15 can be the same as or different from the material of the first dielectric layer 13. In one embodiment, the material of the second dielectric layer 15 is the same as the material of the first dielectric layer 13, and both are oxides, such as silicon oxide.

[0114] The seed material layer 161' and the bulk material layer 162' can be formed using a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, electroplating, electroless plating, sputtering, or the like. For example, the seed material layer 161' can be formed first by a chemical vapor deposition process, and then the bulk material layer 162' can be formed by an electroplating process. The materials of the first bulk material layer 162' and the seed material layer 161' include copper.

[0115] In the embodiments of the present disclosure, the first conductive layer 14 is formed below the second conductive layer 16, and the diffusion coefficient of the first conductive layer 14 in a solid is less than the diffusion coefficient of the second conductive layer 16 in the solid. Due to the protection and blocking effect of the first conductive layer 14, the conductive material in the second conductive layer 16 is difficult to diffuse to the surrounding area when the second conductive layer 16 is formed.

[0116] The substrate 10 and the first dielectric layer 13 will be etched later to form a conductive via T (see Figure 14 ) below the first sub-layer 141. In the embodiments of the present disclosure, when the etching process causes damage to the first sub-layer 141 in the process of forming the conductive via T (see Figure 14 ), the conductive material in the first conductive layer 14 is difficult to diffuse to the surrounding area due to the diffusion coefficient of the first conductive layer 14 in a solid being less than the diffusion coefficient of the second conductive layer 16 in the solid, which reduces the impact on the semiconductor structure; at the same time, the damage to the second conductive layer 16 caused by the etching process is avoided or reduced due to the protection of the first conductive layer 14. Here, the diffusion coefficients of the first conductive layer 14 and the second conductive layer 16 refer to the diffusion coefficients of the first conductive layer 14 and the second conductive layer 16 in the same solid, which can be a semiconductor material, such as silicon.

[0117] Next, step S105 is performed, as shown in Figure 14 , the substrate 10 and the first dielectric layer 13 are etched from the lower surface opposite to the upper surface of the substrate 10 to the first sub-layer 141 to form a conductive via T exposing the first sub-layer 141.

[0118] In one embodiment, the bottom surface of the conductive via T exposes the first sublayer 141, which still covers the surface of the second conductive layer 16. However, it is not limited to this; the conductive via T can also penetrate the first sublayer 141 and expose the second conductive layer 16. In this embodiment, due to the protective and blocking effect of the first sublayer 141, even if the second conductive layer 16 is exposed and damaged during the formation of the conductive via T, the conductive material in the second conductive layer 16 is difficult to diffuse to the surrounding area, thus expanding the process window for forming the conductive via T.

[0119] like Figure 1 As shown, in one embodiment, after etching the substrate 10 and the first dielectric layer 13 from the lower surface opposite to the upper surface of the substrate 10 toward the first sublayer 141 to form a conductive via T exposing the first sublayer 141, the method further includes forming a fourth conductive layer 18 within the conductive via T. The fourth conductive layer 18 is used to transmit signals between different semiconductor structures.

[0120] See you again Figure 1 In one embodiment, before forming the fourth conductive layer 18, the method further includes forming an insulating layer 17 within the conductive via T, the insulating layer 17 covering the sidewall of the conductive via T, for electrically isolating the substrate 10 and the fourth conductive layer 18.

[0121] Here, the fourth conductive layer 18 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, and sputtering. The materials for the fourth conductive layer 18 include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, metal alloys, or any combination thereof, such as copper and titanium nitride. The material for the insulating layer 17 includes oxides, such as silicon oxide.

[0122] Figure 9 The first conductive layer 14 shown includes a tungsten layer L2. However, it is not limited to this, such as... Figures 15 to 16 As shown, in another embodiment of this disclosure, the first conductive layer 14 further includes a titanium nitride layer L1, and a tungsten layer L2 covers the titanium nitride layer L1.

[0123] Specifically, forming the first conductive layer 14 includes:

[0124] A titanium nitride layer L1 is formed, which covers the sidewalls and bottom surface of the contact hole V and the upper surface of the first dielectric layer 13; a tungsten layer L2 is formed, which covers the titanium nitride layer L1 and fills the contact hole V; wherein, the tungsten layer L2 and the titanium nitride layer L1 located in the contact hole V are defined as the second sublayer 142.

[0125] The tungsten layer L2 and the titanium nitride layer L1 are etched to cover a portion of the upper surface of the first dielectric layer 13 to form a first sublayer 141 and a third sublayer 143. The third sublayer 143 is located on the first dielectric layer 13 and connected to the second sublayer 142. The first sublayer 141 is located in the peripheral region of the contact hole V.

[0126] However, this is not the only embodiment. In some embodiments, the titanium nitride layer L1 may also fill the contact hole V and cover the upper surface of the first dielectric layer 13, and the tungsten layer L2 may cover the titanium nitride layer L1.

[0127] In this embodiment, a titanium nitride layer L1 and a tungsten layer L2 are used as the first conductive layer 14, which can increase the adhesion between the first conductive layer 14 and the first dielectric layer 13 and improve the performance of the semiconductor structure. Optionally, the ratio of the thickness of the titanium nitride layer L1 to the thickness of the tungsten layer L2 in the first sub-layer 141 is in the range of 0.1-0.5, for example, 0.1, 0.2, 0.3, 0.4, 0.5, which has both good adhesion and barrier effect, and helps to improve the performance of the device structure.

[0128] Next, in Figure 16 Based on this, steps S104 and S105 are executed to finally form the following... Figure 2 The semiconductor structure shown.

[0129] like Figure 17 As shown, in another embodiment of this disclosure, before forming the seed material layer 161', the method further includes: forming a third conductive layer 19, the third conductive layer 19 covering the sidewall of the opening S; wherein the diffusion coefficient of the third conductive layer 19 in the solid is less than the diffusion coefficient of the second conductive layer 16 in the solid. Here, the diffusion coefficients of the third conductive layer 19 and the second conductive layer 16 refer to the diffusion coefficients of the third conductive layer 19 and the second conductive layer 16 in the same solid, which can be a semiconductor material, such as silicon.

[0130] Next, as Figure 18 As shown, a second conductive layer 16 is formed in the opening S, and a third conductive layer 19 is located between the sidewalls of the second dielectric layer 15 and the second conductive layer 16.

[0131] In this embodiment of the present disclosure, a third conductive layer 19 is formed between the sidewall of the second conductive layer 16 and the second dielectric layer 15. Due to the protective effect of the third conductive layer 19, the diffusion of conductive material in the second conductive layer 16 to the surrounding area can be further avoided or mitigated. At the same time, the diffusion coefficient of the third conductive layer 19 is smaller than that of the second conductive layer 16, and the third conductive layer 19 itself is difficult to diffuse to the surrounding area, thereby reducing its impact on the performance of the semiconductor structure.

[0132] Here, the third conductive layer 19 can be formed using a process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, or the like. The third conductive layer 19 can have a single-layer or multi-layer structure. In one embodiment, the third conductive layer 19 can be a tungsten layer, which can include a tungsten seed layer and a tungsten bulk layer covering the tungsten seed layer. In some embodiments, the third conductive layer 19 can also be a combination of a tungsten layer and a titanium nitride layer, with the tungsten layer being located between the titanium nitride layer and the second conductive layer 16. However, the material of the third conductive layer 19 is not limited to this, and any material that satisfies the conditions described above with respect to the diffusion coefficient can be used as the material of the third conductive layer 19.

[0133] Next, on the basis of the semiconductor structure shown in FIG. 6, step S105 is continued to finally form a semiconductor structure as shown in FIG. 7. Figure 18 Figure 3

[0134] It should be noted that the sequence of the above steps can be changed by those skilled in the art without departing from the scope of the present disclosure, and the above is only an optional embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, and improvement within the spirit and principle of the present disclosure shall be included in the scope of the present disclosure.​​

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A first dielectric layer covers the upper surface of the substrate; The first conductive layer includes at least a first sublayer, the first sublayer covering a portion of the upper surface of the first dielectric layer; A second conductive layer covers the first conductive layer; wherein the diffusion coefficient of the first conductive layer in the solid is less than the diffusion coefficient of the second conductive layer in the solid; A conductive via, the conductive via extending from a lower surface opposite the substrate to the first sublayer and exposing the first sublayer; The first conductive layer is used to mitigate the damage to the second conductive layer caused by the etching process that forms the conductive via.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: at least one contact hole located within the first dielectric layer; the first conductive layer further includes a second sublayer and a third sublayer, the second sublayer filling the contact hole, and the third sublayer located on the first dielectric layer and connected to the second sublayer.

3. The semiconductor structure according to claim 2, characterized in that, The upper surface of the third sub-layer is flush with the upper surface of the first sub-layer, and the first sub-layer and the third sub-layer are set separately from each other.

4. The semiconductor structure according to claim 1, characterized in that, The material of the first conductive layer includes tungsten.

5. The semiconductor structure according to claim 4, characterized in that, The first conductive layer includes a tungsten layer, which includes a tungsten seed layer and a tungsten body layer covering the tungsten seed layer.

6. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes: a second dielectric layer located on the first dielectric layer, the second dielectric layer having a plurality of openings, the plurality of openings including at least one first opening, the bottom of the first opening exposing the first sublayer, and the second conductive layer covering the first sublayer exposed by the first opening and filling the first opening.

7. The semiconductor structure according to claim 6, characterized in that, The plurality of openings also include at least one second opening, the bottom of which exposes the third sublayer, and the second conductive layer covers the third sublayer exposed by the second opening and fills the second opening.

8. The semiconductor structure according to claim 7, characterized in that, The second conductive layer includes a seed layer and a main layer. The seed layer covers the sidewalls of the opening and the first and third sub-layers exposed at the bottom of the opening. The main layer fills the opening.

9. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure further includes: a third conductive layer, which is located between the sidewall of the second conductive layer and the second dielectric layer; wherein the diffusion coefficient of the third conductive layer in the solid is less than the diffusion coefficient of the second conductive layer in the solid.

10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a fourth conductive layer located within the conductive via.

11. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; A first dielectric layer is formed on the substrate, the first dielectric layer covering the upper surface of the substrate; A first conductive layer is formed, the first conductive layer including at least a first sublayer covering a portion of the upper surface of the first dielectric layer; A second conductive layer is formed, which covers the first conductive layer; wherein the diffusion coefficient of the first conductive layer in the solid is less than the diffusion coefficient of the second conductive layer in the solid; The substrate and the first dielectric layer are etched from the lower surface opposite the upper surface of the substrate toward the first sublayer to form a conductive via exposing the first sublayer.

12. The manufacturing method according to claim 11, characterized in that, Forming a first conductive layer includes: The first dielectric layer is etched to form at least one contact hole; A first conductive material layer is formed, which fills the contact hole and covers the upper surface of the first dielectric layer; wherein the first conductive material layer filling the contact hole is defined as a second sublayer. The portion of the first conductive material layer covering the upper surface of the first dielectric layer is etched to form a first sublayer and a third sublayer. The third sublayer is located on the first dielectric layer and connected to the second sublayer. The first sublayer is located in the peripheral region of the contact hole.

13. The manufacturing method according to claim 12, characterized in that, Forming a second conductive layer includes: A second dielectric layer is formed, which covers the first sublayer, the third sublayer, and the first dielectric layer. The second dielectric layer is etched to form a plurality of openings, the plurality of openings including at least one first opening exposing the first sublayer and at least one second opening exposing the third sublayer; A seed material layer is formed, which covers the sidewall of the opening, the first sub-layer and the third sub-layer exposed by the opening, and the upper surface of the second dielectric layer; A main material layer is formed, which covers the seed material layer and fills the opening; Part of the main material layer and the seed material layer are removed until the upper surfaces of the main material layer and the seed material layer are flush with the upper surface of the second dielectric layer, so as to form a main layer and a seed layer respectively, wherein the seed layer and the main layer constitute the second conductive layer.

14. The manufacturing method according to claim 13, characterized in that, Before forming the seed crystal material layer, the method further includes: A third conductive layer is formed, which covers the sidewall of the opening; wherein the diffusion coefficient of the third conductive layer in the solid is less than the diffusion coefficient of the second conductive layer in the solid.

15. The manufacturing method according to claim 11, characterized in that, After etching the substrate and the first dielectric layer from the lower surface opposite to the upper surface of the substrate toward the first sublayer to form a conductive via exposing the first sublayer, the method further includes: A fourth conductive layer is formed within the conductive via.

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