An array substrate and a display device

Abstract

Embodiments of the present application disclose an array substrate and a display device. Among them, the array substrate includes a display area, a non-display area, a substrate, signal lines, a first connection line, a second connection line, a third connection line, and pads. The non-display area includes a first non-display area; the signal lines are located on one side of the substrate and in the display area, and the signal lines include a first signal line and a second signal line; the first connection line is located on one side of the substrate and in the display area; the second connection line, the third connection line, and the pads are located on one side of the substrate and in the first non-display area; the first signal line is electrically connected to the pads through the first connection line and the third connection line; the second signal line is electrically connected to the pads through the second connection line; the second connection line includes a first sub-connection line, and the extending direction of the first sub-connection line intersects with the plane where the substrate is located. It can be seen that by providing the first sub-connection line with an extending direction intersecting with the substrate, the length of the second connection line is increased, and the problem of uneven display is avoided in the embodiments of the present application.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Art

[0002] As products advance, the demand for narrow or even borderless bezels is becoming more and more urgent. Among them, the lower bezel of the screen has many connecting lines, which takes up a lot of space. At present, in order to reduce the space of the lower bezel, the connecting lines of the lower bezel are generally designed in the display area to reduce the space of the lower bezel.

[0003] However, the connecting wires designed in the display area need to be wound to connect with the signal wires in the display area, which will cause the length of some connecting wires to be significantly longer than the length of other connecting wires, thereby causing obvious differences in the lengths of the connecting wires, thereby causing obvious differences in the resistances of the connecting wires, and thus easily causing the problem of uneven display of the display panel. Summary of the invention

[0004] In view of this, embodiments of the present application disclose an array substrate and a display device, which reduce the resistance difference between connecting lines and avoid the problem of uneven display of the display panel.

[0005] The technical solutions provided by the embodiments of this application are as follows:

[0006] A first aspect of an embodiment of the present application provides an array substrate, including:

[0007] A display area and a non-display area at least partially surrounding the display area, the non-display area including a first non-display area;

[0008] substrate;

[0009] A signal line, located at one side of the substrate and located in the display area, the signal line comprising a first signal line and a second signal line;

[0010] A first connecting line, located at one side of the substrate and located in the display area;

[0011] A second connecting line, a third connecting line and a pad are located at one side of the substrate and in the first non-display area;

[0012] The first signal line is electrically connected to the pad through the first connection line and the third connection line;

[0013] The second signal line is electrically connected to the pad through the second connecting line;

[0014] The second connection line includes a first sub-connection line, and an extension direction of the first sub-connection line intersects with a plane where the substrate is located.

[0015] In a second aspect of the present application, a display device is provided, including an array substrate as described in any one of the above first aspects.

[0016] As can be seen from the above technical solutions, embodiments of the present application disclose an array substrate and a display device. The array substrate includes a display area, at least a part of a non-display area surrounding the display area, a substrate, signal lines, a first connection line, a second connection line, a third connection line, and pads. The non-display area includes a first non-display area; the signal lines are located on one side of the substrate and in the display area, and the signal lines include a first signal line and a second signal line; the first connection line is located on one side of the substrate and in the display area; the second connection line, the third connection line, and the pads are located on one side of the substrate and in the first non-display area; the first signal line is electrically connected to the pad through the first connection line and the third connection line; the second signal line is electrically connected to the pad through the second connection line; the second connection line includes a first sub-connection line, and the extending direction of the first sub-connection line intersects with the plane where the substrate is located. It can be seen that by setting the first sub-connection line whose extending direction intersects with the substrate, compared with the connection lines that are substantially parallel to the substrate in the prior art, the length of the second connection line is increased, so that the difference between the length of the second connection line and the sum of the lengths of the first connection line and the third connection line is reduced, thereby reducing the length difference between the connection lines, further reducing the resistance difference between the connection lines, and avoiding the problem of uneven display of the picture on the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the disclosed drawings without creative efforts.

[0018] Figure 1 FIG. 13 is a schematic structural diagram of an array substrate disclosed in the prior art;

[0019] Figure 2 FIG. 17 is a schematic structural diagram of an array substrate disclosed in an embodiment of the present application;

[0020] Figure 3 FIG. 23 is a sectional view at the position of the middle tangent line B-B' disclosed in an embodiment of the present application; Figure 2 FIG. 23 is a sectional view at the position of the middle tangent line B-B' disclosed in an embodiment of the present application;

[0021] Figure 4 FIG. 29 is a sectional view at the position of the middle tangent line A-A' disclosed in the prior art; Figure 1 FIG. 29 is a sectional view at the position of the middle tangent line A-A' disclosed in the prior art;

[0022] Figure 5 FIG. 55 is another sectional view disclosed in an embodiment of the present application; Figure 2Cross-sectional view at the position of the median tangent B-B’;

[0023] Figure 6 Another one disclosed in the embodiments of the present application Figure 2 Cross-sectional view at the position of the median tangent B-B’;

[0024] Figure 7 A pixel circuit diagram in the array substrate disclosed in the embodiments of the present application;

[0025] Figure 8 Another one disclosed in the embodiments of the present application Figure 2 Cross-sectional view at the position of the median tangent B-B’;

[0026] Figure 9 Schematic diagram of the positions of a raised portion and a spaced portion disclosed in the embodiments of the present application;

[0027] Figure 10 Another one disclosed in the embodiments of the present application Figure 2 Cross-sectional view at the position of the median tangent B-B’;

[0028] Figure 11 Schematic diagram of a display device disclosed in the embodiments of the present application.

[0029] Explanation of reference numerals:

[0030] A1 - Display area; A2 - Non-display area; A3 - Signal line; A4 - Connection line, A5 - Connection line; A6 - Substrate; A7 - Insulating layer;

[0031] B1 - Display area; B2 - Non-display area, B201 - First non-display area, B202 - Second non-display area; B3 - Signal line, B301 - First signal line, B302 - Second signal line; B4 - First connection line; B5 - Second connection line, B501 - First sub-connection line, B502 - Second sub-connection line; B6 - Third connection line; B7 - Pad; B8 - Substrate; B9 - Insulating layer; B10 - Raised portion; B11 - Spaced portion; B12 - Light-shielding layer; B13 - Driving structure; B14 - First conductive layer; B15 - Second conductive layer;

[0032] Tm - Driving transistor; T1 - Gate reset transistor; T2 - Anode reset transistor; T3 - Data writing transistor; T4 - Threshold compensation transistor; T5 - First light-emitting control transistor; T6 - Second light-emitting control transistor; Cst - Storage capacitor; P - Light-emitting device; N1 - First node; N2 - Second node; N3 - Third node; N4 - Fourth node; Ref - Reset signal line; 10 - Data line; Pvdd - First power signal line; Pvee - Second power signal line Pvee; E - Light-emitting control line;

[0033] 100 - Array substrate, 200 - Housing. Detailed implementation

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0035] Multiple connection lines are provided in the non - display area of a conventional array substrate. The multiple connection lines need to occupy a relatively large space, resulting in a relatively large space in the lower border. To reduce the space of the lower border, in the prior art, some connection lines are arranged in the display area. Figure 1 It is a schematic structural diagram of an array substrate disclosed in the prior art. As Figure 1 shown, the connection line A4 is entirely located in the non - display area A2, and the connection line A5 is partially located in the display area A1 and partially located in the non - display area A2. The connection line A5 located in the display area A1 is connected to the signal line A3 located in the display area A1 by means of winding. In this way, the length of the connection line A4 is significantly shorter than the length of the connection line A5, resulting in an obvious length difference between the connection lines. The obvious length difference between the connection lines will lead to an obvious resistance value difference between the connection lines, thereby causing different degrees of signal attenuation of the driving signal voltage output from the driving chip, and it is easy to have the problem of uneven display of the display panel screen.

[0036] To this end, embodiments of the present application disclose an array substrate and a display device. The array substrate includes a display area, at least a part of a non-display area surrounding the display area, a substrate, signal lines, a first connection line, a second connection line, a third connection line, and a pad. The non-display area includes a first non-display area; the signal lines are located on one side of the substrate and in the display area, and the signal lines include a first signal line and a second signal line; the first connection line is located on one side of the substrate and in the display area; the second connection line, the third connection line, and the pad are located on one side of the substrate and in the first non-display area; the first signal line is electrically connected to the pad through the first connection line and the third connection line; the second signal line is electrically connected to the pad through the second connection line; the second connection line includes a first sub-connection line, and the extending direction of the first sub-connection line intersects with the plane where the substrate is located. It can be seen that in the embodiments of the present application, by providing the first sub-connection line whose extending direction intersects with the substrate, compared with the connection lines substantially parallel to the substrate in the prior art, the length of the first sub-connection line is increased in the second connection line of the embodiments of the present application, so that the length of the second connection line is increased. As a result, the difference between the length of the second connection line and the sum of the lengths of the first connection line and the third connection line is reduced, thereby reducing the length difference between the connection lines, and further reducing the resistance difference between the connection lines, and avoiding the problem of uneven display of the picture on the display panel.

[0037] See Figure 2 , a schematic structural diagram of an array substrate disclosed in an embodiment of the present application, and see Figure 3 , an embodiment of the present application discloses a Figure 2 The cross-sectional view at the position of the tangent line B-B' in

[0038] The array substrate disclosed in the embodiment of the present application includes a display area B1 and at least a part of a non-display area B2 surrounding the display area B1, and the non-display area B2 includes a first non-display area B201;

[0039] A substrate B8;

[0040] Signal lines B3, located on one side of the substrate B8 and in the display area B1, and the signal lines B3 include a first signal line B301 and a second signal line B302;

[0041] A first connection line B4, located on one side of the substrate B8 and in the display area B1;

[0042] A second connection line B5, a third connection line B6, and a pad B7, located on one side of the substrate B8 and in the first non-display area B201;

[0043] The first signal line B301 is electrically connected to the pad B7 through the first connection line B4 and the third connection line B6;

[0044] The second signal line B302 is electrically connected to the pad B7 through the second connection line B5;

[0045] Wherein, the second connection line B5 includes a first sub-connection line B501, and the extending direction of the first sub-connection line B501 intersects the plane where the substrate B8 is located.

[0046] It should be noted that the first connection line B4, the second connection line B5, and the third connection line B6 are used to transmit the driving signal sent by the driving structure B13 to the signal line B3 in the display area B1. The pad B7 is used for binding connection with the driving structure B13, wherein the driving structure B13 can be a driving chip or a flexible circuit board fixed with a driving chip.

[0047] It should be noted that the non-display area B2 in the embodiment of the present application further includes a second non-display area B202. Optionally, the first non-display area B201 refers to the lower border area of the screen, and the second non-display area B202 generally refers to the upper border area of the screen, and / or the left border area of the screen, and / or the right border area of the screen. In other embodiments, the first non-display area B201 and the second non-display area B202 can also be other border areas, and the present application does not limit this.

[0048] Optionally, the extending direction of the third connection line B6 in the embodiment of the present application is substantially parallel to the plane where the substrate B8 is located.

[0049] It should be noted that in the embodiment of the present application, in the direction perpendicular to the plane where the substrate B8 is located, the two sides of the second connection line B5 can be the insulating layer B9, and there can be other film layers between the second connection line B5 and the substrate B8, and the present application does not limit this.

[0050] See Figure 4 which is a cross-sectional view at the position of the tangent line A-A' disclosed in the prior art. In the prior art, the connection line A4 is located on one side of the substrate A6, and in the direction perpendicular to the plane where the substrate A6 is located, both sides of the connection line A4 are the insulating layer A7. By comparing Figure 1 with Figure 3 and Figure 4 it can be known that compared with the prior art, the first sub-connection line B501 is added in the embodiment of the present application. Thus, the length of the second connection line B5 in the embodiment of the present application is increased by the length of the first sub-connection line B501 compared with the length of the connection line A4 in the prior art.

[0051] It can be seen that in the embodiment of the present application, by arranging the first connection line in the display area, the space occupied by the connection line in the non-display area is reduced, thereby reducing the space of the border. Moreover, by arranging the second signal line to be directly electrically connected to the pad through the second connection line, the number of connection lines arranged in the display area can be reduced, and the wiring method in the display area can be simplified. More importantly, by arranging the first sub-connection line with an extending direction intersecting the substrate in the non-display area, compared with the second connection line substantially parallel to the substrate in the prior art, the second connection line in the embodiment of the present application increases the length of the first sub-connection line, so that the length of the second connection line is increased, and the difference between the length of the second connection line and the sum of the lengths of the first connection line and the third connection line is reduced, thereby reducing the length difference between the connection lines, and further reducing the resistance difference between the connection lines, avoiding the problem of uneven display of the display panel screen.

[0052] See Figure 2 and Figure 3 , in a possible implementation manner, the array substrate disclosed in the embodiment of the present application further includes:

[0053] The protruding portion B10 is located between the substrate B8 and the second connection line B5;

[0054] The spacing portion B11 is located between the substrate B8 and the second connection line B5 and between two protruding portions B10;

[0055] The protruding portion B10 and the spacing portion B11 are arranged along the extending direction of the second connection line B5.

[0056] It should be noted that by arranging the protruding portion B10 and the spacing portion B11 between the substrate B8 and the second connection line B5, the surface of the film layer including the protruding portion B10 and the spacing portion B11 is uneven. Therefore, the second connection line B5 is also uneven, thereby including the first sub-connection line B501. It can be understood that the more the protruding portion B10 and the spacing portion B11 are arranged, the more line segments of the second connection line B5 will be sunken downward, and correspondingly, the more line segments of the second connection line B5 will be protruded upward. Thus, the second connection line B5 will increase more length.

[0057] In the embodiment of the present application, a certain film layer between the second connection line B5 and the substrate B8 can be patterned to form the protruding portion B10 and the spacing portion B11. Specifically, the conductive layer can be patterned, and of course, other film layers can also be patterned. The present application does not limit this.

[0058] In the embodiment of the present application, three methods for patterning the film layer to form the protruding portion B10 and the spacing portion B11 are provided. The first method, see Figure 3, in the embodiment of the present application, the hollowing can be directly performed at the position of the spacer B11. In this way, a step difference will be formed in the film layer, thereby forming the convex portion B10 and the spacer B11. For the second method, refer to Figure 5 , in the embodiment of the present application, the position of the spacer B11 may not be hollowed out, and a step difference will still be formed in the film layer, thereby forming the convex portion B10 and the spacer B11. It should be noted that in the first method, the step difference is larger and the length of the first sub-connection line B501 is longer. In the second method, the step difference is relatively small, which can avoid the problem of broken lines caused by too large a step difference. For the third method, refer to Figure 6 , in the embodiment of the present application, some positions of the spacer B11 can be hollowed out, and some positions of the spacer B11 can be not hollowed out. In this way, a step difference will be formed in the film layer, thereby forming the convex portion B10 and the spacer B11. It should be noted that in the embodiment of the present application, the step difference can be adjusted according to actual needs, so as to adjust the length of the second connection line, and the appropriate setting method can be selected according to the specific situation of the product.

[0059] It can be seen that in the embodiment of the present application, by setting the convex portion and the spacer, a first sub-connection line whose extending direction intersects the plane where the substrate is located is formed. Compared with the connection line that is substantially parallel to the substrate in the prior art, the length of the second connection line is increased. As a result, the difference between the length of the second connection line and the sum of the lengths of the first connection line and the third connection line is reduced, thereby reducing the length difference between the connection lines, further reducing the resistance difference between the connection lines, and avoiding the problem of uneven display of the display panel screen.

[0060] In a possible implementation manner, the convex portion B10 in the array substrate disclosed in the embodiment of the present application is made of a conductive material.

[0061] It should be noted that the conductive material can be metal, etc., and there is no specific limitation, and it can be selected according to actual needs.

[0062] It can be seen that in the embodiment of the present application, by setting the convex portion as a conductive material, the capacitance of the second connection line can be increased through the overlap of the second connection line and the conductive material, thereby reducing the difference between the capacitance of the second connection line and the capacitance of the connection line composed of the first connection line and the third connection line, and further avoiding the problem of uneven display of the display panel screen. Moreover, since the convex portion is made of a conductive material, free electrons can be attracted, avoiding the problem of electrostatic injury caused by the accumulation of electrons in the relatively long second connection line.

[0063] In a possible implementation manner, the convex portion B10 in the array substrate disclosed in the embodiment of the present application is connected to a fixed potential.

[0064] It can be seen that in the embodiment of the present application, by connecting the convex portion to a fixed potential, the convex portion can be connected to a fixed voltage value, preventing the convex portion from being in a floating state without being connected to a potential, which easily attracts free electrons and causes damage to the second connection line, and avoiding the influence on the performance of the second connection line.

[0065] In a possible implementation manner, the fixed potential in the array substrate disclosed in the embodiment of the present application includes at least one of the following: a first power supply voltage fixed potential, a second power supply voltage fixed potential, and a reference voltage fixed potential.

[0066] It should be noted that the first power supply voltage fixed potential in the embodiment of the present application can be a PVDD fixed potential, and the second power supply voltage fixed potential can be a PVEE fixed potential. Among them, PVDD refers to Pixel VDD, and PVEE refers to Pixel VEE. Pixel represents a pixel, VDD represents a positive voltage, and VEE represents a negative voltage. Therefore, PVDD represents providing a positive voltage to the pixel, and PVEE represents providing a negative voltage to the pixel. The reference voltage (Voltage Reference, Vref) in the embodiment of the present application refers to a voltage in the circuit that is independent of the load, power supply, temperature drift, time, etc. and can remain constant all the time; when measuring the voltage value, it is the voltage value used as a reference point.

[0067] See Figure 7, which is a pixel circuit diagram in the array substrate disclosed in the embodiments of the present application. The pixel circuit includes a driving transistor Tm, a gate reset transistor T1, an anode reset transistor T2, a data writing transistor T3, a threshold compensation transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a storage capacitor Cst. Among them, the gate reset transistor T1 is used to reset the gate of the driving transistor Tm, and the anode reset transistor T2 is used to reset the light-emitting device P. The first pole of the gate reset transistor T1 is coupled to the reset signal line Ref, and the reset line Ref is used to provide a reset signal. The second pole of the gate reset transistor T1 is coupled to the first node N1, the gate of the driving transistor Tm is coupled to the first node N1, the first pole of the driving transistor Tm is coupled to the second node N2, and the second pole of the driving transistor Tm is coupled to the third node N3. The driving transistor Tm is connected in series between the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The first pole of the data writing transistor T3 is coupled to the data line 10, the second pole of the data writing transistor T3 is coupled to the second node N2, and the threshold compensation transistor T4 is connected in series between the first node N1 and the third node N3. The first electrode plate of the storage capacitor Cst and one pole of the first light-emitting control transistor T5 are both coupled to the first power supply signal line Pvdd. The first pole of the anode reset transistor T2 is coupled to the reset signal line Ref, and the second pole of the anode reset transistor T2 and the first electrode of the light-emitting device P are coupled to the fourth node N4. The second electrode of the light-emitting device P is coupled to the second power supply signal line Pvee. Among them, the first power supply signal line Pvdd is a positive power supply line, and the second power supply signal line Pvee is a negative power supply line. The gates of the data writing transistor T3 and the threshold compensation transistor T4 are coupled to the first scan line Sc1, the gates of the gate reset transistor T1 and the anode reset transistor T2 are coupled to the second scan line Sc2, and the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are coupled to the light-emitting control line E. It should be noted that Figure 7 only the pixel circuit with 7 transistors and 1 capacitor is schematically shown, which is not a limitation to the present application.

[0068] It should be noted that the first power supply signal line Pvdd is connected to the fixed potential of PVDD, the second power supply signal line Pvee is connected to the fixed potential of PVEE, and the reset line Ref is connected to the fixed potential of Vref.

[0069] In a possible implementation manner, the signal line in the embodiments of the present application is a data line. That is, corresponding to Figure 7 the data line 10 in

[0070] In a possible implementation, the fixed potential is the PVDD fixed potential, and all the protruding portions are connected to the PVDD fixed potential. In this way, all the protruding portions are connected to the same PVDD fixed potential, which can fully ensure the consistency of the capacitance change of the connection line to PVDD, reduce the capacitance difference between adjacent connection lines, and further avoid affecting the performance of the second connection line.

[0071] In a possible implementation, the fixed potential is the PVEE fixed potential, and all the protruding portions are connected to the PVEE fixed potential. In this way, all the protruding portions are connected to the same PVEE fixed potential, which can fully ensure the consistency of the capacitance change of the connection line to PVEE, reduce the capacitance difference between adjacent connection lines, and further avoid affecting the performance of the second connection line.

[0072] In a possible implementation, the fixed potential is the Vref fixed potential, and all the protruding portions are connected to the Vref fixed potential. In this way, all the protruding portions are connected to the same Vref fixed potential, which can fully ensure the consistency of the capacitance change of the connection line to Vref, reduce the capacitance difference between adjacent connection lines, and further avoid affecting the performance of the second connection line.

[0073] The inventor considered that in the embodiments of the present application, some of the second connection lines are connected to the PVDD fixed potential, and some of the second connection lines are connected to the PVEE fixed potential. Therefore, in a possible implementation, the fixed potential includes the PVDD fixed potential and the PVEE fixed potential, some of the protruding portions are connected to the PVDD fixed potential, and some of the protruding portions are connected to the PVEE fixed potential. Specifically: the protruding portions where the second connection lines connected to the PVDD fixed potential overlap are connected to the PVDD fixed potential, and the protruding portions where the second connection lines connected to the PVEE fixed potential overlap are connected to the PVEE fixed potential. In this way, the protruding portions where the second connection lines connected to the PVDD fixed potential overlap are uniformly at the PVDD fixed potential, and the protruding portions where the second connection lines connected to the PVEE fixed potential overlap are uniformly at the PVEE fixed potential, which can reduce the voltage difference between the upper and lower parts of the connection line, prevent the problem of electrochemical corrosion of the connection line during the reliability test, and achieve the protection of the connection line.

[0074] It can be seen that in the embodiments of the present application, by reusing the original fixed potential in the display panel, additional signals are avoided.

[0075] See Figure 8 , which is a cross-sectional view at the position of the tangent line B - B' in another Figure 2 disclosed in the embodiments of the present application. In a possible implementation, the array substrate disclosed in the embodiments of the present application further includes:

[0076] A light-shielding layer B12, which is on the same layer as the protruding portion B10 and the spacer portion B11.

[0077] It should be noted that the light-shielding layer is located between the thin-film transistor and the substrate. The light-shielding layer has a thin thickness, generally about 100 nm. The light-shielding layer can be used to shield the active layer from light, preventing the light from affecting the stability of the active layer; it can also prevent the ions in the bottom layer from entering the thin-film transistor, avoiding affecting the performance of the thin-film transistor; it can also prevent the aggregation of free electrons, avoiding the aggregated electrons from breaking down the thin-film transistor and protecting the thin-film transistor.

[0078] It can be seen that in the embodiment of the present application, the protrusion and the spacer are arranged on the same layer as the light-shielding layer, and a mask can be shared, reducing costs. Moreover, since the light-shielding layer has a thin thickness, arranging the protrusion and the spacer on the same layer as the light-shielding layer has little influence on the morphology of the second connection line and will not cause the second connection line to break.

[0079] In an alternative embodiment, in the direction from the middle of the first non-display area pointing to the edge and perpendicular to the extension direction of the signal line, the length of the second connection line gradually increases, and the middle second connection line needs to increase a longer length.

[0080] See Figure 9 , which is a schematic diagram of the positions of the protrusion and the spacer disclosed in the embodiment of the present application, and continue to refer to Figure 2 . In a possible implementation manner, in the array substrate disclosed in the embodiment of the present application, in the direction from the middle of the first non-display area B201 pointing to the edge and perpendicular to the extension direction of the signal line B3, the number of the spacers B10 overlapping with one of the second connection lines B5 gradually decreases, and / or the number of the protrusions B11 overlapping with one of the second connection lines B5 gradually decreases.

[0081] It can be seen that in the embodiment of the present application, by setting the number of the spacers overlapping with one second connection line to gradually decrease, and / or setting the number of the protrusions overlapping with one second connection line to gradually decrease, in the direction from the middle of the first non-display area pointing to the edge and perpendicular to the extension direction of the signal line, the length of the middle second connection line will increase more, so that the length difference between the connection lines will be reduced.

[0082] See Figure 10 , which is another Figure 2 cross-sectional view at the position of the middle tangent B-B'. In a possible implementation manner, the array substrate disclosed in the embodiment of the present application further includes an insulating layer B9, a first conductive layer B14, and a second conductive layer B15. The insulating layer B9 is located between the first conductive layer B14 and the second conductive layer B15;

[0083] At least a part of the second connection line B5 is located in the first conductive layer B14; and / or,

[0084] The second connection line B5 is at least partially located in the second conductive layer B15.

[0085] It should be noted that, referring to Figure 7 , the first conductive layer is generally used as the gate of the thin film transistor and the connection line, and the second conductive layer is generally used as one of the electrodes of the capacitor and the connection line.

[0086] It can be seen that in the embodiments of the present application, the cushion layer can be selected to be disposed under which conductive layer according to the actual situation, which increases the feasibility of the solution.

[0087] Referring to Figure 3 , in a possible implementation manner, the second connection line B5 in the embodiments of the present application further includes a second sub-connection line B502 electrically connected to the first sub-connection line B501, and the extending direction of the second sub-connection line B502 intersects with the extending direction of the first sub-connection line B501. Among them, the extending direction of the second sub-connection line B502 is also substantially parallel to the plane where the substrate B8 is located.

[0088] Referring to Figure 11 , which is a schematic diagram of a display device disclosed in the embodiments of the present application. The embodiments of the present application also provide a display device, including the array substrate 100 as described in any one of the above.

[0089] It should be noted that the display device in the embodiments of the present application may further include a housing 200. Figure 11 Taking the display device as a mobile phone as an example, the display device may also be a computer, a tablet, etc., and the present application does not limit this.

[0090] It should be noted that for the specific working principles of the components in the device embodiments, please refer to the corresponding parts of the array substrate embodiments, which will not be elaborated here.

[0091] Finally, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0092] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0093] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An array substrate, characterized in that, Comprising: A display area and at least a partially non-display area surrounding the display area, the non-display area including a first non-display area; A substrate; Signal lines, located on one side of the substrate and within the display area, the signal lines including a first signal line and a second signal line; A first connection line, located on one side of the substrate and within the display area; A second connection line, a third connection line, and a pad, located on one side of the substrate and within the first non-display area; The first signal line is electrically connected to the pad through the first connection line and the third connection line; The second signal line is electrically connected to the pad through the second connection line; Wherein, the second connection line includes a first sub-connection line, and the extending direction of the first sub-connection line intersects with the plane where the substrate is located; The array substrate further comprises: A raised portion, located between the substrate and the second connection line; A spaced portion, located between the substrate and the second connection line and between two of the raised portions; The raised portion and the spaced portion are arranged along the extending direction of the second connection line; In the direction pointing from the middle of the first non-display area to the edge and perpendicular to the extending direction of the signal line, the number of the spaced portions overlapping with one of the second connection lines gradually decreases, and / or the number of the raised portions overlapping with one of the second connection lines gradually decreases.

2. The array substrate according to claim 1, wherein The raised portion is made of a conductive material.

3. The array substrate according to claim 2, wherein The raised portion is connected to a fixed potential.

4. The array substrate according to claim 3, wherein, The fixed potential includes at least one of the following: a first power supply voltage fixed potential, a second power supply voltage fixed potential, a reference voltage fixed potential.

5. The array substrate according to claim 1, wherein Further comprising: A light-shielding layer, on the same layer as the raised portion and the spaced portion.

6. The array substrate according to claim 1, wherein Further comprising an insulating layer, a first conductive layer, and a second conductive layer, the insulating layer being located between the first conductive layer and the second conductive layer; At least a part of the second connection line is located in the first conductive layer; and / or, At least a part of the second connection line is located in the second conductive layer.

7. The array substrate according to claim 1, characterized in that The signal line is a data line.

8. The array substrate according to claim 1, wherein The second connection line further includes a second sub-connection line electrically connected to the first sub-connection line, and the extending direction of the second sub-connection line intersects with the extending direction of the first sub-connection line.

9. A display device, characterized in that, Comprising the array substrate according to any one of claims 1-8.

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