A pixel unit and a forming method

Abstract

This invention discloses a pixel unit and its formation method. The pixel unit includes a photosensitive portion of a second conductivity type disposed in a substrate of a first conductivity type; isolation portions of the first conductivity type disposed in substrates on both sides of the photosensitive portion; a first region of the second conductivity type disposed in a substrate on the front side of the photosensitive portion; a second region of the first conductivity type disposed in a substrate on the front side of the photosensitive portion and the isolation portion, and the second region surrounds the side surface of the first region; a contact portion disposed on the front side of the first region; and a gate surrounding the side surface of the contact portion and disposed on the front surface of the substrate, wherein the inner and outer sides of the gate partially overlap with the first region and the second region in a vertical position. This invention allows for adjustment of the device's response speed and saturation detection current by applying different bias voltages to the gate, achieving imaging and detection functions that can accommodate both high speed and large electron flow, thus expanding its application range.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a pixel unit and a method for forming it. Background Technology

[0002] Silicon-based photodiodes can be used for the detection and imaging of low-energy secondary electron flows, such as 1keV to 10keV, enabling their application in fields such as scanning electron microscopy.

[0003] Currently, existing pixel units based on silicon-based partially pinned photodiodes have advantages such as low cost and easy integration, but in actual device design, there is a trade-off between response speed and the maximum electron flow intensity detected, which limits the application range of the devices. Summary of the Invention

[0004] The purpose of this invention is to overcome the above-mentioned defects in the prior art and to provide a pixel unit and a method for forming it.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] This invention provides a pixel unit, comprising:

[0007] Substrate of the first conductivity type;

[0008] A photosensitive portion of a second conductivity type is disposed in the substrate;

[0009] An isolation portion of a first conductivity type is provided in the substrate on both sides of the photosensitive portion;

[0010] A first region of a second conductivity type is provided in the substrate on the front side of the photosensitive part;

[0011] A second region of a first conductivity type is disposed in the substrate on the front side of the photosensitive part and the insulating part, and the second region surrounds the side exterior of the first region;

[0012] A contact portion is provided on the front side of the first area;

[0013] A gate is disposed on the front surface of the substrate surrounding the side of the contact portion, with its inner and outer sides partially overlapping the first and second regions in vertical position.

[0014] Furthermore, a partially pinned photodiode is formed between the second region, the photosensitive portion, and the first region on the front surface of the substrate.

[0015] Furthermore, the gate is used to control the potential distribution of the pixel unit on the front surface of the substrate.

[0016] Furthermore, the first region includes a third region and a fourth region. The contact portion is disposed on the front side of the third region, and the fourth region surrounds the side and bottom surfaces of the third region. The inner side of the gate and the fourth region partially overlap vertically. The conductivity of the third region, the fourth region, and the photosensitive portion decreases sequentially. The conductivity of the second region is higher than that of the isolation portion and the photosensitive portion.

[0017] Furthermore, it also includes: a dielectric layer disposed on the front surface of the substrate and filling the space between the contact portion and the gate; and / or a passivation layer disposed on the back surface of the substrate and located on the back surface of the photosensitive portion and the isolation portion.

[0018] The present invention also provides a method for forming a pixel unit, comprising:

[0019] Provide a substrate of the first conductivity type;

[0020] A photosensitive portion of a second conductivity type is formed in the substrate;

[0021] An isolation portion of a first conductivity type is formed in the substrate on both sides of the photosensitive portion;

[0022] A second region of a first conductivity type is formed below the front surface of the substrate, such that the second region is located on the front surface of the photosensitive part and the isolation part, and the second region forms a window on the front surface of the photosensitive part.

[0023] An annular gate is formed on the front surface of the substrate above the window, and the outer annular portion of the gate overlaps with the second region in a vertical position.

[0024] A first region of a second conductivity type is formed below the front surface of the substrate on the inner side of the gate ring, such that the first region is located on the front surface of the photosensitive part, so as to form a partially pinned photodiode between the second region, the photosensitive part and the first region, and to form a partial vertical overlap between the first region and the inner side of the gate ring.

[0025] A contact portion is formed on the front side of the first region, located within the annulus of the gate.

[0026] Furthermore, it also includes:

[0027] Before forming the second region, a fourth region of the second conductivity type is first formed below the front surface of the substrate, such that the fourth region is located on the front surface of the photosensitive part. Then, the second region is formed around the outside of the side of the fourth region, so that the second region has the window around the outside of the side of the fourth region.

[0028] When forming the gate, the inner side of the gate and the fourth region are partially overlapped in vertical position. After forming the gate, a third region of the second conductivity type is formed on the front surface of the fourth region, located within the ring of the gate, thereby forming the first region composed of the third region and the fourth region, and the contact portion is formed on the front surface of the third region.

[0029] Furthermore, by ion implantation, the first conductivity type and the second conductivity type are formed, and the conductivity of the formed third region, the fourth region and the photosensitive portion decreases sequentially, and the conductivity of the second region is higher than that of the isolation portion and the photosensitive portion.

[0030] Furthermore, forming a contact portion on the front side of the first region within the annular region of the gate specifically includes:

[0031] A dielectric layer is formed on the front surface of the substrate to cover the gate and is planarized;

[0032] A through-hole is formed on the front surface of the dielectric layer within the annulus of the gate, with its bottom connected to the front surface of the first region;

[0033] The contact portion is formed by filling the through hole with conductive material.

[0034] Furthermore, it also includes:

[0035] The back side of the substrate is thinned to expose the back surface of the photosensitive part and the insulating part;

[0036] A passivation layer is formed on the back surface of the photosensitive part and the isolation part on the thinned back surface of the substrate.

[0037] As can be seen from the above technical solution, the present invention forms a partially pinned photodiode on the substrate and sets a ring gate structure above the partially pinned photodiode to control the potential distribution on the surface of the pixel unit device. Thus, by applying different bias voltages to the gate, the response speed and saturation detection current of the pixel unit device can be adjusted, thereby achieving imaging and detection functions that can take into account both high speed and large electron flow, and expanding the application range. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a pixel unit according to a preferred embodiment of the present invention;

[0039] Figure 2 This is a flowchart of a pixel unit formation method according to a preferred embodiment of the present invention;

[0040] Figure 3This is a schematic diagram of device parameters obtained through simulation according to a preferred embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0042] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0043] Please see Figure 1 , Figure 1 This is a schematic diagram of a pixel unit according to a preferred embodiment of the present invention. Figure 1 As shown, a pixel unit of the present invention is built on a substrate 10 and includes the following main structural components: a photosensitive part 108, an isolation part 106, a first region 112, a second region 105, a contact part 104, and a gate 103.

[0044] The substrate 10 can be a semiconductor substrate. For example, the substrate 10 can be a bulk semiconductor substrate, a semiconductor-on-insulator (SIA) substrate, etc. The substrate 10 can be a wafer, such as a silicon wafer. Typically, a SIA substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide layer, a silicon oxide layer, etc. Other substrates can also be used.

[0045] In some embodiments, the semiconductor material of the substrate 10 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0046] The substrate 10 has a first conductivity type. The first conductivity type can be either P-type or N-type. Correspondingly, the second conductivity type can be either N-type or P-type. Furthermore, the first conductivity type can be formed using, for example, ion implantation with P-type or N-type dopant. Similarly, the second conductivity type can be formed using, for example, ion implantation with N-type or P-type dopant. The following explanation uses an example where the first conductivity type is P-type and formed using ion implantation with P-type dopant, and the second conductivity type is N-type and formed using ion implantation with N-type dopant.

[0047] In some embodiments, the substrate 10 may be a single-crystal silicon substrate 10 with p-type doping.

[0048] The photosensitive portion 108 is disposed in the substrate 10 and has an N-type conductivity type. For example, the photosensitive portion 108 may be formed in a P-type doped single-crystal silicon substrate 10 using N-type doping.

[0049] In some embodiments, the photosensitive portion 108 may form a photodiode, which can be used to separate electron-hole pairs generated when low-energy electrons are injected into the silicon substrate 10.

[0050] An isolation portion 106 is disposed in the substrate 10 and located on both sides of the photosensitive portion 108, and can be used as an isolation between pixels. The isolation portion 106 has a P-type conductivity type. For example, the isolation portion 106 can be formed in a P-type doped single-crystal silicon substrate 10 using P-type doping and located on both sides of the N-type doped photosensitive portion 108.

[0051] The first region 112 is disposed below the front surface of the substrate 10 and is located on the front surface of the photosensitive portion 108. The first region 112 has an N-type conductivity type. For example, the first region 112 may be formed in a P-type doped single-crystal silicon substrate 10 using N(N+) type doping and located on the front surface of the N-type doped photosensitive portion 108.

[0052] The second region 105 is disposed below the front surface of the substrate 10 and is located on the front surface of the photosensitive portion 108 and the isolation portion 106; and the second region 105 surrounds the outside of the side surface of the first region 112. The second region 105 has a P-type conductivity type. For example, the second region 105 may be formed in a P-type doped single crystal silicon substrate 10 using P+ type doping, and is located on the front surface of the N-type doped photosensitive portion 108 and the P-type doped isolation portion 106, while also surrounding the outside of the side surface of the N(N+) type doped first region 112, forming a P+ type pinned implantation region.

[0053] The contact portion 104 is disposed on the front surface of the substrate 10, that is, on the front surface of the first region 112, and forms an ohmic contact with the front surface of the first region 112 to draw out photoelectrons.

[0054] A gate 103 is disposed on the front surface of the substrate 10 and surrounds the outside of the side of the contact portion 104 to form a ring-shaped gate 103. Furthermore, the inner side of the ring gate 103 partially overlaps with the first region 112 in terms of vertical position, and the outer side of the ring gate 103 also partially overlaps with the second region 105 in terms of vertical position.

[0055] In some embodiments, the gate 103 may be a polysilicon gate 103 or the like.

[0056] In some embodiments, the operating voltage of the gate 103 can be between 1.2V and 5V.

[0057] The gate 103 and the substrate 10 can be isolated by the gate dielectric layer 109. In some embodiments, the gate dielectric layer 109 may be made of materials such as silicon oxide, silicon nitride, or hafnium oxide.

[0058] Sidewalls 102 may also be provided on both sides of the gate 103. The sidewall 102 may be made of silicon oxide, silicon nitride, silicon carbonitride, etc.

[0059] In some embodiments, the contact portion 104 may be a metal electrode. The electrode metal may be, for example, copper, aluminum, tungsten, or a metal alloy.

[0060] Please see Figure 1 In some embodiments, the second region 105 and the first region 112 are laterally isolated by the photosensitive portion 108, such that a partially pinned photodiode is formed between the second region 105, the photosensitive portion 108, and the first region 112 on the front surface of the substrate 10.

[0061] Gate 103 can be used to control the potential distribution of pixel unit devices on the front surface of substrate 10. By applying different bias voltages to polysilicon gate 103, the response speed and saturation probe current of pixel unit devices can be adjusted, thereby achieving both high-speed imaging and detection with large electron flow.

[0062] Please see Figure 1 In some embodiments, the first region 112 may include a third region 110 and a fourth region 111 connected together. The third region 110 may be formed using N+ type doping; the contact portion 104 may be disposed on the front side of the N+ type doped third region 110. The fourth region 111 may surround the side and bottom surfaces of the third region 110, and the fourth region 111 may be formed using N-type doping. The inner side of the gate 103 and the fourth region 111 partially overlap vertically.

[0063] In some embodiments, the conductivity of the third region 110, the fourth region 111, and the photosensitive portion 108 decreases sequentially, that is, the N-type doping concentration of the third region 110, the fourth region 111, and the photosensitive portion 108 decreases sequentially.

[0064] In some embodiments, the conductivity of the second region 105 can be adjusted to be higher than that of the isolation portion 106 and the photosensitive portion 108.

[0065] Please see Figure 1 In some embodiments, a dielectric layer 101 may also be provided on the front surface of the substrate 10. The dielectric layer 101 may fill between the contact portion 104 and the gate 103 to maintain isolation between the contact portion 104 and the gate 103. Furthermore, the dielectric layer 101 may extend to completely cover the front surface of the substrate 10.

[0066] In some embodiments, a passivation layer 107 may also be provided on the back side of the substrate 10. Furthermore, the passivation layer 107 may be located on the back surface of the photosensitive portion 108 and the isolation portion 106.

[0067] In some embodiments, the passivation layer 107 material may be hafnium dioxide, silicon oxide, silicon nitride, phosphosilicate glass, etc.

[0068] The following detailed description of a pixel unit formation method of the present invention, with reference to specific embodiments and accompanying drawings, provides a detailed explanation.

[0069] Please see Figure 2 The present invention provides a pixel unit forming method, which can be used to form, for example, the pixel unit formed described above. Figure 1 A pixel unit in [the context of a pixel unit], and may include the following steps:

[0070] Step S1: Provide a substrate 10 of a first conductivity type.

[0071] In some embodiments, the substrate 10 may be a single-crystal silicon substrate 10 with P-doping.

[0072] Step S2: Form a photosensitive part 108 of a second conductivity type in the substrate 10.

[0073] First, an N-doped region with a suitable junction depth can be formed in the silicon substrate 10 by ion implantation and thermal diffusion, thereby forming the photosensitive part 108.

[0074] In some embodiments, the impurity ions used in the doping process may include, but are not limited to, phosphorus and arsenic.

[0075] In some embodiments, the implantation concentration during doping can be from 1e11cm^-2 to 1e12cm^-2.

[0076] In some embodiments, the implantation energy during doping can be from 20 keV to 1300 keV.

[0077] Step S3: An isolation portion 106 of a first conductivity type is formed in the substrate 10 on both sides of the photosensitive portion 108.

[0078] An isolation region can be defined on the surface of the silicon substrate 10, and photoresist can be applied to the surface of the silicon substrate 10 outside the isolation region. Then, by ion implantation, an isolation region 106 with appropriate junction depth and P-type doping is formed in the silicon substrate 10 on both sides of the photosensitive part 108 to serve as an isolation structure between pixels.

[0079] In some embodiments, the impurity ions used in the doping process may include, but are not limited to, boron and boron fluoride.

[0080] In some embodiments, the implantation concentration during doping can be from 1e12cm^-2 to 1e14cm^-2.

[0081] In some embodiments, the implantation energy during doping can be between 10 keV and 500 keV.

[0082] Step S4: A second region 105 of the first conductivity type is formed below the front surface of the substrate 10, such that the second region 105 is located on the front surface of the photosensitive part 108 and the isolation part 106, and a window 113 is formed on the front surface of the photosensitive part 108 by the second region 105.

[0083] A fourth region can be defined on the surface of the silicon substrate 10, and photoresist can be applied to the surface of the silicon substrate 10 outside the fourth region. Then, an N-type doped fourth region 111 can be formed below the front surface of the silicon substrate 10 and on the front surface of the photosensitive part 108 by ion implantation.

[0084] In some embodiments, the impurity ions used in the doping process may include, but are not limited to, phosphorus and arsenic.

[0085] In some embodiments, the implantation concentration during doping can be from 1e11cm^-2 to 1e13cm^-2.

[0086] In some embodiments, the implantation energy during doping can be from 10 keV to 200 keV.

[0087] Next, a second region can be defined on the surface of the silicon substrate 10 surrounding the fourth region 111, and photoresist can be applied to the surface of the silicon substrate 10 outside the second region. Then, a P+-doped second region 105 can be formed below the front surface of the silicon substrate 10 and on the front surface of the photosensitive portion 108 and the isolation portion 106 by ion implantation.

[0088] In some embodiments, the impurity ions used in the doping process may include, but are not limited to, boron and boron fluoride.

[0089] In some embodiments, the implantation concentration during doping can be from 1e13cm^-2 to 1e14cm^-2.

[0090] In some embodiments, the implantation energy during doping can be between 10 keV and 90 keV.

[0091] When performing ion implantation in the second region 105, the area around the fourth region 111 needs to be completely covered by photoresist to prevent the P+ doped second region 105 from contacting the already formed N-type doped fourth region 111. This allows the second region 105 to form a window 113 on the front surface of the photosensitive portion 108 around the fourth region 111, i.e., to form the second region 105 surrounding the outside of the side of the fourth region 111, so as to form a lateral pin diode structure on the surface of the silicon substrate 10.

[0092] In other embodiments, the step of forming the fourth region 111 may be omitted, and the second region 105 with the window 113 structure may be formed directly.

[0093] Then, the injection regions formed above can be activated by annealing.

[0094] In some embodiments, the annealing temperature can be between 800 and 1100 degrees Celsius.

[0095] In some embodiments, the annealing time can be from 10 seconds to 30 minutes.

[0096] Step S5: Form an annular gate 103 on the front surface of the substrate 10 above the window 113, and make the outer annular part of the gate 103 partially overlap with the second region 105 in terms of vertical position.

[0097] Next, a dielectric deposition process can be used to form, for example, a silicon oxide gate dielectric layer 109 on the front surface of the silicon substrate 10.

[0098] In some embodiments, the thickness of the gate dielectric layer 109 may be 2 nanometers to 8 nanometers.

[0099] Then, a gate forming process can be used to form, for example, a polysilicon ring gate 103 on the gate dielectric layer 109. When forming the gate 103, it is necessary to make the outer ring of the gate 103 partially overlap with the second region 105 in terms of vertical position, and at the same time, it is necessary to make the inner ring of the gate 103 partially overlap with the fourth region 111 in terms of vertical position.

[0100] Next, a sidewall forming process can be used to form, for example, silicon nitride sidewalls 102 on both sides of the gate 103.

[0101] When the step of forming the fourth region 111 is omitted, the aforementioned position of the inner annular side of the gate 103 on the silicon substrate 10 can remain unchanged.

[0102] Step S6: A first region 112 of the second conductivity type is formed below the front surface of the substrate 10 on the inner side of the gate 103, such that the first region 112 is located on the front surface of the photosensitive part 108, and the first region 112 and the inner side of the gate 103 partially overlap in vertical position.

[0103] Next, using the sidewalls 102 formed on both sides of the gate 103, and through ion implantation, an N+-doped third region 110 located within the ring of the gate 103 is formed on the front surface of the fourth region 111 within the front surface of the silicon substrate 10. Thus, a first region 112 composed of the third region 110 and the fourth region 111 is formed.

[0104] In this way, a partially pinned photodiode is formed between the second region 105, the photosensitive part 108, and the first region 112.

[0105] When the step of forming the fourth region 111 is omitted, the first region 112 can be formed by the third region 110. At this time, it is necessary to inject the third region 110 so that the side of the third region 110 extends to the lower inner side of the annular gate 103, so that the inner annular side of the gate 103 and the third region 110 partially overlap vertically.

[0106] Step S7: A contact portion 104 is formed on the front side of the first region 112, located within the annulus of the gate 103.

[0107] Next, a dielectric layer 101 can be formed on the front surface of the silicon substrate 10 using a dielectric deposition process, covering the gate 103. Then, the surface of the dielectric layer 101 can be planarized using, for example, a chemical mechanical polishing process, and can be stopped on the top surface of the gate 103.

[0108] Next, photolithography, etching and other processes can be used to form a through hole on the front surface of the dielectric layer 101 within the ring of the gate 103, with the bottom connected to the front surface of the third region 110 (first region 112).

[0109] Then, a metal filling process can be used to fill the through hole with a conductive material, such as copper, and excess copper outside the through hole can be removed by planarization to form the contact portion 104.

[0110] Next, a back-side process can be used to thin the back side of the silicon substrate 10 to the required thickness, for example, to expose the back surface of the photosensitive portion 108 and the isolation portion 106.

[0111] Finally, a passivation layer 107 can be formed on the back surface of the photosensitive part 108 and the isolation part 106 on the back side of the thinned substrate 10 to ensure that electrons can enter the photodiode region.

[0112] Ultimately formed as Figure 1 The pixel unit structure is shown. Parameters characterizing the performance of a pixel unit device may include pixel unit reset time and maximum voltage swing, etc.

[0113] Figure 3 The simulation results shown illustrate the relationship between readout speed and voltage swing under different gate voltages. The pixel unit structure of this invention allows for adjustment of the device readout speed and the amount of electron flow the device can withstand by changing the gate voltage; that is, changing the gate voltage can adjust the device performance. For example, when N-type doping is used in the first region 112, a negative bias can be applied to the ring gate 103 to increase the voltage swing. This helps to control the depletion region boundary as close as possible to the first region 112, achieving a larger output voltage linear region range and increasing the voltage swing. Conversely, when a positive bias is applied to the ring gate 103, although the voltage swing decreases, the device readout speed is increased. This enables high-speed imaging or high electron flow imaging.

[0114] In summary, this invention forms a partially pinned photodiode on the substrate 10 and sets a ring gate 103 structure above the partially pinned photodiode to control the potential distribution on the surface of the pixel unit device. Thus, by applying different bias voltages to the gate 103, the response speed and saturation detection current of the pixel unit device can be adjusted, achieving imaging and detection functions that can take into account both high speed and large electron flow, thereby expanding the application range.

[0115] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A pixel unit, characterized in that, include: Substrate of the first conductivity type; A photosensitive portion of a second conductivity type is disposed in the substrate; An isolation portion of a first conductivity type is provided in the substrate on both sides of the photosensitive portion; A first region of a second conductivity type is provided in the substrate on the front side of the photosensitive part; A second region of a first conductivity type is disposed in the substrate on the front side of the photosensitive part and the isolation part, and the second region surrounds the side exterior of the first region; a partially pinned photodiode is formed between the second region, the photosensitive part and the first region on the front surface of the substrate; A contact portion is provided on the front side of the first area; A gate is disposed on the front surface of the substrate surrounding the side of the contact portion, with its inner and outer sides partially overlapping the first and second regions in vertical position.

2. The pixel unit according to claim 1, characterized in that, The gate is used to control the potential distribution of the pixel unit on the front surface of the substrate.

3. The pixel unit according to claim 1, characterized in that, The first region includes a third region and a fourth region. The contact portion is disposed on the front side of the third region. The fourth region surrounds the side and bottom surfaces of the third region. The inner side of the gate and the fourth region partially overlap vertically. The conductivity of the third region, the fourth region and the photosensitive portion decreases sequentially. The conductivity of the second region is higher than that of the isolation portion and the photosensitive portion.

4. The pixel unit according to claim 1, characterized in that, Also includes: A dielectric layer is disposed on the front surface of the substrate and filled between the contact portion and the gate. And / or, a passivation layer disposed on the back side of the substrate and located on the back surface of the photosensitive part and the isolation part.

5. A method for forming a pixel unit, characterized in that, include: Provide a substrate of the first conductivity type; A photosensitive portion of a second conductivity type is formed in the substrate; An isolation portion of a first conductivity type is formed in the substrate on both sides of the photosensitive portion; A second region of a first conductivity type is formed below the front surface of the substrate, such that the second region is located on the front surface of the photosensitive part and the isolation part, and the second region forms a window on the front surface of the photosensitive part. An annular gate is formed on the front surface of the substrate above the window, and the outer annular part of the gate partially overlaps with the second region in a vertical position. A first region of a second conductivity type is formed below the front surface of the substrate on the inner side of the gate ring, such that the first region is located on the front surface of the photosensitive part, so as to form a partially pinned photodiode between the second region, the photosensitive part and the first region, and to form a partial vertical overlap between the first region and the inner side of the gate ring. A contact portion is formed on the front side of the first region, located within the annulus of the gate.

6. The pixel unit forming method according to claim 5, characterized in that, Also includes: Before forming the second region, a fourth region of the second conductivity type is first formed below the front surface of the substrate, such that the fourth region is located on the front surface of the photosensitive part. Then, the second region is formed around the outside of the side of the fourth region, so that the second region has the window around the outside of the side of the fourth region. When forming the gate, the inner side of the gate and the fourth region are partially overlapped in vertical position. After forming the gate, a third region of the second conductivity type is formed on the front surface of the fourth region, located within the ring of the gate, thereby forming the first region composed of the third region and the fourth region, and the contact portion is formed on the front surface of the third region.

7. The pixel unit forming method according to claim 6, characterized in that, By ion implantation, the first conductivity type and the second conductivity type are formed, and the conductivity of the formed third region, the fourth region and the photosensitive part decreases sequentially, and the conductivity of the second region is higher than that of the isolation part and the photosensitive part.

8. The pixel unit forming method according to claim 5, characterized in that, The formation of a contact portion within an annular shape of the gate on the front surface of the first region specifically includes: A dielectric layer is formed on the front surface of the substrate to cover the gate and is planarized; A through-hole is formed on the front surface of the dielectric layer within the annulus of the gate, with its bottom connected to the front surface of the first region; The contact portion is formed by filling the through hole with conductive material.

9. The pixel unit forming method according to claim 5, characterized in that, Also includes: The back side of the substrate is thinned to expose the back surface of the photosensitive part and the insulating part; A passivation layer is formed on the back surface of the photosensitive part and the isolation part on the thinned back surface of the substrate.

Images