A semiconductor structure and a method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a semiconductor substrate, the semiconductor substrate comprises a plurality of first regions and second regions which are alternately arranged, a surface of the semiconductor substrate comprises an epitaxial layer, and a surface of the epitaxial layer comprises a current dispersion layer; a first doped region is located in the current dispersion layer of the first region; a second doped region is located in the first doped region; a third doped region is located in the current dispersion layer and crosses the first region and an adjacent second region, one end of the third doped region is connected to the second doped region in the first region, and the other end of the third doped region extends into the second region; and an electric field buffer region is located in the current dispersion layer of the second region and between adjacent third doped regions. The technical scheme of the application can avoid the occurrence of secondary degradation in a power MOSFET device, and improve the performance and reliability of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] When traditional silicon carbide power MOSFETs are used independently as switches, the body diode built into the power MOSFET structure acts as a freewheeling diode to withstand the reverse surge voltage and surge current generated by inductive loads or parasitic inductance in the circuit. When the PN junction of the body diode is subjected to large current for a long time, the stacking defects in the silicon carbide crystal structure may expand and develop into diode degradation, resulting in a decrease in the conductivity of the device. This has long been a hidden danger to the reliability of silicon carbide power MOSFETs.

[0003] In silicon carbide power modules used for switching applications, a freewheeling diode is usually connected in parallel to improve its reverse current handling capability. However, this comes at the cost of slowing down the switching frequency and increasing switching losses due to the external device.

[0004] Therefore, it is necessary to provide more effective and reliable technical solutions to improve the current carrying capacity of the body diode without affecting the device performance and to avoid secondary degradation. Summary of the Invention

[0005] This application provides a semiconductor structure and a method for forming the same, which can avoid secondary degradation in power MOSFET devices and improve device performance and reliability.

[0006] One aspect of this application provides a semiconductor structure comprising: a semiconductor substrate including a plurality of alternating first regions and second regions, the surface of the semiconductor substrate including an epitaxial layer, the surface of the epitaxial layer including a current dispersing layer; a first doped region located in the current dispersing layer of the first region, the first doped regions in adjacent first regions being staggered in the y-direction; a second doped region located in the first doped region; a third doped region located in the current dispersing layer and spanning the first region and adjacent second regions, one end of the third doped region being connected to the second doped region in the first region, the other end of the third doped region extending into the second region, the third doped regions being staggered in the y-direction; and an electric field buffer located in the current dispersing layer of the second region and located between adjacent third doped regions.

[0007] In some embodiments of this application, the doping type of the first doped region is opposite to that of the current dispersing layer; the doping type of the second doped region is the same as that of the current dispersing layer; the doping type of the third doped region is opposite to that of the current dispersing layer; and the doping type of the electric field buffer is the same as that of the current dispersing layer.

[0008] In some embodiments of this application, the width of the second region is more than 20% of the width of the first region.

[0009] In some embodiments of this application, the electric field buffer is arranged in a column along the y-direction in the second region, and the electric field buffer and the third doped region located in the second region fill the second region.

[0010] In some embodiments of this application, the other end of the third doped region extends to the boundary of the second region away from the first region.

[0011] In some embodiments of this application, the width of the second region is more than 50% of the width of the first region.

[0012] In some embodiments of this application, the electric field buffers in the second region are arranged in two parallel columns along the y-direction, and the two columns of electric field buffers are respectively located at the two side boundaries of the second region adjacent to the first region.

[0013] In some embodiments of this application, the other end of the third doped region extends to the boundary of the second region away from the first region.

[0014] In some embodiments of this application, the third doped region is connected in the y-direction.

[0015] In some embodiments of this application, the semiconductor structure further includes: a fourth doped region located in the current dispersion layer of the second region, a portion of the fourth doped region being located in the electric field buffer zone of the second region, and the remainder of the fourth doped region being located in the current dispersion layer between the electric field buffer zones in the second region.

[0016] In some embodiments of this application, the doping type of the fourth doped region is opposite to the doping type of the current dispersing layer.

[0017] In some embodiments of this application, the semiconductor structure further includes: a gate layer, the gate layer being located on the surface of the current dispersing layer of the first region, the gate layer covering the three sides of the first doped region except for the side contacting the third doped region, and covering the corresponding three sides of the second doped region and the current dispersing layer between the first doped regions; the gate layer is divided into two layers: a gate electrode layer and a gate dielectric layer; the gate dielectric layer is located between the gate electrode layer and the current dispersing layer, and the gate electrode layer is located on top of the gate dielectric layer.

[0018] In some embodiments of this application, the semiconductor structure further includes: a first metal layer that covers the third doped region and extends to the surface of a second doped region connected to the third doped region, and spans and covers most of the electric field buffer and current dispersing layer of the second region; the first metal layer contacts the second doped region to form a source ohmic contact; the first metal layer contacts the third doped region to form a body diode ohmic contact; the first metal layer contacts the electric field buffer to form a Schottky contact; and the first metal layer contacts the current dispersing layer to form a Schottky contact.

[0019] In some embodiments of this application, the semiconductor structure further includes: a second metal layer located on the side of the semiconductor substrate opposite to the epitaxial layer; the second metal layer contacts the side of the semiconductor substrate opposite to the epitaxial layer and forms an ohmic contact.

[0020] In some embodiments of this application, the first region is used to form a power MOSFET device, the second region is used to form a Schottky diode, the first metal layer serves as both the source metal of the power MOSFET and the anode metal of the Schottky diode, and the second metal layer serves as both the drain metal of the power MOSFET and the cathode metal of the Schottky diode.

[0021] Another aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate including a plurality of alternating first regions and second regions, the surface of the semiconductor substrate including an epitaxial layer, the surface of the epitaxial layer including a current dispersing layer; forming a first doped region in the current dispersing layer of the first region, the first doped regions in adjacent first regions being alternately arranged in the y-direction; forming a second doped region in the first doped region; forming a third doped region in the current dispersing layer, the third doped region spanning the first region and adjacent second regions, one end of the third doped region being connected to the second doped region in the first region, the other end of the third doped region extending into the second region, the third doped regions being alternately arranged in the y-direction; forming an electric field buffer in the current dispersing layer of the second region, the electric field buffer being located between adjacent third doped regions.

[0022] In some embodiments of this application, the doping type of the first doped region is opposite to that of the current dispersing layer; the doping type of the second doped region is the same as that of the current dispersing layer; the doping type of the third doped region is opposite to that of the current dispersing layer; and the doping type of the electric field buffer is the same as that of the current dispersing layer.

[0023] In some embodiments of this application, the width of the second region is more than 20% of the width of the first region.

[0024] In some embodiments of this application, the electric field buffer is arranged in a column along the y-direction in the second region, and the electric field buffer and the third doped region located in the second region fill the second region.

[0025] In some embodiments of this application, the other end of the third doped region extends to the boundary of the second region away from the first region.

[0026] In some embodiments of this application, the width of the second region is more than 50% of the width of the first region.

[0027] In some embodiments of this application, the electric field buffers in the second region are arranged in two parallel columns along the y-direction, and the two columns of electric field buffers are respectively located at the two side boundaries of the second region adjacent to the first region.

[0028] In some embodiments of this application, the other end of the third doped region extends to the boundary of the second region away from the first region.

[0029] In some embodiments of this application, the third doped region is connected in the y-direction.

[0030] In some embodiments of this application, the method of forming the semiconductor structure further includes: forming a fourth doped region in the current dispersion layer of the second region, wherein a portion of the fourth doped region is located in the electric field buffer zone of the second region, and the remainder of the fourth doped region is located in the current dispersion layer between the electric field buffer zones in the second region.

[0031] In some embodiments of this application, the doping type of the fourth doped region is opposite to the doping type of the current dispersing layer.

[0032] In some embodiments of this application, the method of forming the semiconductor structure further includes: forming a gate layer on the surface of the current dispersing layer in the first region, the gate layer covering the three sides of the first doped region except for the side in contact with the third doped region, and covering the corresponding three sides of the second doped region and the current dispersing layer between the first doped regions; the gate layer is divided into two layers: a gate electrode layer and a gate dielectric layer; the gate dielectric layer is located between the gate electrode layer and the current dispersing layer, and the gate electrode layer is located on top of the gate dielectric layer.

[0033] In some embodiments of this application, the method of forming the semiconductor structure further includes: forming a first metal layer, the first metal layer covering the third doped region and extending to the surface of a second doped region connected to the third doped region, and spanning and covering most of the electric field buffer and current dispersing layer of the second region; the first metal layer contacting the second doped region to form a source ohmic contact; the first metal layer contacting the third doped region to form a body diode ohmic contact; the first metal layer contacting the electric field buffer to form a Schottky contact; and the first metal layer contacting the current dispersing layer to form a Schottky contact.

[0034] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming a second metal layer on the semiconductor substrate on the side opposite to the epitaxial layer; the second metal layer contacts the side of the semiconductor substrate opposite to the epitaxial layer to form an ohmic contact.

[0035] In some embodiments of this application, the first region is used to form a power MOSFET device, the second region is used to form a Schottky diode, the first metal layer serves simultaneously as the source metal of the power MOSFET and the anode metal of the Schottky diode, and the second metal layer serves simultaneously as the drain metal of the power MOSFET and the cathode metal of the Schottky diode.

[0036] This application provides a semiconductor structure and a method for forming the same, which can avoid secondary degradation in power MOSFET devices and improve device performance and reliability. Attached Figure Description

[0037] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0038] Figures 1 to 5 This is a schematic diagram of the semiconductor structure described in the first embodiment of this application;

[0039] Figures 6 to 11 This is a schematic diagram of the semiconductor structure described in the second embodiment of this application;

[0040] Figures 12 to 16 This is a schematic diagram of the semiconductor structure described in the third embodiment of this application;

[0041] Figures 17 to 22 This is a schematic diagram of the semiconductor structure described in the fourth embodiment of this application.

[0042] Attachment Number:

[0043] First Embodiment

[0044] 110 substrate 170 First District 120 Epitaxial layer 171 First doped region 130 Current dispersing layer 172 Second doped region 140 First metal layer 173 Third doped region 141a Source Ohm Contact 174 JFET region 141b Body diode ohmic contact 175 gate layer 142 Schottky Contact 175a Gate electrode layer 150 Interlayer dielectric layer 175b Gate oxide layer 160 Second metal layer 180 Second Zone 181 Electric field buffer

[0045] Second Embodiment

[0046]

[0047]

[0048] Third Embodiment

[0049] 310 substrate 170 First District 320 Epitaxial layer 371 First doped region 330 Current dispersing layer 372 Second doped region 340 First metal layer 373 Third doped region 341a Source Ohm Contact 374 JFET region 341b Body diode ohmic contact 375 gate layer 342 Schottky Contact 375a Gate electrode layer 350 Interlayer dielectric layer 375b Gate oxide layer 360 Second metal layer 380 Second Zone

[0050] Fourth embodiment

[0051]

[0052] Detailed Implementation

[0053] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0054] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0055] To address the issue of diode degradation caused by the development of stacking defects in the epitaxial layer of the body diode in power MOSFET devices under prolonged exposure to high current, leading to decreased diode conductivity, a MOSFET structure with an integrated Schottky junction (also known as JBSFET) has been proposed and applied. Because the forward voltage of the Schottky junction is lower than that of the PN junction of the body diode, it preferentially conducts when the reverse voltage rises, thereby reducing the current carried by the conductive diode and significantly decreasing the chance of diode degradation.

[0056] These devices possess the advantages of Schottky diodes, which have shorter reverse recovery times than ordinary PN diodes. Furthermore, because the Schottky junction and MOSFET structure are on the same bare die with a shorter physical distance, they not only have less switching loss than traditional MOSFET devices and higher switching speed, but they are even superior to power modules using Schottky freewheeling diodes.

[0057] However, a drawback of such devices is their weak short-circuit withstand capability. When the MOSFET is forward-biased, if a large surge current, such as that caused by a short circuit, flows through it, the temperature rise due to Joule heating will lead to a significant increase in the leakage current of the Schottky junction. The Joule heating generated by the leakage current then feeds back to raise the temperature, ultimately causing thermal runaway and damaging the device. Because silicon carbide has a higher thermal conductivity than silicon, heat spreads rapidly within the device crystal, so thermal runaway often damages the device before the gate driver's short-circuit protection mechanism is activated (approximately 3 to 5 microseconds).

[0058] Furthermore, most existing JBSFET structure designs only consider a small proportion of Schottky contacts to reduce the reverse current of the conductor diode and lower the reverse recovery time. The rated current ratio between the MOSFET section and the Schottky junction is often difficult to adjust flexibly. In most power module applications, an external freewheeling diode is still required to meet the rated reverse current requirements.

[0059] Based on the above-mentioned problems, this application provides a semiconductor structure and its formation method. It adds considerations to improve the flexibility of adjusting the rated current ratio between the MOSFET and the Schottky junction in the device, as well as to improve the short-circuit withstand capability, on the basis of the MOSFET structure with built-in Schottky junction. This can avoid the occurrence of secondary degradation in power MOSFET devices, achieve savings in external freewheeling diode devices, and improve device reliability.

[0060] It should be noted that the technical solution of this application can be implemented in various embodiments, and this application only uses four embodiments (first embodiment, second embodiment, third embodiment and fourth embodiment) as examples for illustration. However, this is not a limitation of this application. The technical solution of this application may also include any other implementation with the same technical concept as the technical solution of this application.

[0061] The various embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0062] Figures 1 to 5 This is a schematic diagram of the semiconductor structure described in the first embodiment of this application. Wherein, Figure 1 The image shown is a three-dimensional view of the semiconductor structure 100; Figure 2 The image shown is a top view of the semiconductor structure 100; Figure 3 This is a cross-sectional view of the semiconductor structure 100 along axis A-A; Figure 4 This is a cross-sectional view of the semiconductor structure 100 along axis B-B; Figure 5 This is a cross-sectional view of the semiconductor structure 100 along axis C-C. Figure 1 The upper surface of the structure shown and Figure 2 All shown are Figure 3 The structure shown has a cross section along axis X—X, and Figure 4 and Figure 5 The structure shown is a cross-section along the Y-Y axis. Figure 1 and Figure 2 The device structures in the diagram are all mirror-symmetrical about the S-axis, and are presented as simplified schematic diagrams. Figure 1 and Figure 2 Some labels have been omitted, but this should not affect the understanding of the structural content by relevant personnel. The semiconductor structure described in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0063] refer to Figures 1 to 5 As shown, the semiconductor structure 100 includes: a semiconductor substrate 110, the semiconductor substrate 110 including a plurality of alternating first regions 170 and second regions 180, the surface of the semiconductor substrate 110 including an epitaxial layer 120, and the surface of the epitaxial layer 120 including a current dispersing layer 130.

[0064] In some embodiments of this application, the semiconductor substrate 110 may be a silicon carbide substrate doped with impurity ions, such as an N-type doped silicon carbide substrate.

[0065] In some embodiments of this application, the first region 170 is used to form a power MOSFET device, and the second region 180 is used to form a Schottky diode.

[0066] refer to Figure 1 and Figure 2 As shown, in some embodiments of this application, the first region 170 and the second region 180 are repeatedly alternated in the y direction.

[0067] In some embodiments of this application, the width of the second region 180 is more than 20% of the width of the first region 170.

[0068] In some embodiments of this application, the material of the epitaxial layer 120 may include silicon carbide or other semiconductor materials, and the epitaxial layer 120 and the semiconductor substrate 110 have the same doping type. For example, the doping type of the epitaxial layer 120 is N-type. The thickness of the epitaxial layer 120 is from 2 micrometers to 150 micrometers.

[0069] In some embodiments of this application, the thickness of the current dispersing layer 130 is the depth of the first doped region plus 0.1 to 1 micrometer. The current dispersing layer 130 and the epitaxial layer 120 are made of the same material and have the same doping type, but the doping concentration of the current dispersing layer 130 is higher than that of the epitaxial layer 120. The doping type of the current dispersing layer 130 is, for example, N-type.

[0070] refer to Figures 1 to 4 As shown, the semiconductor structure 100 further includes a first doped region 171 located in the current dispersing layer 130 of the first region 170. The first doped region 171 extends from the upper surface of the current dispersing layer 130 into the current dispersing layer 130 along the z-direction. The first doped region 171 is arranged in parallel with two units in the x-direction and repeats along the y-direction. The first doped regions 171 in adjacent first regions 170 are staggered in the y-direction.

[0071] In some embodiments of this application, the depth of the first doped region 171 is the depth of the second doped region 172 plus 0.3 to 3 micrometers. The doping type of the first doped region 171 is opposite to that of the epitaxial layer 120. For example, the doping type of the first doped region 171 is p-type.

[0072] Continue to refer to Figures 1 to 4As shown, the region between the first doped region 171 and the first region 170 is also referred to as the JFET region 174. The width of the JFET region 174 can be from 0.5 micrometers to 2 micrometers.

[0073] Continue to refer to Figures 1 to 4 As shown, the semiconductor structure 100 further includes a second doped region 172 located within the first doped region 171. The second doped region 172 extends along the z-direction from the upper surface of the current dispersing layer 130 into the current dispersing layer 130.

[0074] In some embodiments of this application, the depth of the second doped region 172 is less than the depth of the first doped region 171, and can be 0.1 micrometers to 1 micrometer. The boundary distance between the second doped region 172 and the first doped region 171 is the channel length of the power MOSFET device in the semiconductor structure 100, and can be 0.2 micrometers to 1 micrometer. The second doped region 172 and the epitaxial layer 120 have the same doping type. The doping type of the second doped region 172 is, for example, N-type.

[0075] refer to Figure 1 , Figure 2 and Figure 5 As shown, the semiconductor structure 100 further includes a third doped region 173 located in the current dispersing layer 130. The third doped region 173 extends along the z-direction from the upper surface of the current dispersing layer 130 into the current dispersing layer 130. The third doped region 173 has a strip-like shape in the xy-plane and spans the first region 170 and the adjacent second region 180. One end of the third doped region 173 is connected to the second doped region 172 in the first region 170, and the other end of the third doped region 173 extends to the boundary of the second region 180 away from the first region 170. The third doped region 173 and the Schottky contact 142 alternate in the y-direction.

[0076] In some embodiments of this application, the depth of the third doped region 173 is the depth of the second doped region plus 0.3 to 3 micrometers. The width of the third doped region 173 in the y-direction is less than the width of the second doped region 172 in the y-direction. The third doped region 173 and the first doped region 171 have the same doping type, and the doping concentration of the third doped region 173 is higher than the doping concentration of the first doped region 171. The doping type of the third doped region 173 is, for example, p-type.

[0077] refer to Figures 1 to 3 and Figure 5As shown, the semiconductor structure 100 further includes an electric field buffer 181 located in the current dispersing layer of the second region 180. The electric field buffer 181 extends along the z-direction from the upper surface of the current dispersing layer 130 into the current dispersing layer 130.

[0078] In some embodiments of this application, the depth of the electric field buffer 181 can be from 0.1 micrometers to 3 micrometers. The width of the electric field buffer 181 in the x-direction can be from 0.5 micrometers to the width of the second region 180. The electric field buffer 181 and the epitaxial layer 120 have the same doping type, and the net doping concentration of the electric field buffer 181 is lower than the doping concentration of the current dispersing layer 130. The net doping concentration of the electric field buffer 181 is at most 80% of the doping concentration of the current dispersing layer 130.

[0079] refer to Figures 1 to 4 As shown, the semiconductor structure 100 further includes a gate layer 175 located on the surface of the current dispersing layer 130 in the first region 170. The gate layer 175 covers the three sides of the first doped region 171 except for the side contacting the third doped region 173, and covers the corresponding three sides of the second doped region 172 and the JFET region 174. The gate layer 175 is divided into two layers: a gate electrode layer 175a and a gate dielectric layer 175b. The gate dielectric layer 175b is located between the gate electrode layer 175a and the current dispersing layer 130, while the gate electrode layer 175a is located above the gate dielectric layer 175b.

[0080] In some embodiments of this application, the thickness of the gate dielectric layer 175b may be from 100 angstroms to 800 angstroms; the thickness of the gate electrode layer 175a may be from 0.1 micrometers to 1 micrometer.

[0081] Continue to refer to Figures 1 to 5 As shown, the semiconductor structure 100 further includes: a first metal layer 140, which covers the third doped region 173 and extends to the surface of the second doped region 172 connected to the third doped region, and spans and covers most of the electric field buffer zone 181 of the second region 180.

[0082] Continue to refer to Figures 1 to 5 As shown, the first metal layer 140 contacts the second doped region 172 to form a source ohmic contact 141a; the first metal layer 140 contacts the third doped region 173 to form a body diode ohmic contact 141b; and the first metal layer 140 contacts the electric field buffer 181 to form a Schottky contact 142.

[0083] Continue to refer to Figures 1 to 5As shown, the semiconductor structure 100 further includes a second metal layer 160 located on the side of the semiconductor substrate 110 opposite to the epitaxial layer 120. The second metal layer 160 forms an ohmic contact with the semiconductor substrate 110.

[0084] refer to Figure 4 As shown, the source ohmic contact 141a provides a source contact for the power MOSFET in the device, the body diode ohmic contact 141b provides a body diode contact for the power MOSFET in the device and provides grounding for the first doped region 171, and the first metal layer 140 serves as both the source metal of the power MOSFET formed in the first region 170 and the anode metal of the Schottky diode formed in the second region 180.

[0085] refer to Figure 5 As shown, the Schottky contact 142 is the main functional part of the Schottky diode in the device, and the second metal layer 160 serves as both the drain metal of the power MOSFET formed in the first region 170 and the cathode metal of the Schottky diode formed in the second region 180.

[0086] In some embodiments of this application, the first metal layer 140 and the second metal layer 160 may be composed of multiple metals or multiple layers of metals, such as nickel, titanium, platinum, aluminum, etc.

[0087] Continue to refer to Figure 1 , Figure 3 and Figure 4 As shown, the semiconductor structure 100 further includes an interlayer dielectric layer 150 located between the first metal layer 160 and the gate layer 175, for insulating between the gate and the source and for insulating and reducing gate-source leakage current (IGSS).

[0088] To clearly explain the structure and facilitate understanding, Figure 1 Part of the first metal layer and the gate layer were removed. Figure 2 The interlayer dielectric layer was omitted, and Figure 2 The first metal layer in the first area on the right is also omitted to facilitate the display of the underlying structure. This should be understood by relevant personnel.

[0089] In the technical solution of this application, each of the first regions 170 has two rows of first doped regions 171 arranged side by side along the y-direction. Therefore, the width of the first region 170 can be considered fixed, thereby adjusting the width of the second region 180 to achieve any rated current ratio between the first region 170 and the second region 180. Examples will be provided below.

[0090] For example, in some applications of switching power modules, the ratio of the rated current of the freewheeling diode to the rated current of the MOSFET is required to be 3:4, and the desired third-quadrant forward voltage is approximately 1.5V (the forward voltage of the MOSFET body diode is typically 2V to 3V). In some embodiments of this application, if the area ratio of the Schottky contact 142 to the ohmic contact 141b of the body diode is 1:1, then the width ratio of the second region 180 to the first region 170 must be at least 1:1. For instance, in the embodiment where the width of the first region 170 is 8 to 12 micrometers, the width of the second region 180 must also be 8 to 12 micrometers. The actual designed width and width ratio may need to take into account feature sizes and doping concentrations in each region.

[0091] Under the same application conditions as the aforementioned switching power module, and in conjunction with other embodiments of this application, if the area ratio of the Schottky contact 142 and the body diode ohmic contact 141b in the embodiment is 3:1, then the width ratio of the second region 180 and the first region 170 must be at least 2:3. For example, in the embodiment where the width of the first region 170 is 8 to 12 micrometers, the width of the second region 180 must be 5 to 8 micrometers. The actual designed width and width ratio may need to take into account feature sizes and doping concentrations in each region.

[0092] With a highly flexible rated current ratio between the first region 170 and the second region 180, the external freewheeling diode in power module applications can be fully integrated into the MOSFET device. In addition to the advantages of JBSFET, such as high switching frequency, low switching loss, and reduced diode degradation, the integration of the MOSFET device and the freewheeling diode device can greatly save the area and material occupied by the edge structure, since each individual device (bare die) requires an edge structure to withstand the high voltage at the boundary. Furthermore, since silicon carbide is more expensive than other semiconductors, the semiconductor structure of this application has a great advantage in reducing the cost of power module applications.

[0093] The technical solution of this application also provides several measures to improve the short-circuit thermal runaway problem and enhance the short-circuit withstand capability.

[0094] The third doped region 173 in the power MOSFET device serves to form a body diode and to provide grounding for the first doped region 171, ensuring that the potential difference between the gate dielectric layers 175b is the same as the input gate voltage at all times, thus ensuring the controllability and stability of the MOSFET channel switching.

[0095] First, the layout of this application's structure alternates the third doped regions 173 below the Schottky contact, enabling it to simultaneously suppress Schottky junction leakage current. When the MOSFET is forward-biased, the built-in JBS diode is reverse-biased, thus forming a depletion region in the PN junction between each third doped region 173 and the current dispersing layer 130. This pushes the highest electric field point from the Schottky contact surface deeper into the epitaxial layer 120, reducing the electric field at the Schottky junction and decreasing its leakage current. When a short circuit occurs, the drain-source voltage (VDS) surges, equivalent to a surge in the reverse voltage of the built-in JBS diode. The depletion region between the third doped region 173 and the current dispersing layer 130 expands significantly, and the rate and extent of this expansion are positively correlated with the peak voltage during a short circuit, effectively preventing the rise of Schottky leakage current in the first step of short-circuit thermal runaway.

[0096] Secondly, to further suppress the Schottky junction electric field and leakage current, an electric field buffer 181 is provided under the Schottky contact. The doping concentration of the electric field buffer 181 is lower than that of the current dispersion layer 130. Under the same reverse bias, the lower the doping concentration in the semiconductor, the larger the width of the depletion region. The function of the electric field buffer 181 is to increase the rate of depletion region expansion caused by the third doped region 173 during a short circuit, thereby shortening the device's response time to short-circuit thermal runaway.

[0097] Finally, in the first region 170, the JFET region 174 that conducts forward current can be considered as a longitudinal JFET region extending along the y-direction, located in the middle of the MOSFET portion, and several other lateral JFET regions extending along the x-direction. The Schottky contact boundary is separated from the longitudinal JFET region by at least one first doped region 171, effectively blocking the high electric field of the longitudinal JFET region. Each of the lateral JFET regions is misaligned with the Schottky contact 142 in the y-direction, ensuring that the high electric field of the lateral JFET region does not affect the Schottky contact surface and increase leakage current.

[0098] In different embodiments of the technical solution of this application, some or all of the third doped region 173 has the advantage of serving three purposes in one region, including forming the ground of the first doped region 171, forming the body diode of the MOSFET device, and suppressing the leakage current of the Schottky junction and preventing short-circuit thermal runaway as described above. This helps to improve the area utilization efficiency of the device and is of great benefit to the improvement of the device energy density and the saving of materials and costs.

[0099] refer to Figure 1 and Figures 3 to 5 As shown, a semiconductor substrate 110 is provided, and an epitaxial layer 120 is grown on the surface of the substrate 110 using a suitable process, such as vapor phase epitaxy. The doping concentration of the epitaxial layer 120 is 5 x 10⁻⁶. 14 Up to 1x1018 atom / cm 3 .exist Figure 1 and Figures 3 to 5 Only one epitaxial layer 120 is shown. Those skilled in the art will understand that, depending on actual needs, epitaxial layer 120 may include two or more layers to improve the flexibility of semiconductor device design and device performance.

[0100] Continue to refer to Figure 1 and Figures 3 to 5 As shown, a current dispersion layer 130 is formed on the surface of the epitaxial layer 120 using a suitable process, such as vapor phase epitaxy or ion implantation of the epitaxial layer 120; the implanted ion type is, for example, N-type, and the element is, for example, nitrogen or phosphorus; the ion implantation concentration is up to 5 x 10⁻⁶. 17 atom / cm 3 Injected energy is between 10 keV and 10 keV. 4 Within keV.

[0101] refer to Figures 1 to 3 and Figure 5 As shown, an electric field buffer 181 is formed in the current dispersing layer 130 of the second region 180. Specifically, the surface of the current dispersing layer 130 of the second region 180 is patterned to form a window corresponding to the electric field buffer 181, and reverse ion implantation is performed on the window. The type of implanted ions is opposite to the type of implanted ions in the epitaxial layer 120. The implanted ions in the electric field buffer layer 181 are, for example, p-type, and the element is, for example, boron or aluminum; the ion implantation concentration is more than 20 percent of the ion implantation concentration in the current dispersing layer 130; the implantation energy is between 10 keV and 10 keV. 4 Within keV.

[0102] refer to Figures 1 to 4 As shown, a first doped region 171 is formed in the current dispersing layer 130 of the first region 170. Specifically, the surface of the current dispersing layer 130 of the first region 170 is patterned to form a window corresponding to the first doped region 171, and ion implantation is performed on the window. The type of implanted ions is opposite to the type of implanted ions in the epitaxial layer 120. The implanted ions in the first doped region 171 are, for example, p-type, and the element is, for example, boron or aluminum; the ion implantation concentration is the ion implantation concentration of the current dispersing layer 130 plus 5 x 10. 14 atom / cm 3 Up to 1x10 19 atom / cm 3 Injected energy is between 10 keV and 10 keV. 4 Within keV.

[0103] Continue to refer to Figures 1 to 4As shown, a second doped region 172 is formed in the first doped region 171. Specifically, the surface of the first doped region 171 is patterned to form a window corresponding to the second doped region 172, and ion implantation is performed on the window. The implanted ion type is the same as the implanted ion type of the epitaxial layer 120. The implanted ions in the second doped region 172 are, for example, N-type, and the element is, for example, nitrogen or phosphorus; the ion implantation concentration is 1 x 10⁻⁶. 18 atom / cm 3 Up to 1x10 21 atom / cm 3 Injected energy is between 10 keV and 10 keV. 3 Within keV.

[0104] refer to Figures 1 to 3 and Figure 5 As shown, a third doped region 173 is formed on one side of the first doped region 171 near the boundary of the first region 170. Specifically, the surface of the current dispersing layer 130 is patterned to form a window corresponding to the third doped region 173, and ion implantation is performed on the window. The type of implanted ions is the same as the type of implanted ions in the first doped region 171. The implanted ions in the third doped region 173 are, for example, p-type, and the element is, for example, boron or aluminum; the ion implantation concentration is 1 x 10⁻⁶. 17 atom / cm 3 Up to 1x10 21 atom / cm 3 Injected energy is between 10 keV and 10 keV. 3 Within keV.

[0105] refer to Figures 1 to 4 As shown, a gate layer 175, comprising a gate electrode layer 175a and a gate dielectric layer 175b, is formed on the surface of the current dispersion layer 130. Specifically, a dielectric layer is formed on the surface of the current dispersion layer 130 using a suitable process, such as thermal oxidation, chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.; the material can be various oxides or dielectrics, such as silicon dioxide or aluminum oxide. A conductive layer is formed on the surface of the dielectric layer using a suitable process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.; the material can be various conductive materials, such as polycrystalline silicon, amorphous silicon, germanium silicon, and polycrystalline silicon carbide, etc. The surface of the conductive layer is patterned to form a window for etching the gate layer 175, and the conductive layer and dielectric layer are etched through the window to form the gate layer 175.

[0106] Continue to refer to Figures 1 to 4As shown, an interlayer dielectric layer 150 is formed on the upper surface of the device after the gate layer 175 is formed using a suitable process. The suitable process can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.; the material can be various oxides or dielectrics, such as plasma-enhanced tetraethoxysilane (PETEOS).

[0107] refer to Figures 1 to 5 As shown, ohmic contacts are formed on the surface of the first region 170, including a source ohmic contact 141a formed on the second doped region 172 and a body diode ohmic contact 141b formed on the third doped region 173. Specifically, the surface of the interlayer dielectric layer 150 is patterned to form windows for the ohmic contacts; a metal layer is deposited on the upper surface of the device, the material being, for example, nickel, titanium, platinum, aluminum, etc., the metal layer may be composed of multiple metals or multiple layers of metals; high-temperature annealing is performed to form the source ohmic contact 141a between the metal layer and the second doped region 172, and the body diode ohmic contact 141b between the metal layer and the third doped region 173, the annealing temperature may be within the range of 800 degrees Celsius to 1200 degrees Celsius; and excess metal in the metal layer is etched down to below the height of the interlayer dielectric layer 150.

[0108] refer to Figures 1 to 5 As shown, a Schottky contact 142 is formed on the surface of the second region 180. Specifically, the surface of the interlayer dielectric layer 150 is patterned to form the window of the Schottky contact 142; a metal layer is deposited on the upper surface of the device, the material being, for example, nickel, titanium, platinum, aluminum, etc., the metal layer may be composed of multiple metals or multiple layers of metals, and the metal may be different from the metal used to form the ohmic contact; high-temperature annealing is performed to form the Schottky contact 142 between the metal layer and the electric field buffer 181, the annealing temperature may be within 500 degrees Celsius to 900 degrees Celsius; optionally, the metal layer and the metal layer deposited when forming the ohmic contact may be directly combined to form the first metal layer 140 of the device; or the excess metal of the metal layer may be etched to a height below the interlayer dielectric layer 150, and then another one or more metals may be deposited to form the first metal layer 140 of the device.

[0109] Optionally, while reducing the number of process steps, the etching windows for ohmic contacts and the etching windows for Schottky contacts can be formed and metal deposited simultaneously. The annealing of the ohmic and Schottky contacts can be performed simultaneously at the same temperature, using the median of the annealing temperatures for the ohmic and Schottky contacts. Due to the different doping concentrations in each region, the metal layer will automatically form ohmic contacts with the highly doped second doped region 172 and the highly doped third doped region 173, and will automatically form Schottky contacts with the low-doped electric field buffer zone 181.

[0110] refer to Figure 1 , Figures 3 to 5 As shown, a second metal layer 160 is formed on the surface of the substrate 110 opposite to the epitaxial layer 120. Specifically, the second metal layer 160 is deposited on the surface, and the material is, for example, nickel, titanium, platinum, aluminum, etc. The second metal layer 160 can be composed of multiple metals or multiple layers of metals, and the material and structure of the second metal layer 160 can be different from the material and structure of the first metal layer 140; and high-temperature annealing is performed to form an ohmic contact between the metal layer and the substrate surface, and the annealing temperature can be within the range of 800 degrees Celsius to 1200 degrees Celsius.

[0111] The above describes the semiconductor structure 100 and its formation method in the first embodiment of the technical solution of this application. However, the technical solution of this application may have other embodiments. Three other semiconductor structure embodiments will be described below, including the semiconductor structure 200 of the second embodiment, the semiconductor structure 300 of the third embodiment, and the semiconductor structure 400 of the fourth embodiment. The semiconductor structures 200 to 400 are actually embodiments of implementing simple width adjustment of the second region 180 of the semiconductor structure 100 to increase the ratio of the rated current of the JBS diode to the MOSFET. However, in addition to extending all structures within the second region 180 simply along the x-direction, structural designs on other second regions to optimize device characteristics are also proposed. It should be noted that since the methods and processes for forming the semiconductor structures in different embodiments are the same, the formation methods of the semiconductor structures will not be described below. However, those skilled in the art should understand that the formation methods of semiconductor structures 200, 300, and 400 can also be easily understood from the formation method of the semiconductor structure 100 in the first embodiment.

[0112] Figures 6 to 11 This is a schematic diagram of the semiconductor structure 200 described in some embodiments of this application. Wherein, Figure 6 The image shown is a three-dimensional view of the semiconductor structure 200; Figure 7 The image shown is a top view of the semiconductor structure 200; Figure 8 This is a cross-sectional view of the semiconductor structure 200 along axis A-A; Figure 9 This is a cross-sectional view of the semiconductor structure 200 along axis B-B; Figure 10 This is a cross-sectional view of the semiconductor structure 200 along axis C-C; Figure 11 This is a cross-sectional view of the semiconductor structure 200 along axis D-D. Figure 6 The upper surface of the structure shown and Figure 7 All shown are Figure 8 The structure shown has a cross section along axis X—X, and Figures 9 to 11 The structure shown is a cross-section along the Y-Y axis. Figure 6 and Figure 7 The device structures in the diagram are all mirror-symmetrical about the S-axis, and are presented as simplified schematic diagrams. Figure 6 and Figure 7 Some labels have been omitted, but this should not affect the understanding of the structural content by relevant personnel. The semiconductor structure described in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0113] It should be noted that in the second embodiment, most of the semiconductor structure 200 and the semiconductor structure 100 are the same. Therefore, for the sake of brevity, the units and tens digits of the marking numbers for the parts of semiconductor structure 200 and semiconductor structure 100 that have the same function and purpose are marked the same, and will not be described in detail here, but simply explained.

[0114] refer to Figures 6 to 11 As shown, the semiconductor structure 200 includes: a semiconductor substrate 210, the semiconductor substrate 210 including a plurality of alternating first regions 270 and second regions 280, the surface of the semiconductor substrate 210 including an epitaxial layer 220, the surface of the epitaxial layer 220 including a current dispersing layer 230; a first doped region 271 located in the current dispersing layer 230 of the first region 270; a second doped region 272 located in the first doped region 271; a third doped region 273 located in the current dispersing layer 230, the third doped region 273 being strip-shaped, with one end connected to the second doped region 272 in the first region 270, and the other end of the third doped region 273 extending to the boundary of the second region 280 away from the first region 270, the third doped region 273 and Schottky contacts 242a and 242b alternating in the y-direction.

[0115] refer to Figures 6 to 7 , Figure 10 and Figure 11 As shown, the semiconductor structure 200 further includes an electric field buffer 281 located in the current dispersion layer of the second region 280. The electric field buffers 281 are arranged in two parallel columns along the y-direction in the second region 280, with each column located at one of the two boundaries of the second region 280 in the x-direction. The electric field buffers 281 extend from the boundary of the second region 280 towards its center in the x-direction. In some embodiments of this application, the width of the electric field buffer 281 in the x-direction can be from 0.5 micrometers to one-third of the width of the second region 280.

[0116] refer to Figures 6 to 9As shown, the semiconductor structure 200 further includes a gate layer 275 located on the surface of the current dispersing layer 230 in the first region 270. The gate layer 275 covers the three sides of the first doped region 271 except for the side contacting the third doped region 273, and covers the corresponding three sides of the second doped region 272 and the JFET region 274. The gate layer 275 is divided into two layers: a gate electrode layer 275a and a gate dielectric layer 275b. The gate dielectric layer 275b is located between the gate electrode layer 275a and the current dispersing layer 230, while the gate electrode layer 275a is located above the gate dielectric layer 275b.

[0117] refer to Figures 6 to 11 As shown, the semiconductor structure 200 further includes: a first metal layer 240, which covers the third doped region 273 and extends to the surface of the second doped region 272 connected to the third doped region, and spans and covers most of the electric field buffer 281 and current dispersion layer 230 of the second region 280.

[0118] Continue to refer to Figures 6 to 11 As shown, the first metal layer 240 contacts the second doped region 272 to form a source ohmic contact 241a; the first metal layer 240 contacts the third doped region 273 to form a body diode ohmic contact 241b; the first metal layer 240 contacts the current dispersing layer 230 to form a low-barrier Schottky contact 242a; and the first metal layer 240 contacts the electric field buffer 281 to form a high-barrier Schottky contact 242b.

[0119] Continue to refer to Figures 6 to 11 As shown, the semiconductor structure 200 further includes a second metal layer 260 located on the side of the semiconductor substrate 210 opposite to the epitaxial layer 220. The second metal layer 260 forms an ohmic contact with the semiconductor substrate 210.

[0120] refer to Figure 6 , Figure 8 and Figure 9 As shown, the semiconductor structure 200 further includes an interlayer dielectric layer 250 located between the first metal layer 260 and the gate layer 275, for insulation between the gate and the source.

[0121] To clearly explain the structure and facilitate understanding, Figure 6 Part of the first metal layer and the gate layer were removed. Figure 7 The interlayer dielectric layer was omitted, and Figure 7 The first metal layer in the first area on the right is also omitted to facilitate the display of the underlying structure. This should be understood by relevant personnel.

[0122] The semiconductor structure 200 is actually an embodiment of semiconductor structure 100 extending the second region 180 to increase the ratio of the rated current of the JBS diode to the MOSFET. However, in addition to all structures within the second region 180 that are simply extended along the x-direction, when the width of the second region is greater than 50% of the width of the first region, the electric field buffer can be divided into two columns and placed at the two side boundaries of the second region in the x-direction.

[0123] Continue to refer to Figures 6 to 11 As shown, in some embodiments of this application, since the Schottky contacts 242a and 242b of the semiconductor structure 200 are both arranged with the third doped region 273, the third doped region 273 still plays an excellent role in reducing the Schottky junction electric field, suppressing Schottky leakage current and preventing short-circuit thermal runaway, and at the same time provides grounding for the first doped region 271 and forms a body diode for the MOSFET device.

[0124] refer to Figures 6 to 8 As shown, the location in the second region 280 that is first affected by a short circuit is the Schottky contact at the boundary of the first region 270 in the x direction. Since this boundary is closest to the JFET region 274, it is most affected by the high current, high electric field, and high Joule heat during a short circuit in the JFET region 274. Therefore, it is necessary to set the electric field buffer 281 at the boundary for protection. The first metal layer 240 of the boundary region forms the electric field buffer 281 with a low doping concentration into a high barrier Schottky contact 242b to increase the forward voltage and suppress leakage current. However, the Schottky contact near the center of the second region 280x is far from the JFET region 274, and is therefore least affected by the high current, high electric field and high Joule heat during the short circuit of the JFET region 274. Thus, the electric field buffer zone in the center of the second region 280 can be removed, and the first metal layer 240 in the center of the second region 280 forms a low barrier Schottky contact 242a by the current dispersion layer 230 with a high contact doping concentration.

[0125] The forward voltage of the low-barrier Schottky contact 242a is lower than that of the high-barrier Schottky contact 242b, and the doping concentration of the current dispersing layer 230 below the low-barrier Schottky contact 242a is higher than that of the electric field buffer 281, resulting in a lower resistance of the current dispersing layer 230 than that of the electric field buffer 281. Therefore, in some embodiments of this application, removing the electric field buffer in the middle of the second region 280 can reduce the forward voltage and on-resistance of the JBS diode portion of the device without impairing the short-circuit withstand capability of the device.

[0126] Figures 12 to 16This is a schematic diagram of the semiconductor structure 300 described in some embodiments of this application. Wherein, Figure 12 The image shown is a three-dimensional view of the semiconductor structure 300. Figure 13 The image shown is a top view of the semiconductor structure 300; Figure 14 This is a cross-sectional view of the semiconductor structure 300 along axis A-A; Figure 15 This is a cross-sectional view of the semiconductor structure 300 along axis B-B; Figure 16 This is a cross-sectional view of the semiconductor structure 300 along axis C-C. Figure 12 The upper surface of the structure shown and Figure 13 All shown are Figure 14 The structure shown has a cross section along axis X—X, and Figure 15 and Figure 16 The structure shown is a cross-section along the Y-Y axis. Figure 12 and Figure 13 The device structures in the diagram are all mirror-symmetrical about the S-axis, and are presented as simplified schematic diagrams. Figure 12 and Figure 13 Some labels have been omitted, but this should not affect the understanding of the structural content by relevant personnel. The semiconductor structure described in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0127] It should be noted that in the third embodiment, most of the semiconductor structure 300 and semiconductor structure 200 are the same. Therefore, for the sake of brevity, the units and tens digits of the marking numbers for the parts of semiconductor structure 300 and semiconductor structure 200 that have the same function and purpose are marked the same, and will not be described in detail here, but simply explained.

[0128] refer to Figures 12 to 16 As shown, the semiconductor structure 300 includes: a semiconductor substrate 310, the semiconductor substrate 310 including a plurality of alternating first regions 370 and second regions 380, the surface of the semiconductor substrate 310 including an epitaxial layer 320, the surface of the epitaxial layer 320 including a current dispersing layer 330; a first doped region 371 located in the current dispersing layer 330 of the first region 370, the first doped regions 371 in adjacent first regions 370 being staggered in the y direction; and a second doped region 372 located in the first doped region 371.

[0129] refer to Figure 12 , Figure 13 and Figure 16As shown, the semiconductor structure 300 further includes: a third doping region 373, located in the current dispersion layer 330 of the first region 370, and having a portion protruding into the first region 370. The third doping region 373 at the center of the second region 380 is strip-shaped and alternates with the Schottky contact 342 in the y direction, and the strip-shaped portion extends in the x direction to and connects the second doping region 372 in the first region 370. The strip-shaped portion in the x direction can be referred to as the central strip-shaped portion. The third doping region 373 also has two strip-shaped portions along the two side boundaries of the second region 380 and extending in the y direction, connecting the central strip-shaped portion of each third doping region 373. The strip-shaped portion in the y direction can be referred to as the boundary strip-shaped portion. The third doping region 373 is in a shape of a Chinese character 'Mu' in the second region 380, and protrudes towards and connects to the second doping region 372 in the first region 370. In some embodiments of the present application, the central strip-shaped portion of the third doping region 373 in the second region 380 can also be rotated 90 degrees in the x-y plane, and form an arrangement where the central strip-shaped portion alternates with the Schottky contact 342 in the x direction.

[0130] Reference Figures 12 to 15 As shown, the semiconductor structure 300 further includes: a gate layer 375, located on the surface of the current dispersion layer 330 in the first region 370. The gate layer 375 covers three sides of the first doping region 371 except for the side contacting the third doping region 373, and covers the corresponding three sides of the second doping region 372 and the JFET region 374. The gate layer 375 is divided into two layers: a gate electrode layer 375a and a gate dielectric layer 375b. The gate dielectric layer 375b is located between the gate electrode layer 375a and the current dispersion layer 330, and the gate electrode layer 375a is located above the gate dielectric layer 375b.

[0131] Reference Figures 12 to 16 As shown, the semiconductor structure 300 further includes: a first metal layer 340, which covers the third doping region 373 and extends to the surface of the second doping region 372 connected to the third doping region, and straddles and covers most of the current dispersion layer 330 in the second region 380.

[0132] Continue to refer to Figures 12 to 16 As shown, the first metal layer 340 contacts the second doping region 372 and forms a source ohmic contact 341a; the first metal layer 340 contacts the third doping region 373 and forms a body diode ohmic contact 341b; the first metal layer 340 contacts the current dispersion layer 330 and forms a Schottky contact 342.

[0133] Continue to refer to Figures 12 to 16As shown, the semiconductor structure 300 further includes a second metal layer 360 located on the side of the semiconductor substrate 310 opposite to the epitaxial layer 320. The second metal layer 360 forms an ohmic contact with the semiconductor substrate 310.

[0134] refer to Figure 12 , Figure 14 and Figure 15 As shown, the semiconductor structure 300 further includes an interlayer dielectric layer 350 located between the first metal layer 360 and the gate layer 375, for insulation between the gate and the source.

[0135] To clearly explain the structure and facilitate understanding, Figure 12 Part of the first metal layer and the gate layer were removed. Figure 13 The interlayer dielectric layer was omitted, and Figure 13 The first metal layer in the first area on the right is also omitted to facilitate the display of the underlying structure. This should be understood by relevant personnel.

[0136] In JBS diodes, a unified P-type heavily doped region design provides stronger surge withstand capability compared to independent P-type heavily doped regions with the same total area. This is because the unified P-type heavily doped region shares a larger PN junction, while the independent P-type heavily doped regions are equivalent to numerous smaller PN junctions connected in parallel. The unified P-type heavily doped region can evenly distribute surge current across the entire larger PN junction, while the independent P-type heavily doped regions are more susceptible to device local conditions, leading to current congestion in one or more of the smaller PN junctions, causing hot spots and ultimately device failure.

[0137] refer to Figure 12 and Figure 13 As shown in some embodiments of this application, since the third doped regions 373 within the second region 380 of the semiconductor structure 300 are all interconnected, in addition to providing the basic functions of suppressing Schottky leakage current, providing grounding for the first doped region 371, and forming a body diode for the MOSFET device, the formed body diode also has higher surge withstand capability. In application environments where surge events are frequent and surge withstand capability requirements are high, such as environments with frequent lightning strikes or electrostatic discharges, it has a reliability advantage.

[0138] Figures 17 to 22 This is a schematic diagram of the semiconductor structure 400 described in some embodiments of this application. Wherein, Figure 17 The image shown is a three-dimensional view of the semiconductor structure 400. Figure 18 The image shown is a top view of the semiconductor structure 400; Figure 19This is a cross-sectional view of the semiconductor structure 400 along axis A-A; Figure 20 This is a cross-sectional view of the semiconductor structure 400 along axis B-B; Figure 21 This is a cross-sectional view of the semiconductor structure 400 along axis C-C; Figure 22 This is a cross-sectional view of the semiconductor structure 400 along axis D-D. Figure 17 The upper surface of the structure shown and Figure 18 All shown are Figure 19 The structure shown has a cross section along axis X—X, and Figures 20 to 22 The structure shown is a cross-section along the Y-Y axis. Figure 17 and Figure 18 The device structures in the diagram are all mirror-symmetrical about the S-axis, and are presented as simplified schematic diagrams. Figure 17 and Figure 18 Some labels have been omitted, but this should not affect the understanding of the structural content by relevant personnel. The semiconductor structure described in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0139] It should be noted that in the fourth embodiment, most of the semiconductor structure 400 and semiconductor structure 200 are the same. Therefore, for the sake of brevity, the units and tens digits of the marking numbers for the parts of semiconductor structure 400 and semiconductor structure 200 that have the same function and purpose are marked the same, and will not be described in detail here, but simply explained.

[0140] refer to Figures 17 to 22 As shown, the semiconductor structure 400 includes: a semiconductor substrate 410, which includes a plurality of alternating first regions 470 and second regions 480, an epitaxial layer 420 on the surface of the semiconductor substrate 410, and a current dispersing layer 430 on the surface of the epitaxial layer 420; a first doped region 471 located in the current dispersing layer 430 of the first region 470, wherein the first doped regions 471 in adjacent first regions 470 are staggered in the y-direction; a second doped region 472 located in the first doped region 471; and a third doped region 473 located in the current dispersing layer 430 and spanning the boundary between the first region 470 and the adjacent second region 480, wherein the third doped region 473 is granular and one end is connected to the second doped region 472 in the first region 470, and the other end of the third doped region 473 extends into the second region 480.

[0141] refer to Figures 17 to 19 and Figure 22As shown, the semiconductor structure 400 further includes an electric field buffer 481 located in the current dispersion layer of the second region 480. The electric field buffers 481 are arranged in two parallel columns along the y-direction in the second region 480, with each column located at one of the two side boundaries of the second region 480 in the x-direction. The electric field buffers 481 extend from the boundary of the second region 480 towards its center in the x-direction. In some embodiments of this application, the width of the electric field buffer 481 in the x-direction can be from 0.5 micrometers to one-third of the width of the second region 480.

[0142] refer to Figures 17 to 19 , Figure 21 and Figure 22 As shown, the semiconductor structure 400 further includes a fourth doped region 482, located in the current dispersion layer 430 of the second region 480. The fourth doped region 482 extends from the upper surface of the epitaxial layer 420 into the epitaxial layer 420. The fourth doped region 473 is granular, with a portion of the fourth doped region 473 located in the electric field buffer zone 481 of the second region 480, and the remaining fourth doped regions 473 located in the current dispersion layer 430 between the electric field buffer zones 481 of the second region 480. Their arrangement can be, for example, uniform.

[0143] In some embodiments of this application, the depth of the fourth doped region 482 can be from 0.5 micrometers to 5 micrometers. The spacing between the fourth doped regions 482 can be from 0.5 micrometers to 2 micrometers. The fourth doped region 482 and the third doped region 473 have the same doping type, and the doping concentration of the fourth doped region 482 can be equal to the doping concentration of the third doped region 473. The doping concentration of the fourth doped region 482 is 1 x 10⁻⁶. 17 Up to 1x10 21 atom / cm 3 .

[0144] Continue to refer to Figures 17 to 20 As shown, the semiconductor structure 400 further includes a gate layer 475 located on the surface of the current dispersing layer 430 in the first region 470. The gate layer 475 covers the three sides of the first doped region 471 except for the side contacting the third doped region 473, and covers the corresponding three sides of the second doped region 472 and the JFET region 474. The gate layer 475 is divided into two layers: a gate electrode layer 475a and a gate dielectric layer 475b. The gate dielectric layer 475b is located between the gate electrode layer 475a and the current dispersing layer 430, while the gate electrode layer 475a is located above the gate dielectric layer 475b.

[0145] Continue to refer to Figures 17 to 22As shown, the semiconductor structure 400 further includes: a first metal layer 440, which covers the third doped region 473 and extends to the surface of the second doped region 472 connected to the third doped region, and spans and covers most of the electric field buffer 481 and current dispersion layer 430 of the second region 480.

[0146] Continue to refer to Figures 17 to 22 As shown, the first metal layer 440 contacts the second doped region 472 to form a source ohmic contact 441a; the first metal layer 440 contacts the third doped region 473 or the fourth doped region 482 to form a body diode ohmic contact 441b; the first metal layer 440 contacts the current dispersing layer 430 to form a low-barrier Schottky contact 442a; and the first metal layer 440 contacts the electric field buffer 481 to form a high-barrier Schottky contact 442b.

[0147] Continue to refer to Figures 17 to 22 As shown, the semiconductor structure 400 further includes a second metal layer 460 located on the side of the semiconductor substrate 410 opposite to the epitaxial layer 420. The second metal layer 460 forms an ohmic contact with the semiconductor substrate 410.

[0148] refer to Figure 17 , Figure 19 and Figure 20 As shown, the semiconductor structure 400 further includes an interlayer dielectric layer 450 located between the first metal layer 460 and the gate layer 475, for insulation between the gate and the source.

[0149] This application also provides a method for forming a new structure in the semiconductor structure 400 in the fourth embodiment, in addition to the first to third embodiments.

[0150] refer to Figures 17 to 19 , Figure 21 and Figure 22 As shown, a fourth doped region 482 is formed in the current dispersion layer 430 and the electric field buffer 481 of the second region 480. Specifically, the surfaces of the current dispersion layer 430 and the electric field buffer 481 in the second region 480 are patterned to form a window corresponding to the fourth doped region 482, and ion implantation is performed on the window. The type of implanted ions is the same as that of the implanted ions in the first doped region 471. The implanted ions in the fourth doped region 482 are, for example, p-type, and the element is, for example, boron or aluminum; the ion implantation concentration is 1 x 10⁻⁶. 17 atom / cm 3 Up to 1x10 21 atom / cm 3 Injected energy is between 10 keV and 10 keV. 3Within keV.

[0151] Optionally, with the reduction of process steps, the ion implantation window for the fourth doped region 482 and the ion implantation window for the third doped region 473 can be formed and ion implanted simultaneously, and the ion implantation concentration and implantation energy for the fourth doped region 482 can be the same as those for the third doped region 473.

[0152] To clearly explain the structure and facilitate understanding, Figure 17 Part of the first metal layer and the gate layer were removed. Figure 18 The interlayer dielectric layer was omitted, and Figure 18 The first metal layer in the first area on the right is also omitted to facilitate the display of the underlying structure. This should be understood by relevant personnel.

[0153] The semiconductor structure 400 is essentially a segmentation of the strip-shaped third doped region 273 of the semiconductor structure 200, with the original third doped region located within the second region 280 after the segmentation designated as the fourth doped region. The segmented fourth doped region 482, like the strip-shaped third doped region 273, forms a depletion region in the PN junction between the fourth doped region 482 and the current dispersion layer 430, and between the fourth doped region 482 and the electric field buffer layer 481, when the MOSFET is forward-biased. This reduces the electric field of the Schottky junction in the second region 480, thereby reducing the leakage current of the Schottky junction. The width and expansion rate of the depletion region are positively correlated with the drain-source voltage value and its rise rate, effectively clamping the Schottky junction leakage current during short-circuit operation and preventing short-circuit thermal runaway.

[0154] Compared to the original strip-shaped third doped region 273, the granular fourth doped region 482 has a higher area ratio between the Schottky contact and the ohmic contact of the body diode, improving the area utilization efficiency of the second region 480 of the device without compromising its short-circuit withstand capability. Furthermore, the fourth doped region 482 is separated from the third doped region 473, making its design and parameters independent of the third doped region 473, such as its length, width, spacing, depth, and doping concentration. This allows for fine-tuning and control of the device's body diode performance, increasing the freedom of device design.

[0155] The second region 480 of the semiconductor structure 400 also has an electric field buffer 481, which allows the Schottky contact closest to the high electric field boundary of the second region 480 of the first region 470 to form a high-barrier Schottky contact 442b when the device is short-circuited. This increases the forward voltage of the boundary and the expansion rate of the depletion layer during a short circuit, providing higher Schottky leakage current suppression and short-circuit protection for the Schottky junction at the boundary of this region. The central portion of the second region 480 of the semiconductor structure 400 does not have an electric field buffer, but instead directly provides a low-barrier Schottky contact 442a that contacts the current dispersion layer 430, reducing the forward voltage and on-resistance of the JBS diode portion of the device while maintaining the short-circuit withstand capability of the device.

[0156] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0157] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0158] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0159] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0160] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor substrate, the semiconductor substrate comprising a plurality of alternating first regions and second regions, the surface of the semiconductor substrate comprising an epitaxial layer, the surface of the epitaxial layer comprising a current dispersing layer; The first doped region is located in the current dispersion layer of the first region, and the first doped regions in adjacent first regions are staggered in the y direction; The second doped region is located in the first doped region; A third doped region is located in the current dispersive layer and spans the first region and the adjacent second region. One end of the third doped region is connected to the second doped region in the first region, and the other end of the third doped region extends into the second region. The third doped regions are staggered in the y direction. An electric field buffer is located in the current dispersion layer of the second region and between adjacent third doped regions. The electric field buffers are arranged in two parallel columns along the y-direction in the second region. The two columns of electric field buffers are located at the two side boundaries of the second region adjacent to the first region. The doping type of the first doped region is opposite to that of the current-dispersing layer; the doping type of the second doped region is the same as that of the current-dispersing layer. The doping type of the third doping region is opposite to that of the current dispersing layer; the doping type of the electric field buffer is the same as that of the current dispersing layer.

2. The semiconductor structure as described in claim 1, characterized in that, The width of the second region is more than 20% of the width of the first region.

3. The semiconductor structure as described in claim 1, characterized in that, The other end of the third doped region extends to the boundary of the second region away from the first region.

4. The semiconductor structure as described in claim 1, characterized in that, The third doped region is connected in the y-direction.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: The fourth doped region is located in the current dispersion layer of the second region, a portion of the fourth doped region is located in the electric field buffer zone of the second region, and the remainder of the fourth doped region is located in the current dispersion layer between the electric field buffer zones in the second region.

6. The semiconductor structure as described in claim 5, characterized in that, The doping type of the fourth doped region is opposite to that of the current-dispersing layer.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: A gate layer is located on the surface of the current dispersion layer in the first region. The gate layer covers the three sides of the first doped region except for the side that contacts the third doped region, and covers the corresponding three sides of the second doped region and the current dispersion layer between the first doped regions. The gate layer is divided into two layers: a gate electrode layer and a gate dielectric layer. The gate dielectric layer is located between the gate electrode layer and the current dispersion layer, while the gate electrode layer is located on top of the gate dielectric layer.

8. The semiconductor structure as described in claim 7, characterized in that, Also includes: A first metal layer covers the third doped region and extends to the surface of a second doped region connected to the third doped region, and spans and covers most of the electric field buffer and current dispersion layer of the second region; the first metal layer contacts the second doped region to form a source ohmic contact; the first metal layer contacts the third doped region to form a body diode ohmic contact; the first metal layer contacts the electric field buffer to form a Schottky contact; the first metal layer contacts the current dispersion layer to form a Schottky contact.

9. The semiconductor structure as described in claim 8, characterized in that, Also includes: A second metal layer is located on the side of the semiconductor substrate opposite to the epitaxial layer; the second metal layer contacts the side of the semiconductor substrate opposite to the epitaxial layer and forms an ohmic contact.

10. The semiconductor structure as described in claim 9, characterized in that, The first region is used to form a power MOSFET device, the second region is used to form a Schottky diode, the first metal layer serves as both the source metal of the power MOSFET and the anode metal of the Schottky diode, and the second metal layer serves as both the drain metal of the power MOSFET and the cathode metal of the Schottky diode.

11. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a plurality of alternating first regions and second regions, the surface of the semiconductor substrate including an epitaxial layer including a current dispersing layer; A first doped region is formed in the current dispersion layer of the first region, and the first doped regions in adjacent first regions are alternately arranged in the y direction; A second doped region is formed in the first doped region; A third doped region is formed in the current dispersion layer. The third doped region spans the first region and an adjacent second region. One end of the third doped region is connected to the second doped region in the first region, and the other end of the third doped region extends into the second region. The third doped regions are alternately arranged in the y direction. An electric field buffer is formed in the current dispersion layer of the second region. The electric field buffer is located between adjacent third doped regions. The electric field buffer is arranged in two parallel columns along the y-direction in the second region. The two columns of electric field buffer are located at the two side boundaries of the second region adjacent to the first region. The doping type of the first doped region is opposite to that of the current-dispersing layer; the doping type of the second doped region is the same as that of the current-dispersing layer. The doping type of the third doping region is opposite to that of the current dispersing layer; the doping type of the electric field buffer is the same as that of the current dispersing layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The width of the second region is more than 20% of the width of the first region.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The other end of the third doped region extends to the boundary of the second region away from the first region.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, The third doped region is connected in the y-direction.

15. The method for forming a semiconductor structure as described in claim 11, characterized in that, Also includes: A fourth doped region is formed in the current dispersion layer of the second region, with a portion of the fourth doped region located in the electric field buffer zone of the second region, and the remainder of the fourth doped region located in the current dispersion layer between the electric field buffer zones in the second region.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The doping type of the fourth doped region is opposite to that of the current-dispersing layer.

17. The method for forming a semiconductor structure as described in claim 11, characterized in that, Also includes: A gate layer is formed on the surface of the current dispersion layer in the first region. The gate layer covers the three sides of the first doped region except for the side that contacts the third doped region, and covers the corresponding three sides of the second doped region and the current dispersion layer between the first doped regions. The gate layer is divided into two layers: a gate electrode layer and a gate dielectric layer. The gate dielectric layer is located between the gate electrode layer and the current dispersion layer, while the gate electrode layer is located on top of the gate dielectric layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, Also includes: A first metal layer is formed, which covers the third doped region and extends to the surface of the second doped region connected to the third doped region, and spans and covers most of the electric field buffer and current dispersion layer of the second region; the first metal layer contacts the second doped region and forms a source ohmic contact; the first metal layer contacts the third doped region and forms a body diode ohmic contact; the first metal layer contacts the electric field buffer and forms a Schottky contact; the first metal layer contacts the current dispersion layer and forms a Schottky contact.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, Also includes: A second metal layer is formed on the side of the semiconductor substrate opposite to the epitaxial layer; the second metal layer contacts the side of the semiconductor substrate opposite to the epitaxial layer and forms an ohmic contact.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The first region is used to form a power MOSFET device, the second region is used to form a Schottky diode, the first metal layer serves as both the source metal of the power MOSFET and the anode metal of the Schottky diode, and the second metal layer serves as both the drain metal of the power MOSFET and the cathode metal of the Schottky diode.

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