High write efficiency antifuse array

Abstract

The present invention discloses an antifuse array with high write efficiency, comprising at least one sub-memory array having two antifuse memory cells arranged side by side between two adjacent bit lines. The antifuse transistors of the two antifuse memory cells each include an antifuse gate with at least one sharp corner overlapping a first gate dielectric layer. The second gate dielectric layers of the select transistors of the two antifuse memory cells are interconnected, allowing the two antifuse memory cells to be connected to different bit lines, as well as to the same select line and word line. The present invention utilizes a configuration in which the source contact is shared and the two select transistors share a single channel. This configuration not only stabilizes the source architecture but also increases the channel width of the select transistor, thereby improving write efficiency without increasing the overall layout area.

Description

Technical Field

[0001] The present invention relates to an anti-fuse transistor, and more particularly to an anti-fuse array with high writing efficiency. Background Art

[0002] Antifuse transistors primarily use a capacitor to insert a dielectric layer between two conductors. During programming, a bias is applied to each conductor at both ends, causing the dielectric layer to collapse and break down. After programming, the resistance of the antifuse decreases. With the rapid development of integrated circuits, component sizes are shrinking. In recent years, the use of MOS devices to make antifuse transistors has been developed, with the programming method primarily based on the gate dielectric layer collapse mechanism. Because antifuse transistors rely on the rupture of the gate dielectric layer to form a permanent conductive path, their limitation is that a voltage sufficient to cause the gate dielectric layer to collapse must be applied. However, in conventional antifuse transistors, the interface between the antifuse gate and the gate dielectric layer is often a flat surface, with a uniform charge density. To achieve the goal of breaking down the gate dielectric layer, a high voltage is required, which in turn requires a relatively high current, resulting in a larger component area.

[0003] The applicant of this case has proposed a low voltage anti-fuse element and array, namely Taiwan Patent Application No. 109103372. Figure 1 The antifuse gate 2 of each antifuse memory cell 1 is designed to be shared by four gate dielectric layers 3, forming a sharp corner at the junction of the antifuse gate 2 and the gate dielectric layer 3. This utilizes the principle of tip discharge to reduce the breakdown voltage, reduce current consumption, and simultaneously reduce the device area. During a write operation, the select line SL1 or SL2 is grounded to select the antifuse memory cells 1 in the upper or lower row of the array. A low voltage is applied to the bit line BL1, and a low voltage is provided to the word line WL1 or WL2 to select a specific antifuse memory cell 1 in a row of the array to break through the gate dielectric layer 3. However, when this antifuse array selects an antifuse memory cell 1 for writing, other unselected antifuse memory cells are easily affected by the select bias, which may cause leakage current to flow through the bit line BL1 to the unselected antifuse memory cells. Furthermore, this source structure is not stable, which increases cost requirements. Furthermore, its write efficiency needs to be improved. Summary of the Invention

[0004] In view of the above problems, the main purpose of the present invention is to provide an antifuse array with high write efficiency. The antifuse array utilizes two select transistors sharing a channel, thereby increasing the channel width of the select transistors and improving write efficiency. The antifuse array also utilizes a shared source contact configuration to reduce the cell area, stabilize the source architecture, and thus reduce costs. At the same time, the present invention can reduce the number of control voltages and avoid the occurrence of leakage current.

[0005] Therefore, to achieve the above-mentioned objectives, the present invention provides an anti-fuse transistor with high write efficiency, comprising a plurality of parallel bit lines, word lines, select lines, and at least one sub-memory array. The bit lines extend in a first direction and include adjacent first and second bit lines; the word lines extend in a second direction, different from the first direction, perpendicular to the bit lines, and include a first word line; the select lines extend in a second direction, parallel to the word lines, and include a first select line; and the sub-memory array includes first and second anti-fuse memory cells. The first anti-fuse memory cell includes a first anti-fuse transistor and a first select transistor. The first anti-fuse transistor is connected to the first bit line. The first select transistor is connected in series to the first anti-fuse transistor and is connected to the first word line and the first select line. The second anti-fuse memory cell includes a second anti-fuse transistor and a second select transistor. The second anti-fuse transistor is connected to the second bit line. The second select transistor is connected in series to the second anti-fuse transistor and is connected to the first word line and the first select line. The first and second anti-fuse memory cells are adjacent to each other in the second direction and are located between the first and second bit lines.

[0006] The first anti-fuse transistor and the second anti-fuse transistor each include a first gate dielectric layer and an anti-fuse gate. The anti-fuse gate has one or more sharp corners overlapping the first gate dielectric layer. In one embodiment, the overlapping portion of the anti-fuse gate and each first gate dielectric layer forms at least one sharp corner. During operation, the higher density of charge at the sharp corner reduces the breakdown voltage, thereby reducing the current requirement for programming the anti-fuse memory cell and reducing the device area. The first selection transistor and the second selection transistor each include a second gate dielectric layer, and each second gate dielectric layer is connected to each other. In one embodiment, a first channel region is provided below the anti-fuse gate, and the first selection transistor and the second selection transistor share the second channel region, and the width of the second channel region is greater than the width of the first channel region. In this way, the channel width of the selection transistor can be increased, thereby improving write efficiency without increasing the overall layout area.

[0007] The following detailed description is made through specific embodiments in conjunction with the accompanying drawings, so that the objectives, technical contents, features and effects achieved by the present invention can be more easily understood. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a planar layout of an antifuse array in the prior art.

[0009] Figure 2 FIG. 1 is a planar layout of an antifuse array with high write efficiency according to the first embodiment of the present invention.

[0010] Figure 3 FIG. 4 is a planar layout of a sub-memory array according to the first embodiment of the present invention.

[0011] Figure 4 FIG. 4 is a planar layout of a sub-memory array according to a second embodiment of the present invention.

[0012] Figure 5 It is a structural cross-sectional view of an anti-fuse memory cell in a first direction according to a first embodiment of the present invention.

[0013] Figure 6 FIG. 1 is a cross-sectional view of the structure of two selection transistors of the anti-fuse memory cell in the second direction according to the first embodiment of the present invention.

[0014] 100 - first antifuse transistor; 100' - second antifuse transistor; 100" - third antifuse transistor; 100"' - fourth antifuse transistor; 102 - substrate; 104, 104', 104", 104"' - first gate dielectric layer; 106, 106' ...6" - third antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - first gate dielectric layer; 106" - first antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - fourth antifuse transistor; 106" - first gate dielectric layer; 106" - first antifuse transistor; 106" - first antifuse transistor; 106" - fourth antifuse transistor; 106", 106'" - antifuse gate; 108, 108', 108", 108'" - sharp corners; 110 - sidewall spacer; 112 - first ion-doped region; 114 - first channel region; 116 - LDD region; 120 - extension; 124 - well region; 200 - first select transistor; 200' - second select transistor; 200" - third select transistor; 200'" - fourth select transistor; 204, 204', 204", 204'" - second gate dielectric layer; 206, 206', 206", 206'" - select gate; 210 - sidewall spacer; 212 - second ion-doped region; 214 - second channel region; 216 - LDD region; BL1-BL3 - bit lines; WL1-WL4 - word lines; SL1 - select line. DETAILED DESCRIPTION

[0015] See also Figure 2A first embodiment of the present invention provides a high-write-efficiency antifuse array comprising a plurality of parallel bit lines 10 extending in a first direction. These bit lines 10 include bit lines BL1 to BL3, with bit line BL1 defining a first bit line 12 and bit line BL2 defining a second bit line 14. Furthermore, a plurality of parallel word lines 20 extending perpendicularly to the bit lines 10 extend in a second direction different from the first direction. These word lines 20 include word lines WL1 to WL4, with word lines WL1, WL2, WL3, and WL4 defining a first word line 22, a second word line 24, a third word line 26, and a fourth word line 28, respectively. Furthermore, a plurality of parallel select lines 30 extending parallel to the word lines 20 extend in a second direction. These select lines 30 include select line SL1, which defines a first select line 32. In this embodiment, the vertical direction is the first direction, and the horizontal direction is the second direction. The bit lines 10, word lines 20, and select lines 30 are connected to at least one sub-memory array 40. As shown in the figure, there are four sub-memory arrays 40 arranged in a 2*2 matrix. Each sub-memory array 40 is connected to one word line 20, one select line 30, and two bit lines 10. Because the connection relationship between each sub-memory array 40 and the word lines 20, select lines 30, and bit lines 10 is very similar, the following description will focus on the similarities.

[0016] Figure 3 Schematic diagram of two sub-memory arrays 40. The upper sub-memory array 40 includes a first antifuse memory cell 42 and a second antifuse memory cell 44, and is located between the first bit line 12 and the second bit line 14. The first antifuse memory cell 42 is connected to the first word line 22, the first select line 32, and the first bit line 12. The second antifuse memory cell 44 is connected to the first word line 22, the first select line 32, and the second bit line 14. The first and second antifuse memory cells 42 and 44 are adjacent to each other in the horizontal direction (i.e., the second direction), that is, they are located in the same row. The lower sub-memory array 40 includes a third antifuse memory cell 46 and a fourth antifuse memory cell 48, and is located between the first bit line 12 and the second bit line 14. The third antifuse memory cell 46 is connected to the third word line 26, the first select line 32, and the first bit line 12. The third and first antifuse memory cells 46 and 42 are adjacent to each other in the vertical direction (i.e., the first direction), that is, they are located in the same column. The fourth antifuse memory cell 48 is connected to the third word line 24, the first selection line 32 and the second bit line 14. The fourth antifuse memory cell 48 is located at the intersection of the horizontal direction of the third antifuse memory cell 46 and the vertical direction of the second antifuse memory cell 44. That is, the fourth antifuse memory cell 48 is located in the same row as the third antifuse memory cell 46, and in the same column as the second antifuse memory cell 44.

[0017] Because the first and second antifuse memory cells 42 and 44 and the third and fourth antifuse memory cells 46 and 48 are symmetrically arranged along the first selection line 32 and are all connected to the first selection line 32, they can share a source contact on the first selection line 32 and are connected to each other. Compared with a configuration method in which each antifuse memory cell is connected to different selection lines, a stable source structure can be achieved and the overall layout area can be reduced.

[0018] To further illustrate, the first anti-fuse memory cell 42 includes a first anti-fuse transistor 100 and a first select transistor 200 connected in series outside the first anti-fuse transistor 100. The first anti-fuse transistor 100 has a first gate dielectric layer 104 disposed on a substrate 102. The anti-fuse gate 106 has a sharp corner that overlaps the first gate dielectric layer 104. The anti-fuse gate 106 is connected to the first bit line 12, and a first ion-doped region (not shown) is connected to the first select line 32. The select gate 206 of the first select transistor 200 is connected to the first word line 22. The second gate dielectric layer 204 is disposed on the substrate 102, and a second ion-doped region (not shown) is connected to the first select line 32.

[0019] The second anti-fuse memory cell 44 includes a second anti-fuse transistor 100' and a second selection transistor 200' connected in series to the outside of the second anti-fuse transistor 100'. The second anti-fuse transistor 100' is provided with a first gate dielectric layer 104' on the substrate 102. The anti-fuse gate 106' has a sharp corner 108' overlapping the first gate dielectric layer 104', and the first gate dielectric layer 104' and other first gate dielectric layers share the same anti-fuse gate 106' (see FIG. Figure 2 ), the antifuse gate 106' is connected to the second bit line 14, and the first ion-doped region (not shown) is connected to the first select line 32. The select gate 206' of the second select transistor 200' is connected to the first word line 22, the second gate dielectric layer 204' is disposed on the substrate 102, and the second ion-doped region (not shown) is connected to the first select line 32. The second gate dielectric layer 204 of the first select transistor 200 and the second gate dielectric layer 204' of the second select transistor 200' are connected to each other.

[0020] The third anti-fuse memory cell 46 includes a third anti-fuse transistor 100" and a third selection transistor 200" connected in series to the outside of the third anti-fuse transistor 100". The third anti-fuse transistor 100" has a first gate dielectric layer 104" disposed on the substrate 102. The anti-fuse gate 106" has a sharp corner 108" overlapping the first gate dielectric layer 104". The anti-fuse gate 106" is connected to the first bit line 12, and the first ion doped region (not shown in the figure) is connected to the first selection line 32. The selection gate 206" of the selection transistor 200" is connected to the third word line 26, the second gate dielectric layer 204" is disposed on the substrate 102, and the second ion doped region (not shown in the figure) is connected to the first selection line 32.

[0021] The fourth anti-fuse memory cell 48 includes a fourth anti-fuse transistor 100"' and a fourth selection transistor 200"' connected in series to the outside of the fourth anti-fuse transistor 100"'. The fourth anti-fuse transistor 100"' is provided with a first gate dielectric layer 104"' on the substrate 102. The anti-fuse gate 106"' has a sharp corner 108"' overlapping the first gate dielectric layer 104"', and the first gate dielectric layer 104"' and other first gate dielectric layers share the same anti-fuse gate 106"' (see Figure 2 ), the antifuse gate 106'' is connected to the second bit line 14, and the first ion-doped region (not shown) is connected to the first selection line 32. The selection gate 206'' of the fourth selection transistor 200'' is connected to the third word line 28, and the second ion-doped region (not shown) is connected to the first selection line 32. The second gate dielectric layer 204'' of the third selection transistor 200'' and the second gate dielectric layer 204''' of the fourth selection transistor 200'' are connected to each other.

[0022] In this embodiment, the antifuse gates 106, 106', 106", and 106'" of the first, second, third, and fourth antifuse memory cells 42, 44, 46, and 48 respectively have a sharp corner 108 that overlaps with the first gate dielectric layer 104, 104', 104", and 104'" respectively. The two sharp corners 108' and 108'" on the left and right ends of the antifuse gates 106' and 106'" overlap with two different first gate dielectric layers, respectively. In other words, two adjacent antifuse memory cells (in the definition of the present invention, the two antifuse memory cells 44 and 48 belong to different sub-memory arrays 40) share a common antifuse gate. Furthermore, the overlapping portion of the first gate dielectric layer 104 and the antifuse gate 106 is in the shape of a triangle, forming a sharp corner 108. The angle of the sharp corner 108 is preferably less than or equal to 90 degrees. In practice, there is at least one sharp corner 108, preferably one, and multiple sharp corners can also be designed. The size of the sharp corner 108 is not limited and can be appropriately selected according to the preset write voltage and the thickness of the first gate dielectric layer. Figure 4 As shown, the second embodiment has another implementation of the anti-fuse gate 106, 106', 106", and 106'". In addition to having one or more sharp corners 108, 108', 108", and 108' overlapping the first gate dielectric layer 104, 104', 104", and 104'", the anti-fuse gate 106, 106', 106", and 106'" also extends a distance into the first gate dielectric layer 104, 104', 104", and 104'". In the second embodiment, the overlapping portions of the first gate dielectric layers 104, 104', 104", and 104'" and the antifuse gates 106, 106', 106", and 106'" form a pentagon. This pentagon includes two parallel opposite sides and two intersecting oblique sides extending from the two parallel opposite sides. The two oblique sides intersect to form a sharp corner 108, 108', 108", and 108'" respectively. The present invention utilizes a shared antifuse gate configuration to reduce the antifuse gate area, thereby reducing device size and lowering current consumption.

[0023] Next, the detailed structures of the first, second, third, and fourth antifuse memory cells 42, 44, 46, and 48 are described. Since the cross-sectional structures of each antifuse memory cell are substantially the same, only the first antifuse memory cell 42 is used as a representative. Figure 5As shown, the first anti-fuse transistor 100 and the first select transistor 200 connected in series therewith have a well region 124 disposed on a substrate 102. The first anti-fuse transistor 100 includes a first gate dielectric layer 104, an anti-fuse gate 106, sidewall spacers 110, a first ion-doped region 112, and a first channel region 114. The first gate dielectric layer 104 is formed on the well region 124, the anti-fuse gate 106 is disposed at a corner of the first gate dielectric layer 104, the first channel region 114 is formed below the anti-fuse gate 106, the sidewall spacers 110 are formed outside the anti-fuse gate 106, and the first ion-doped region 112 is formed in the well region 124 on one side of the first gate dielectric layer 104. The first ion-doped region 112 may include a lightly doped (LDD) region 116 adjacent to a vertical edge of the first gate dielectric layer 104. The first select transistor 200 includes a second gate dielectric layer 204, a select gate 206, sidewall spacers 210, a second ion-doped region 212, and a second channel region 214. The second gate dielectric layer 204 is disposed on the well region 124 and is connected to the first gate dielectric layer 104. The select gate 206 covers the second gate dielectric layer 204, with a second channel region 214 formed thereunder. Sidewall spacers 210 are formed on both sides of the second gate dielectric layer 206. The first ion-doped region 112 is formed on one side of the second gate dielectric layer 204, and the second ion-doped region 212 is formed on the other side of the second gate dielectric layer 204, that is, in the well region 124 on the side of the second gate dielectric layer 204 away from the first ion-doped region 112. The second ion-doped region 212 may have a lightly doped (LDD) region 216 adjacent to a vertical edge of the second gate dielectric layer 204. The first ion-doped region 112 and the second ion-doped region 212 may be doped with the same type of ions, while the first ion-doped region 112 and the well region 124 may be doped with different types of ions and may have different doping concentrations depending on the desired operating voltage.

[0024] In this embodiment, the substrate 102 can be a P-type semiconductor substrate or an N-type semiconductor substrate. When the substrate 102 is a P-type semiconductor substrate, the first ion-doped region 112 and the second ion-doped region 212 are N-type doped regions, and the well region 124 is a P-type doped region. When the substrate 102 is an N-type semiconductor substrate, the first ion-doped region 112 and the second ion-doped region 212 are P-type doped regions, and the well region 124 is an N-type doped region. The first gate dielectric layer 104 is a gate oxide having a relatively thin and substantially uniform thickness below the antifuse gate 106. The material thereof can be selected from an oxide layer, a nitride layer, an oxynitride layer, a metal oxide layer, and combinations thereof. Each antifuse memory cell of the above-described embodiment can be manufactured using any standard CMOS process, such as the formation of sidewall spacers, lightly doped (LDD), and gate silicidation. The second gate dielectric layer 204 is formed at the same time as the first gate dielectric layer 108 . Therefore, the second gate dielectric layer 204 and the first gate dielectric layer 104 have substantially the same composition and may have the same or different thicknesses.

[0025] At the same time Figure 6 As shown, the first antifuse memory cell 42 and the second antifuse memory cell 44 share a second channel region 214. The second gate dielectric layer 204 of the first select transistor 200 and the second gate dielectric layer 204' of the second select transistor 200' are connected to each other, allowing the first select transistor 200 and the second select transistor 200' to share the second channel region 214, and the width of the second channel region 214 is greater than the width of the first channel region 114. The present invention utilizes a configuration in which two select transistors share a channel to increase the channel width of the select transistors and improve write efficiency without increasing the overall layout area.

[0026] During a write operation, the first select line 32 is grounded, and a low voltage is applied to the first bit line 12 or the second bit line 14 to select the antifuse memory cells 44, 48 in the right column or the antifuse memory cells 42, 46 in the left column of the sub-memory array. A low voltage is also applied to the first word line 22 or the third word line 26 to select a specific antifuse memory cell in a column of the sub-memory array 40 to break through the first gate dielectric layer 104. For example, by grounding the first select line 32, applying a low voltage to the first bit line 14, and applying a low voltage to the first word line 24, the first antifuse memory cell 44 is selected as the memory cell to be written.

[0027] The present invention uses word lines instead of select lines to select the antifuse memory cell for writing, freeing other antifuse memory cells from the influence of the selection bias voltage, thereby reducing leakage current. Furthermore, the present invention utilizes the principle of tip discharge, where at least one corner of the antifuse gate overlaps with the first gate dielectric layer. Because charge is concentrated at the corner, the resulting electric field is stronger, reducing the write voltage required to break down the portion of the first gate dielectric layer below the corner, making it more susceptible to breakdown and shortening write time.

[0028] In summary, the high-write efficiency antifuse array provided by the present invention is based on a shared antifuse gate architecture. Each of its antifuse transistors includes an antifuse gate having one or more sharp corners overlapping a first gate dielectric layer. Furthermore, the second gate dielectric layers of the select transistors of the two antifuse memory cells are connected to each other, allowing the two antifuse memory cells to be connected to different bit lines, as well as the same select line and word line. The present invention utilizes two select transistors sharing a single channel, increasing the channel width of the select transistors and maximizing the current flowing during breakdown. This improves the success rate and robustness of breakdown, while also increasing write efficiency. Furthermore, the shared source contact configuration allows for a robust source architecture and reduces the overall layout area. Furthermore, the minimum control voltage can be used to provide maximum current, reducing leakage current and ultimately lowering manufacturing costs.

[0029] The above description illustrates the features of the present invention through embodiments, and its purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly, rather than to limit the scope of the present invention. Therefore, any other equivalent modifications or amendments that do not depart from the spirit disclosed by the present invention should still be included in the claims.

Claims

1. An antifuse array with high write efficiency, characterized in that: Include: A plurality of parallel bit lines extending in a first direction and including a first bit line and a second bit line adjacent to each other; A plurality of parallel word lines extending in a second direction different from the first direction and perpendicular to the plurality of bit lines, and including a first word line; a plurality of parallel selection lines extending in the second direction and parallel to the plurality of word lines, and including a first selection line; and At least one sub-memory array, the sub-memory array comprising a first anti-fuse memory cell and a second anti-fuse memory cell, the first anti-fuse memory cell comprising: a first anti-fuse transistor connected to the first bit line; and a first select transistor connected in series to the first anti-fuse transistor and connected to the first word line and the first select line; the second anti-fuse memory cell comprising: a second anti-fuse transistor connected to the second bit line; and a second select transistor connected in series to the second anti-fuse transistor and connected to the first word line and the first select line; the first and second anti-fuse memory cells are adjacent to each other in the second direction and are located between the first bit line and the second bit line; The first anti-fuse transistor and the second anti-fuse transistor each include a first gate dielectric layer and an anti-fuse gate, wherein the anti-fuse gate has at least one sharp corner overlapping the first gate dielectric layer. The first select transistor and the second select transistor each include a second gate dielectric layer, and each second gate dielectric layer is connected to each other. A first channel region is provided below the anti-fuse gate, and the first selection transistor and the second selection transistor share a second channel region, wherein the width of the second channel region is greater than the width of the first channel region; The first antifuse memory cell and the second antifuse memory cell are disposed between the first bit line and the second bit line; The first gate dielectric layer and the second gate dielectric layer are connected to each other.

2. The antifuse array with high write efficiency according to claim 1, wherein: The overlapping portion of the first gate dielectric layer and the anti-fuse gate is in a triangle shape.

3. The antifuse array with high write efficiency according to claim 1, wherein: The overlapping portion of the first gate dielectric layer and the antifuse gate is a pentagon. The pentagon includes two parallel opposite sides and two oblique sides extending from and intersecting the two parallel opposite sides.

4. The antifuse array with high write efficiency according to claim 1, wherein: The first anti-fuse transistor comprises: The anti-fuse gate is disposed on a substrate and connected to the first bit line; The first gate dielectric layer is disposed between the antifuse gate and the substrate; and a first ion-doped region disposed in the substrate on one side of the first gate dielectric layer and connected to the first selection line; The first selection transistor comprises: a selection gate disposed on the substrate and connected to the first word line; a second gate dielectric layer disposed between the select gate and the substrate; and A second ion doping region is disposed in the substrate on a side of the second gate dielectric layer away from the first ion doping region and connected to the first selection line. The second ion doping region and the first ion doping region are doped with the same type of ions.

5. The antifuse array with high write efficiency according to claim 1, wherein: The second anti-fuse transistor comprises: The anti-fuse gate is disposed on a substrate and connected to the second bit line; The first gate dielectric layer is disposed between the antifuse gate and the substrate; and a first ion-doped region disposed in the substrate on one side of the first gate dielectric layer and connected to the first selection line; The second selection transistor comprises: a selection gate disposed on the substrate and connected to the first word line; a second gate dielectric layer disposed between the select gate and the substrate; and A second ion doping region is disposed in the substrate on a side of the second gate dielectric layer away from the first ion doping region and connected to the first selection line. The second ion doping region and the first ion doping region are doped with the same type of ions.

6. The antifuse array with high write efficiency according to claim 4 or 5, characterized in that: If the substrate is a P-type semiconductor substrate, the second ion-doped region and the first ion-doped region are N-type doped regions.

7. The antifuse array with high write efficiency according to claim 4 or 5, characterized in that: The substrate is an N-type semiconductor substrate, and the second ion-doped region and the first ion-doped region are P-type doped regions.

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