Quantum bit components, quantum bit component fabrication methods, chips and equipment

Abstract

This application relates to a quantum bit component, a method for fabricating a quantum bit component, a chip, and an apparatus, and pertains to the field of micro-nano fabrication technology. The quantum bit component includes: a substrate, a superconducting circuit layer, a metal layer under the bump, and solder joints; the superconducting circuit layer is located on the substrate; the metal layer under the bump is located on the superconducting circuit layer, and the metal layer under the bump forms a superconducting connection with the superconducting circuit layer; the material of the metal layer under the bump is niobium; the solder joint is located on the metal layer under the bump, and the solder joint forms a superconducting connection with the metal layer under the bump. Since the oxide layer on the surface of niobium is easier to remove than the oxide layer on the surface of other superconducting materials, thus forming a better superconducting contact with the solder joint, the above solution can greatly improve the superconducting performance between two planar superconducting quantum chips in a flip-chip superconducting quantum chip, thereby improving the performance of the flip-chip superconducting quantum chip.

Description

Technical Field

[0001] This application relates to the field of micro-nano fabrication technology, and in particular to a quantum bit component, a method for fabricating a quantum bit component, a chip, and an apparatus. Background Technology

[0002] The flip-chip bonding superconducting quantum chip packaging process is a process that involves bonding two planar quantum chips together using a superconducting material to obtain a flip-chip bonding superconducting quantum chip.

[0003] In flip-chip superconducting quantum chip manufacturing processes, an under-bump metal (UBM) layer is typically placed between the superconducting circuit layer and the solder joints to prevent alloy formation between the solder joints and the superconducting circuit layer, which could damage the superconducting circuit structure. In related technologies, the UBM layer is usually made of gold.

[0004] Then, since gold is a non-superconducting material and the gold stripping process is difficult, residual gold particles will affect the cleanliness of the aluminum superconducting circuit layer, thereby affecting the performance of the flip-chip superconducting quantum chip. Summary of the Invention

[0005] This application provides a quantum bit component, a method for fabricating a quantum bit component, a chip, and an apparatus, which can improve the performance of flip-chip superconducting quantum chips. The technical solution is as follows.

[0006] On one hand, a quantum bit assembly is provided for flip-chip bonding of a superconducting quantum chip; the quantum bit assembly includes: a substrate, a superconducting circuit layer, a metal layer under the bumps, and solder joints;

[0007] The superconducting circuit layer is located on the substrate;

[0008] The under-bump metal layer is located on the superconducting circuit layer, and the under-bump metal layer forms a superconducting connection with the superconducting circuit layer; the material of the under-bump metal layer is niobium.

[0009] The solder joint is located on the metal layer under the bump, and the solder joint forms a superconducting connection with the metal layer under the bump.

[0010] On the other hand, a method for fabricating a quantum bit component is provided, the method comprising:

[0011] Fabrication of a superconducting circuit layer on a substrate;

[0012] A bump-type undermetal layer is prepared on the upper surface of the superconducting circuit layer; the bump-type undermetal layer forms a superconducting connection with the superconducting circuit layer; the material of the bump-type undermetal layer is niobium.

[0013] Solder joints are prepared on the upper surface of the metal layer under the bump to obtain a quantum bit assembly for flip-chip bonding of a superconducting quantum chip; the solder joints form a superconducting connection with the metal layer under the bump.

[0014] On another front, a flip-chip superconducting quantum chip is provided, the flip-chip superconducting quantum chip comprising two qubit components as described above;

[0015] The two quantum bit components are welded together by solder joints.

[0016] On the other hand, a computer device is provided that includes a flip-chip superconducting quantum chip as described above.

[0017] On the other hand, a production line equipment is provided, comprising: a lithography machine, a vapor deposition machine, and an ion beam etching machine; the lithography machine, the vapor deposition machine, and the ion beam etching machine are used to collaboratively fabricate the quantum bit components as described above.

[0018] The beneficial effects of the technical solutions provided in this application include at least the following:

[0019] By placing a niobium bump under-bump metal layer between the superconducting circuit layer and the solder joint in the qubit assembly of a flip-chip superconducting quantum chip, the superconducting performance between the two planar superconducting quantum chips can be greatly improved, thereby enhancing the performance of the flip-chip superconducting quantum chip. Niobium is a superconducting material, and it is easier to peel off than gold, resulting in less impact on the cleanliness of the superconducting circuit layer. Furthermore, the oxide layer on the niobium surface is easier to remove than oxide layers on other superconducting materials, thus forming a better superconducting contact with the solder joint.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0022] Figure 1 This is a schematic diagram of the structure of the quantum bit component involved in this application;

[0023] Figure 2 This is a flowchart illustrating a method for fabricating a quantum bit component according to an exemplary embodiment of this application;

[0024] Figure 3This is a schematic diagram of the fabrication framework of the quantum bit component involved in this application;

[0025] Figure 4 This is a flowchart illustrating a method for fabricating a quantum bit component according to an exemplary embodiment of this application;

[0026] Figure 5 yes Figure 4 The illustrated embodiment is a schematic diagram of the preparation of a niobium metal film.

[0027] Figure 6 yes Figure 4 Comparison diagram of niobium films involved in the embodiments shown;

[0028] Figure 7 yes Figure 4 The illustrated embodiment is a schematic diagram of the etching profile.

[0029] Figure 8 yes Figure 4 Electron microscopy images of niobium film surfaces under different gas pressures in the illustrated embodiments;

[0030] Figure 9 yes Figure 4 Electron microscopy images of the niobium film surface at different distances in the illustrated embodiments;

[0031] Figure 10 yes Figure 4 Electron microscopy images of niobium film surfaces at different coating powers in the illustrated embodiments;

[0032] Figure 11 yes Figure 4 A schematic diagram of the superconducting transition temperature of niobium film samples under different coating powers in the illustrated embodiment;

[0033] Figure 12 yes Figure 4 The illustrated embodiment shows the natural oxidation characteristic curves of the niobium film.

[0034] Figure 13 This is a schematic diagram illustrating an application scenario of a solution provided in one embodiment of this application;

[0035] Figure 14 This is a schematic diagram of a production line equipment shown in an exemplary embodiment of this application. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0037] A qubit (qubit) is a unit of measurement for quantum information in quantum information science. Unlike a classical bit, which can only be in either a 0 or 1 state, a qubit can be in both 0 and 1 states simultaneously, i.e., a quantum superposition of 0 and 1.

[0038] Josephson junction: also known as a superconducting tunnel junction. It is generally a structure consisting of two superconductors sandwiched by a very thin barrier layer (thickness ≤ the coherence length of a Cooper pair), such as an S (superconductor)-I (semiconductor or insulator)-S (superconductor) structure, abbreviated as SIS. In a Josephson junction, superconducting electrons can tunnel from one side through the semiconductor or insulator film to the other side via the tunneling effect.

[0039] Superconducting circuits: When the ambient temperature drops to a certain threshold, the resistance of some materials disappears, and superconductivity occurs. Circuit structures made from these materials are called superconducting circuits.

[0040] Quantum chip: A chip based on the laws of quantum mechanics. In particular, when the selected carrier is a superconducting quantum circuit and a Josephson junction, the chip is called a superconducting quantum chip.

[0041] Superconducting quantum chips are one of the important carriers for quantum computing research. They generally consist of a substrate, a waveguide layer (also known as a large-circuit structure), a qubit structure, and other structures. The main function of the waveguide layer is to transmit the microwave and electromagnetic fields that control the qubits. Theoretically, considering the losses of microwaves and electromagnetic fields, a relatively thicker waveguide layer is preferable, as this results in better device performance, such as the Q value. Since current qubit structures are mainly Josephson junctions, the double-tilt evaporation method limits the thickness of the superconducting layer in the junction region and the connection between the junction and the external circuit. Therefore, the thickness of the waveguide layer in the large-circuit structure is also subject to corresponding limitations.

[0042] Flip-chip superconducting quantum chips: As the number of qubits increases, simple planar quantum chip designs are limited by size and difficult to scale. This led to the development of flip-chip superconducting quantum chip packaging technology. The process mainly includes: fabricating contact solder joints on two chips (top and bottom) used for the flip-chip bonding process; and then bonding the top and bottom chips together using these solder joints.

[0043] Under-Bump Metal (UBM) Layer in Flip-Chip Superconducting Quantum Chips: During the fabrication of the contact solder joints between the top and bottom wafers, the superconducting circuit structure of the top and bottom wafers is formed by etching an aluminum film. However, the indium material used for the contact solder joints tends to alloy with aluminum, preventing superconductivity and thus compromising the superconducting circuit structure. Therefore, an under-bump metal (UBM) layer is often introduced as a medium between the indium pillar solder joints and the top (bottom) wafers during the fabrication of indium pillar solder joints. The UBM layer needs to achieve good superconducting contact with both the top (bottom) wafers and the indium pillar solder joints.

[0044] Magnetron sputtering coating: Magnetron sputtering coating is a common coating method. Its basic principle is that electrons collide with gas molecules (usually nitrogen or argon molecules) under the combined action of electric and magnetic fields, producing nitrogen or argon cations. The cations bombard the target surface, causing the target atoms to evaporate onto the substrate surface.

[0045] Niobium: A superconducting metallic material with a superconducting transition temperature of approximately 9K.

[0046] Ion beam etching: a physical etching method. Its basic principle is that electrons collide with inert gas molecules (usually argon molecules) to produce cations. These cations are accelerated and bombard the sample surface under the action of an electric field to achieve a physical etching effect.

[0047] The embodiments of this application provide a qubit assembly for flip-chip superconducting quantum chips. For example, the qubit assembly can be a monolithic planar superconducting quantum chip within a flip-chip superconducting quantum chip, or it can be a part of the aforementioned planar superconducting quantum chip. Please refer to... Figure 1 This illustrates a schematic diagram of the structure of a quantum bit assembly as shown in an exemplary embodiment of this application. Figure 1 As shown, the quantum bit assembly may include a substrate 101, a superconducting circuit layer 102, a metal layer under the bumps 103, and solder joints 104.

[0048] The superconducting circuit layer 102 is located on the substrate 101;

[0049] The under-bump metal layer 103 is located on the superconducting circuit layer 102, and the under-bump metal layer 103 and the superconducting circuit layer 102 form a superconducting connection; the material of the under-bump metal layer 103 is niobium.

[0050] Solder joint 104 is located on the under-bump metal layer 103, and solder joint 104 and under-bump metal layer 103 form a superconducting connection.

[0051] In one possible implementation, the solder joint 104 is made of indium metal.

[0052] In one possible implementation, the superconducting circuit layer 102 is made of aluminum.

[0053] In the embodiments of this application, good superconducting contact can be formed between indium and niobium, and good superconducting contact can also be formed between niobium and the superconducting circuit layer. At the same time, niobium, as the under-bump metal layer, can also prevent indium and aluminum superconducting circuit layers from directly contacting each other and forming an alloy, which would damage the superconducting circuit structure.

[0054] In summary, the solution presented in this application, by setting a niobium-based under-bump metal layer between the superconducting circuit layer and the solder joint in the qubit assembly for flip-chip superconducting quantum chips, leverages the fact that niobium is a superconducting material and is easier to peel off than gold, thus having less impact on the cleanliness of the superconducting circuit layer. Furthermore, the oxide layer on the niobium surface is easier to remove than oxide layers on other superconducting materials, resulting in better superconducting contact with the solder joint. Therefore, using niobium as the under-bump metal layer can significantly improve the superconducting performance between two planar superconducting quantum chips in a flip-chip superconducting quantum chip, thereby improving the performance of the flip-chip superconducting quantum chip.

[0055] In the above embodiments of this application, superconducting niobium is used as a UBM layer, which can be applied to flip-chip superconducting quantum chips (such as 2-qubit flip-chip superconducting quantum chips or 49-qubit flip-chip superconducting quantum chips, etc.) to realize superconducting circuit connections between multilayer aluminum superconducting circuit layers. The niobium film as a UBM layer can prevent the formation of alloys between the aluminum circuit and the indium solder joint, thereby affecting the superconducting connection. At the same time, its excellent etching rate and convenient preparation method also greatly improve the efficiency and performance of multilayer aluminum superconducting circuit connections.

[0056] Subsequent embodiments of this application provide a fabrication scheme for a quantum bit component. Please refer to... Figure 2 This illustrates a flowchart of a method for fabricating a quantum bit component according to an exemplary embodiment of this application. Figure 2 As shown, the method may include the following steps:

[0057] Step 201: Fabricate a superconducting circuit layer on the substrate.

[0058] The substrate can be made of sapphire or high-resistivity silicon, and the superconducting circuit layer can be made of aluminum.

[0059] Step 202: Prepare a bump undermetal layer on the upper surface of the superconducting circuit layer; the bump undermetal layer forms a superconducting connection with the superconducting circuit layer; the material of the bump undermetal layer is niobium.

[0060] Step 203: Prepare solder joints on the upper surface of the under-bump metal layer to obtain a quantum bit assembly for flip-chip bonding of a superconducting quantum chip; the solder joints form a superconducting connection with the under-bump metal layer.

[0061] In the embodiments of this application, the solder joint can be a cylindrical structure made of indium metal.

[0062] In the embodiments of this application, the quantum bit component includes, from bottom to top, a substrate, a superconducting circuit layer, a bump under-metal layer, and solder joints. Accordingly, when fabricating the quantum bit component, it is also fabricated layer by layer in the order of superconducting circuit layer, bump under-metal layer, and solder joints.

[0063] In summary, the scheme shown in the embodiments of this application involves fabricating a superconducting circuit layer, a niobium bump under-metal layer, and solder joints layer by layer on a substrate. Since niobium is a superconducting material, and it is easier to peel off than gold, it has less impact on the cleanliness of the superconducting circuit layer. Furthermore, the oxide layer on the surface of niobium is easier to remove than the oxide layer on the surface of other superconducting materials, thus forming a better superconducting contact with the solder joints. Therefore, by using niobium as the bump under-metal layer, the superconducting performance between two planar superconducting quantum chips in a flip-chip superconducting quantum chip can be greatly improved, thereby improving the performance of the flip-chip superconducting quantum chip.

[0064] Please refer to Figure 3 This diagram illustrates the fabrication framework of the quantum bit component involved in this application. Figure 3 As shown in the above embodiments of this application, the main preparation steps for preparing indium solder joints by using superconducting niobium as the under-bump metal layer of a flip-chip superconducting quantum chip can be divided into:

[0065] The process includes: photolithography to define the UBM layer pattern (S31), hard film process to improve the photoresist support for niobium film stress (S32), ion beam etching to remove the oxide layer on the surface of the aluminum film (S33), growth of high-quality niobium film (S34), niobium film stripping (S35), photolithography to define the solder joint layer pattern (S36), ion beam etching to remove the oxide layer on the surface of the niobium film (S37), and solder joint preparation (S38).

[0066] In combination with the above Figure 3 Please refer to Figure 4 This illustrates a flowchart of a method for fabricating a quantum bit component according to an exemplary embodiment of this application. Figure 4 As shown, the method may include the following steps:

[0067] Step 401: Fabricate a superconducting circuit layer on the substrate.

[0068] In the embodiments of this application, a superconducting circuit layer can be prepared on a substrate by steps of evaporating superconducting metal, photolithography to define the circuit layer, and solution etching.

[0069] The superconducting circuit layer mentioned above is made of aluminum.

[0070] For example, firstly, a layer of superconducting material (such as aluminum) is deposited on a substrate (e.g., the substrate material can be sapphire or high-resistivity silicon). Then, a first photoresist is spin-coated on the superconducting material. The pattern of the superconducting circuit layer is defined on the surface of the superconducting material by photolithography. At this time, the substrate contains a layer of superconducting material and the first photoresist layer on the superconducting material that has not been removed by photolithography. Then, the defined circuit pattern is etched using an acidic solution. Finally, the residual first photoresist spin-coated layer is removed by a resist remover and deionized water, and the superconducting circuit layer is retained on the substrate.

[0071] The first photoresist mentioned above is a positive photoresist.

[0072] The above-mentioned photolithography methods can be ultraviolet exposure or laser direct writing.

[0073] The developer mentioned above can be tetramethylammonium hydroxide (TMAH), or a TMAH diluent, etc.

[0074] For example, in the embodiments of this application, AZ6112 photoresist can be spin-coated onto the sample (i.e., the substrate sample with superconducting material deposited on it) and baked at a certain temperature (e.g., 100°C) for a period of time; then the sample is placed in a laser direct writing device (i.e., the photolithography machine mentioned above) and the pattern (i.e., the pattern corresponding to the superconducting circuit layer mentioned above) is written with specific parameters; then the sample is placed in a 2.38% TMAH solution for development for a period of time, and then placed in deionized water for fixing.

[0075] Development is the crucial step in creating patterns in the photoresist on the substrate surface. After exposure, the soluble areas of the photoresist are dissolved by chemical developers, leaving visible island or window patterns on the substrate surface. For positive photoresist, during development, the photoresist in the unexposed areas does not undergo a chemical reaction during exposure, and therefore there is no acid-base neutralization. Thus, the unexposed photoresist is retained, while the exposed positive photoresist gradually dissolves. For negative photoresist, the unexposed negative photoresist first forms a gel in the developer and then decomposes. The photoresist pattern left after development will be used as a mask in subsequent etching and ion implantation processes.

[0076] Step 402: Prepare a photoresist covering the superconducting circuit layer on the substrate.

[0077] In the embodiments of this application, after the superconducting circuit layer is prepared on the substrate, a second photoresist layer can be spin-coated on the substrate, which covers the superconducting circuit layer.

[0078] The second photoresist and the first photoresist can be photoresists of the same material or photoresists of different materials.

[0079] Step 403: Remove the photoresist in the first target area on the upper surface of the superconducting circuit layer by photolithography and development; the first target area is the area where the metal layer under the bump is located.

[0080] In this step, after spin-coating the second photoresist covering the superconducting circuit layer, the second photoresist in the area on the upper surface of the superconducting circuit layer where the bump under metal layer needs to be prepared (i.e., the first target area mentioned above) can be removed by photolithography and development, while the second photoresist in the remaining area is retained.

[0081] Step 404: After removing the photoresist from the first target area, bake the remaining photoresist on the substrate for a first duration.

[0082] In one possible implementation, the duration of the first duration is between 1 and 2 minutes.

[0083] Step 405: Perform ion beam etching for a second duration on the first target area and the remaining photoresist on the substrate.

[0084] Please refer to Figure 5 This illustrates a schematic diagram of the preparation of a metallic niobium film according to an embodiment of this application. Figure 5 As shown in the application embodiment, the niobium film, as the UBM layer, is obtained through a stripping process. The basic principle is to use photolithography to expose the UBM layer growth area, and after the coating is completed, use a photoresist remover (such as Remover PG) to clean away the photoresist, thereby retaining only the grown UBM layer niobium film.

[0085] In actual coating processes, due to the significant stress on the niobium film surface, without proper sample surface treatment, this stress can lead to film cracking. This can result in incomplete removal of the photoresist and its surface niobium film during subsequent photoresist stripping, affecting the cleanliness of the superconducting circuit and reducing the performance of the superconducting quantum chip. Please refer to [reference needed]. Figure 6 It shows a comparison image of a niobium film cracked under stress and a high-quality niobium film after process optimization, according to embodiments of this application. Figure 6 The niobium film on the left side of the image is cracked, making it impossible to completely peel off the photoresist and its surface niobium film during subsequent stripping. In contrast, the niobium film on the right side is not cracked, allowing for cleaner stripping of the photoresist and its surface niobium film during subsequent stripping, resulting in a high-quality UBM layer.

[0086] To address the aforementioned issues, the solution described in this application embodiment involves treating the second photoresist after photolithography and development before fabricating the niobium film, thereby enhancing the second photoresist's support for the stress on the niobium film. This treatment includes a hard film process (i.e., baking on a hot plate after development) and an ion beam etching process.

[0087] Normally, the photoresist can be baked before photolithography, but not after photolithography development. However, in the scheme shown in the embodiments of this application, an additional baking operation can be performed on the photoresist after photolithography development to improve the photoresist's support for the stress of the niobium film.

[0088] Furthermore, the solution shown in the embodiments of this application can also perform an ion beam etching on the photoresist after photolithography and development, thereby forming etching marks on the surface of the photoresist, increasing the contact area between the photoresist and the niobium film layer, and thus improving the stress support effect of the photoresist on the niobium film.

[0089] Please refer to Table 1 below, which shows the timeline of niobium film cracking under stress in the embodiments of this application, using AZ6112 photoresist as an example.

[0090] Table 1

[0091]

[0092] Comparing experimental groups 3 and 4, it can be seen that the ion beam etching process can increase the support of the photoresist (AZ6112) for the stress of the niobium film. Comparing experimental groups 4 and 5, it can be seen that the hard film process can further improve the support of the photoresist AZ6112 for the stress of the niobium film based on the ion beam etching process. Comparing experimental groups 5 and 6, it can be seen that a hard film time of about 1 minute can improve the support of the photoresist AZ6112 for the stress of the niobium film, thereby meeting the growth requirements of the UBM layer.

[0093] Based on the experimental data shown in Table 1 above, the solution shown in this application embodiment can set the first baking time of the remaining photoresist on the substrate to about 1 minute. For example, the first baking time can be set to 1 minute or 2 minutes, or the first baking time can be set to any duration between 1 minute and 2 minutes.

[0094] In this embodiment, the step of ion beam etching of the first target area on the upper surface of the superconducting circuit layer can not only improve the support effect of the remaining photoresist on the stress of the niobium film, but also remove the oxide layer of the first target area on the upper surface of the superconducting circuit layer.

[0095] Aluminum, as a superconducting metallic material, has a critical transition temperature of 1.196K. It readily forms Josephson junctions with aluminum / alumina / aluminum structures, and therefore aluminum is widely used in the fabrication of superconducting circuits.

[0096] When aluminum is exposed to air, a dense oxide layer forms on its surface. This oxide layer has an insulating effect and can affect superconducting performance. Therefore, in this embodiment, before fabricating the under-bump metal layer on top of the superconducting circuit layer, an ion beam etching process can be performed on the first target area on the upper surface of the superconducting circuit layer to remove the oxide layer in the first target area.

[0097] In one possible implementation, the second duration of ion beam etching ranges from 120 seconds to 180 seconds.

[0098] In this embodiment, a set of film strip resistors prepared with aluminum film are used. By measuring the film strip resistance after different etching times, the oxide layer thickness and the etching time required to etch away the oxide layer are calculated. The principle of this method is: resistance value after etching / resistance value before etching = aluminum film thickness before etching / aluminum film thickness after etching ≈ total thickness of aluminum and aluminum oxide before etching / total thickness of aluminum and aluminum oxide after etching.

[0099] Please refer to Figure 7 This illustrates a schematic diagram of the etching profiles involved in an embodiment of this application. Figure 7 As shown, for ion sources with the same etching conditions, the etching rates for alumina and aluminum are different. Please refer to [reference needed]. Figure 7 Etching curves with different slopes are shown in the figures. Etching curve 71 is the curve of etching thickness and etching time when the ion source etches aluminum under certain etching conditions, and its corresponding relationship is y = 0.0617x, where y is the etching thickness and x is the etching time. Etching curve 72 is the curve of etching thickness and etching time when the ion source etches aluminum under the same etching conditions, and its corresponding relationship is y = 0.1583x - 9.765. The time point at which etching curves 71 and 72 intersect (101.087s) can be regarded as the time when the oxide layer is just etched away. Based on the above experimental results, a time of about 150s is taken as the etching time (i.e., the second time mentioned above) to ensure superconducting contact between aluminum and niobium. For example, the solution shown in the embodiments of this application can set the second time for ion beam etching of the first target area and the remaining photoresist on the substrate to be between 2 minutes and 3 minutes. For example, the second time can be 120s, 150s or 180s, etc., or the second time can be set to any other time between 2 minutes and 3 minutes.

[0100] After removing the oxide layer in the first target region on the upper surface of the superconducting circuit layer, a metal layer under the bump can be prepared in the first target region on the upper surface of the superconducting circuit layer. Please refer to the following steps for this process.

[0101] Step 406: Prepare a niobium film on the photoresist and the first target area.

[0102] In one possible implementation, a niobium film layer is fabricated on the photoresist and the first target region, including:

[0103] A niobium film was prepared on photoresist and a first target area by magnetron sputtering.

[0104] In one possible implementation, the gas pressure range for magnetron sputtering is 8 × 10⁻⁶. -4 Up to 2×10 -3 torr.

[0105] In one possible implementation, the distance between the niobium target and the substrate in magnetron sputtering ranges from 8 cm to 12 cm.

[0106] In one possible implementation, the power of magnetron sputtering ranges from 150 watts to 220 watts.

[0107] In one possible implementation, the gas flow rate of magnetron sputtering ranges from 4 standard milliliters per minute to 6 standard milliliters per minute.

[0108] In this embodiment, the niobium film can be grown by magnetron sputtering. The basic principle is that electrons collide with argon molecules under the combined action of an electric and magnetic field, generating argon cations. These cations bombard the surface of the niobium target, causing target atoms to evaporate onto the substrate surface. During the magnetron sputtering deposition process, the gas flow rate, working pressure, target-substrate distance, and deposition power are all adjustable parameters.

[0109] In the embodiments of this application, the above-mentioned gas flow rate, working gas pressure, target-substrate distance, and coating power can be selected based on the following experimental results.

[0110] 1) The working gas pressure was determined through the first set of experiments. The experimental design was as follows: the gas flow rate was kept constant at 5 standard cubic centimeters per minute (sccm), the target-substrate distance was kept constant at 10cm, and the coating power was kept constant at 150W. The working gas pressure was divided into 10... -3 torr, 5×10 -3 torr, 10 -2 torr. After coating, observe its morphology under a scanning electron microscope. Please refer to [reference needed]. Figure 8The image shows electron micrographs of the niobium film surface under different air pressures according to the embodiments of this application.

[0111] exist Figure 8 In the middle, from left to right, are 10 -3 torr, 5×10 -3 torr, 10 -2 Electron microscopy images of the niobium film surface under the operating pressure of the torr. As can be seen from the image above, when the operating pressure is 10... -3 When the torr is applied, the surface of the niobium film is an ordered elongated granular structure; when the working pressure is 5×10 -3 During the torr process, the surface of the niobium film exhibits a coexistence of elongated and irregular grains; when the working gas pressure is 10... -2 During torr, the surface of the niobium film completely transforms into an irregular granular state. Therefore, in the embodiments of this application, 10 -3 A pressure of approximately 10 torr is used as the optimized working pressure for niobium film coating. For example, 10 torr can be selected. -3 The working pressure can be set to the torr pressure, or 8×10 can be selected. -4 torr or 2×10 -3 Torr can be used as the working pressure, or you can choose 8×10. -4 torr to 2×10 -3 Any other air pressure between torr is used as the above working air pressure.

[0112] 2) The working distance between the target and the substrate was determined through the second set of experiments. The experimental design was as follows: the gas flow rate was kept constant at 5 sccm, the coating power was kept constant at 150 W, and the working gas pressure was kept constant at 10. -3 With torr unchanged, the working distance between the target and the substrate was adjusted to 8 cm and 10 cm. After coating, the morphology was observed under a scanning electron microscope. Please refer to [reference needed]. Figure 9 The image shows electron micrographs of the niobium film surface at different distances in the embodiments of this application.

[0113] exist Figure 9 In the middle, from left to right, are electron micrographs of the niobium film surface at working distances of 10 cm and 8 cm, respectively. Figure 9 As can be seen, when the working distance is 10cm, the grain size on the niobium film surface is smaller and more uniform, while when the working distance is 8cm, the grain size on the niobium film surface becomes larger. Therefore, in the embodiments of this application, a distance of approximately 10cm between the target and the substrate can be selected as the optimized working distance. For example, a distance of 10cm, 8cm, or 12cm can be selected as the working distance, or any other distance between 8cm and 12cm can be selected as the aforementioned working distance.

[0114] 3) The coating power was determined through the third set of experiments. The experimental design was as follows: the gas flow rate was kept constant at 5 sccm, and the working gas pressure was kept constant at 10. -3 With torr constant and the working distance between the target and substrate kept constant at 10 cm, the coating power was set to 100 W, 150 W, and 200 W. The morphology was observed under a scanning electron microscope after coating. Please refer to [reference needed]. Figure 10 The image shows electron microscope (EM) images of the niobium film surface under different coating powers according to the embodiments of this application.

[0115] exist Figure 10 In the middle, from left to right, are electron microscope images of the niobium film surface at coating powers of 100W, 150W, and 200W, respectively.

[0116] from Figure 10 From the scanning electron microscope, there was no significant difference in the surface of the niobium film under several different coating powers. To further confirm the optimized coating power, the superconducting transition temperature of the niobium film samples under the above three different coating powers was measured. Please refer to [reference needed]. Figure 11 It shows a schematic diagram of the superconducting transition temperature of niobium film samples under different coating powers.

[0117] Depend on Figure 11 It can be seen that at a coating power of 100W, the superconducting transition temperature of the niobium film is 6.9K, while at coating powers of 150W and 200W, the superconducting transition temperature of the niobium film is around 8K. Therefore, the coating power can be determined by combining 150W and 200W. For example, considering the coating efficiency, a power of around 200W can be selected as the coating power. For example, the coating power can be directly set to 200W, or 150W or 220W can be selected as the coating power, or any other power between 150W and 220W can be selected as the coating power mentioned above.

[0118] Step 407: Remove the photoresist and the niobium metal film layer on top of the photoresist to obtain the bump under metal layer located on the upper surface of the superconducting circuit layer.

[0119] In this embodiment, after removing the second photoresist and the niobium film on top of the second photoresist, a metal niobium material bump under metal layer can be left on top of the superconducting circuit layer.

[0120] The process of removing the second photoresist and the niobium film on top of the second photoresist can be achieved by cleaning the sample with the evaporated niobium film using a photoresist remover and deionized water.

[0121] After the under-bump metal layer is fabricated on the upper layer of the superconducting circuit layer, the under-bump metal layer can be ion-beam etched to remove the oxide layer on the upper surface of the under-bump metal layer. This process is described in subsequent steps 408 to 410.

[0122] Step 408: Prepare a photoresist covering the superconducting circuit layer and the under-bump metal layer on the substrate.

[0123] In the embodiments of this application, after the superconducting circuit layer and the under-bump metal layer are prepared on the substrate, a third photoresist layer can be spin-coated on the substrate, which covers the aforementioned under-bump metal layer.

[0124] The third photoresist and the first / second photoresist mentioned above can be photoresists of the same material or photoresists of different materials.

[0125] Step 409: Remove the photoresist in the second target area on the upper surface of the metal layer under the bump by photolithography development; the second target area is the area where the solder joint is located.

[0126] In this step, after spin-coating the third photoresist covering the metal layer under the bump, the third photoresist in the area where solder joints need to be formed (i.e., the second target area mentioned above) on the upper surface of the metal layer under the bump can be removed by photolithography and development, while the third photoresist in the remaining area is retained.

[0127] Step 410: Ion beam etching is performed on the second target region on the upper surface of the metal layer under the bump to remove the oxide layer of the second target region on the upper surface of the metal layer under the bump.

[0128] In one possible implementation, the depth of ion beam etching ranges from 15 nanometers to 18 nanometers.

[0129] In flip-chip superconducting quantum chips, the niobium film, serving as the UBM layer, undergoes numerous processing steps before an oxide layer removal process is performed, allowing for superconducting contact with the indium solder joints. To completely remove the oxide layer at the solder joint locations on the niobium film's surface and ensure a good superconducting contact with the indium solder joints, studying the oxidation characteristics of the niobium film is a crucial step in using it as the UBM layer in flip-chip superconducting quantum chips. In this application, the niobium film resistance was investigated at deposition power of 100W, 150W, and 200W, and its characteristic curves for natural oxidation in air were tested. Please refer to... Figure 12 The diagram shows the natural oxidation characteristic curves of the niobium film involved in the embodiments of this application.

[0130] like Figure 12 As shown, this includes a curve showing the relationship between oxide layer thickness and number of days, derived from the above. Figure 12As can be seen, the oxidation curve of the niobium film becomes flatter over time. Under three different power conditions, the thickness of the oxide layer on the surface of the niobium film is about 10 nm after 30 days. In order to ensure that the oxide layer thickness of the niobium film is completely removed, in the scheme shown in the embodiment of this application, the etching depth of the metal layer under the bump can be set to above 15 nm. That is to say, in the ion beam etching process, a film layer of more than 15 nm can be removed.

[0131] For example, in the embodiments of this application, the depth of ion beam etching of the metal layer under the bump can be set to 15nm, 18nm, or any depth between 15nm and 18nm.

[0132] Step 411: Prepare solder joints on the upper surface of the under-bump metal layer to obtain a qubit component for flip-chip bonding of a superconducting quantum chip; the solder joints form a superconducting connection with the under-bump metal layer.

[0133] In this embodiment of the application, after removing the oxide layer in the second target region on the upper surface of the under-bump metal layer, an indium solder joint can be prepared in the second target region on the upper surface of the under-bump metal layer.

[0134] In one possible implementation, the solder joints can be prepared by photolithography followed by vapor deposition. In this case, the preparation process of the solder joints is similar to that of the metal layer under the bump, and will not be described in detail here.

[0135] In summary, the scheme shown in the embodiments of this application involves fabricating a superconducting circuit layer, a niobium bump under-metal layer, and solder joints layer by layer on a substrate. Since niobium is a superconducting material, and it is easier to peel off than gold, it has less impact on the cleanliness of the superconducting circuit layer. Furthermore, the oxide layer on the surface of niobium is easier to remove than the oxide layer on the surface of other superconducting materials, thus forming a better superconducting contact with the solder joints. Therefore, by using niobium as the bump under-metal layer, the superconducting performance between two planar superconducting quantum chips in a flip-chip superconducting quantum chip can be greatly improved, thereby improving the performance of the flip-chip superconducting quantum chip.

[0136] In one exemplary embodiment of this application, a flip-chip superconducting quantum chip is also provided, which comprises as described above. Figure 1 The shown is a quantum bit component. This quantum bit component can be used... Figure 2 or Figure 4 The preparation is carried out according to the method shown.

[0137] In one exemplary embodiment of this application, a computer device is also provided, the computer device comprising a flip-chip superconducting quantum chip, the flip-chip superconducting quantum chip comprising... Figure 1The shown is a quantum bit component. This quantum bit component can be used... Figure 2 or Figure 4 The preparation is carried out according to the method shown.

[0138] Please refer to Figure 13 This illustration shows a schematic diagram of an application scenario for a solution provided in one embodiment of this application. For example... Figure 13 As shown, the application scenario can be a superconducting quantum computing platform, which includes: a quantum bit chip 131, a dilution refrigerator 132, a control device 133, and a computer 134.

[0139] The quantum bit chip 131 is a circuit operating on physical quantum bits, and it can be implemented as a quantum computing device. The dilution cooler 132 is used to provide an absolute zero environment for the superconducting quantum chip. The aforementioned quantum bit chip 131 can be the flip-chip superconducting quantum chip described above.

[0140] Control device 133 controls the quantum bit chip 131, and computer 134 controls control device 133. For example, a written quantum program is compiled into instructions by software in computer 134 and sent to control device 133 (such as an electronic / microwave control system). Control device 133 converts these instructions into electronic / microwave control signals and inputs them to dilution refrigerator 132 to control the superconducting quantum bits at a temperature below 10 mK. The reading process is the reverse; the read waveform is sent to quantum bit chip 131.

[0141] Figure 14 A schematic diagram of a production line equipment illustrated in an exemplary embodiment of this application is shown, such as... Figure 14 As shown, the production line equipment includes: an ion beam etching machine 1401, a photolithography machine 1402, and a vapor deposition machine 1403. The ion beam etching machine 1401, the photolithography machine 1402, and the vapor deposition machine 1403 are used to collaboratively prepare the aforementioned... Figure 1 The quantum bit component shown.

[0142] Optionally, the ion beam etching machine 1401, the photolithography machine 1402, and the evaporation machine 1403 can be used to collaboratively perform the following steps:

[0143] Fabrication of a superconducting circuit layer on a substrate;

[0144] A bump-type undermetal layer is prepared on the upper surface of the superconducting circuit layer; the bump-type undermetal layer forms a superconducting connection with the superconducting circuit layer; the material of the bump-type undermetal layer is niobium.

[0145] Solder joints are prepared on the upper surface of the metal layer under the bump to obtain a quantum bit assembly for flip-chip bonding of a superconducting quantum chip; the solder joints form a superconducting connection with the metal layer under the bump.

[0146] In one possible implementation, an under-bump metal layer is prepared on the upper surface of the superconducting circuit layer, thereby preparing indium solder joints, including:

[0147] A photoresist covering the superconducting circuit layer is prepared on the substrate;

[0148] The photoresist in the first target region on the upper surface of the superconducting circuit layer is removed by photolithography; the first target region is the area where the metal layer under the bump is located.

[0149] A niobium film is prepared on the photoresist and the first target region;

[0150] Remove the photoresist and the niobium metal film layer on top of the photoresist to obtain the under-bump metal layer located on the upper surface of the superconducting circuit layer.

[0151] In one possible implementation, before fabricating a niobium film layer on the photoresist and the first target region, the method further includes:

[0152] After removing the photoresist from the first target area, the remaining photoresist on the substrate is baked for a first duration.

[0153] In one possible implementation, the duration of the first duration is between 1 minute and 2 minutes.

[0154] In one possible implementation, before fabricating a niobium film layer on the photoresist and the first target region, the method further includes:

[0155] After removing the photoresist from the first target area, the remaining photoresist on the first target area and the substrate is subjected to ion beam etching for a second duration to remove the oxide layer in the first target area and improve the support of the remaining photoresist for the stress of the niobium film.

[0156] In one possible implementation, the second duration ranges from 2 to 3 minutes.

[0157] In one possible implementation, a niobium film layer is fabricated on the photoresist and the first target region, including:

[0158] A niobium film was prepared on the photoresist and the first target area by magnetron sputtering.

[0159] In one possible implementation, the gas pressure range for magnetron sputtering is 8 × 10⁻⁶. -4 Up to 2×10 -3 Entrust.

[0160] In one possible implementation, the distance between the magnetron sputtered niobium target and the substrate ranges from 8 cm to 12 cm.

[0161] In one possible implementation, the power of magnetron sputtering ranges from 150 watts to 220 watts.

[0162] In one possible implementation, the gas flow rate of magnetron sputtering ranges from 4 standard milliliters per minute to 6 standard milliliters per minute.

[0163] In one possible implementation, before preparing the solder joint on the upper surface of the metal layer under the bump, the method further includes:

[0164] The metal layer under the bump is etched with an ion beam to remove the oxide layer on the upper surface of the metal layer under the bump.

[0165] The process of ion beam etching of the under-bump metal layer can include: preparing photoresist covering the superconducting circuit layer and the under-bump metal layer on a substrate; removing the photoresist of the second target area on the upper surface of the under-bump metal layer by photolithography; the second target area is the area where the solder joint is located; and performing ion beam etching on the second target area on the upper surface of the under-bump metal layer to remove the oxide layer of the second target area on the upper surface of the under-bump metal layer.

[0166] In one possible implementation, the depth of the ion beam etching ranges from 15 nanometers to 18 nanometers.

[0167] The processes for fabricating qubit components using the aforementioned ion beam etching machine 1401, photolithography machine 1402, and evaporation machine 1403 can be referenced. Figure 2 or Figure 4 The descriptions in the illustrated embodiments will not be repeated here.

[0168] Optionally, the production line equipment also includes a processor that can be electrically connected to the ion beam etching machine 1401, the lithography machine 1402, and the vapor deposition machine 1403, respectively, to control the ion beam etching machine 1401, the lithography machine 1402, and the vapor deposition machine 1403, etc.

[0169] Optionally, the production line equipment also includes a power supply to provide power to electrical equipment such as the processor, ion beam etching machine 1401, lithography machine 1402, and vapor deposition machine 1403.

[0170] Optionally, the machines can be spatially connected via conveyor belts, or the movement of the prepared material between the machines can be accomplished using robotic arms.

[0171] Optionally, the production line equipment also includes a memory that can be used to store at least one computer instruction, which the processor executes to cause the production line equipment to perform the above-described quantum bit component fabrication method.

[0172] In one exemplary embodiment, a computer-readable storage medium is also provided, which stores at least one computer instruction that is executed by a processor in a production line device to cause the production line device to perform the above-described method for fabricating a quantum bit component.

[0173] In an exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. The processor of the production line equipment reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the production line equipment to perform the above-described method for fabricating quantum bit components.

[0174] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0175] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for fabricating a quantum bit component, characterized in that, The method includes: A superconducting circuit layer is fabricated on a substrate; the material of the superconducting circuit layer is aluminum. A photoresist covering the superconducting circuit layer is prepared on the substrate; The photoresist in the first target area on the upper surface of the superconducting circuit layer is removed by photolithography; the first target area is the region where the metal layer under the bump is located. After removing the photoresist from the first target area, the remaining photoresist on the substrate is baked for a first duration using a hot plate, and then the first target area and the remaining photoresist on the substrate are etched by an ion beam for a second duration. The first duration is between 1 minute and 2 minutes; the second duration is between 2 minutes and 3 minutes. The second duration is set based on the etching time for etching away the oxide layer on the surface of the aluminum material, and the etching time is calculated by measuring the film resistance of the aluminum material after different etching times. A niobium film is prepared on the photoresist and the first target region; The photoresist and the niobium metal film layer on top of the photoresist are removed to obtain the under-bump metal layer located on the upper surface of the superconducting circuit layer; the under-bump metal layer forms a superconducting connection with the superconducting circuit layer; Solder joints are prepared on the upper surface of the metal layer under the bump to obtain a quantum bit assembly for flip-chip bonding of a superconducting quantum chip; the solder joints form a superconducting connection with the metal layer under the bump.

2. The method according to claim 1, characterized in that, Fabricating a niobium film layer on the photoresist and the first target region includes: A niobium film was prepared on the photoresist and the first target area by magnetron sputtering.

3. The method according to claim 2, characterized in that, The gas pressure range for magnetron sputtering is 8 × 10⁻⁶. -4 Up to 2×10 -3 Entrust.

4. The method according to claim 2, characterized in that, The distance between the niobium target and the substrate during magnetron sputtering ranges from 8 cm to 12 cm.

5. The method according to claim 2, characterized in that, The power range of magnetron sputtering is from 150 watts to 220 watts.

6. The method according to claim 2, characterized in that, The gas flow rate for magnetron sputtering ranges from 4 standard milliliters per minute to 6 standard milliliters per minute.

7. The method according to claim 1, characterized in that, Before preparing solder joints on the upper surface of the metal layer under the bump, the process further includes: The metal layer under the bump is etched with an ion beam to remove the oxide layer on the upper surface of the metal layer under the bump.

8. The method according to claim 7, characterized in that, The depth of the ion beam etching ranges from 15 nanometers to 18 nanometers.

9. A production line equipment, characterized in that, The production line equipment includes: a lithography machine, a vapor deposition machine, and an ion beam etching machine; the lithography machine, the vapor deposition machine, and the ion beam etching machine are used to cooperate in performing the quantum bit component fabrication method as described in any one of claims 1 to 8.

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