A method for monitoring a secure operating environment in a SoC system

Abstract

The application discloses a kind of security operation environment monitoring implementation methods in SoC system, belong to security chip design technical field, the SoC system includes processor and the security monitoring module being connected with processor, security monitoring module is built-in multiple sensors, method includes: step 1: after SoC system power on or reset, security monitoring module enters initialization stage, in initialization stage, security monitoring module carries out sensor configuration and peripheral environment detection, processor is configured as reference according to the sensor data obtained in this stage, sensor threshold value;Step 2: after processor configuration is completed, security monitoring module enters monitoring stage, in monitoring stage, each sensor independently detects.The present application can make up the deficiency of existing chip protection means in flexibility, security, adaptability and the like, make chip security detection means diversification, and can adapt to various complex environments, compatible system security and use flexibility.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of secure chip design, in particular to a secure running environment monitoring implementation method in a SoC system. BACKGROUND

[0002] With the continuous rapid development of information technology, SoC (System on Chip) chips play an important role in various industries, and secure SoC chips gradually show their importance because of their unique role in the field of information security. However, various attack techniques against secure chips have emerged, such as fault injection attacks, physical attacks, etc.

[0003] Fault injection attacks cause circuit abnormalities by using faults (voltage, clock, temperature, etc.), and analyze the sensitive information inside the chip according to the abnormal information; or directly use the abnormality of the circuit to change the program running. The traditional way to prevent fault injection attacks is to embed sensors inside the SoC chip to play a warning role.

[0004] Physical attacks generally remove the chip package, make electrical contact with the internal circuit, and combine other attack means to obtain the sensitive information stored in the chip. Generally, active shielding layers (Active shield) can be added to the chip to issue a warning when the chip is damaged.

[0005] The above-mentioned protection means against secure SoC chip attacks are relatively single, and it is difficult to balance the flexibility of use and system security. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a secure running environment monitoring implementation method in a SoC system which combines multiple detection means, has flexible configuration and high security.

[0007] To solve the above technical problems, the present application provides the following technical solutions:

[0008] A secure running environment monitoring implementation method in a SoC system, the SoC system comprising a processor and a security monitoring module connected to the processor, the security monitoring module being built-in with at least two of a temperature sensor, a voltage sensor, a frequency sensor, an electromagnetic sensor and an active defense layer, the method comprising:

[0009] Step 1: After the SoC system is powered on or reset, the security monitoring module enters an initialization stage, in which the security monitoring module performs sensor configuration and peripheral environment detection, and the processor configures sensor threshold values based on the sensor data obtained in this stage as a reference;

[0010] Step 2: After the processor is configured, the security monitoring module enters a monitoring stage, and in the monitoring stage, each sensor independently performs detection.

[0011] The present application has the following beneficial effects:

[0012] The SoC system security running environment monitoring implementation method has the following beneficial effects: the security monitoring module in the chip is built-in with multiple sensors for attack behavior detection, such as temperature sensors, voltage sensors, frequency sensors, electromagnetic sensors, and active defense layers, attack prevention capability is improved through multi-dimensional detection of multiple sensors, and the system can be protected in multiple dimensions; an initialization stage is established before the monitoring stage, and the method can be applied to various external environments. The present application can make up for the deficiencies of existing chip protection methods in flexibility, security, adaptability, etc., diversify chip security detection methods, and adapt to various complex environments, and compatible system security and use flexibility. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 The present application has the following beneficial effects:

[0014] Figure 2 The present application has the following beneficial effects: DETAILED DESCRIPTION

[0015] In order to make the technical problems, technical solutions and advantages of the present application clearer, specific embodiments will be described in detail below with reference to the drawings.

[0016] The present application provides a SoC system security running environment monitoring implementation method, the SoC system comprising a processor and a security monitoring module connected to the processor, the security monitoring module being built-in with at least two of temperature sensors, voltage sensors, frequency sensors, electromagnetic sensors and active defense layers (Sensor1, Sensor2…, SensorN, as shown in the figure), the method comprising: Figure 1 Figures 1-2 The present application has the following beneficial effects:

[0017] Step 1: After the SoC system is powered on or reset, the security monitoring module enters an initialization stage, in which the security monitoring module performs sensor configuration and peripheral environment detection, and the processor configures sensor threshold values according to sensor data obtained in this stage as a reference;

[0018] ​In this step, after the SoC system is powered on or reset, the security monitoring module first enters an initialization (Init) stage, no sensitive data is generated in this stage, and the SoC system in this stage can be considered to have no attack value. The security monitoring module in this stage performs sensor configuration and peripheral environment detection, and the SoC system processor configures multiple thresholds according to the sensor data obtained in this stage (the sensor data can be sent to the processor by the security monitoring module).

[0019] Step 2: After the processor configuration is completed, the security monitoring module enters a monitoring stage, and each sensor independently performs detection in the monitoring stage.

[0020] The security running environment monitoring implementation method of the SoC system of the application has multiple sensors in the security monitoring module in the chip for attack behavior detection, such as temperature sensors, voltage sensors, frequency sensors, electromagnetic sensors, and active defense layers, which can improve the attack prevention capability through multi-dimensional detection of multiple sensors, and can provide multi-dimensional protection for the system; by establishing an initialization stage before the monitoring stage, it can be applied to various external environments. The application can make up for the deficiencies of existing chip protection methods in flexibility, security, adaptability, etc., diversify chip security detection methods, and adapt to various complex environments, and compatible system security and use flexibility.

[0021] Further, the step 1 can include:

[0022] In the initialization stage, if an abnormal situation occurs, the processor directly enters a fatal (Fatal) state by configuring the register of the security monitoring module;

[0023] And / or, in the initialization stage, the SoC system generates a random number, which is used as a key for the processor to configure the security monitoring module.

[0024] In this way, if an obvious abnormal situation such as security firmware verification failure occurs in the Init stage, the SoC processor can directly enter the Fatal state by configuring the register of the security monitoring module. Moreover, the application proposes to use a random number as a key for the processor to configure the security monitoring module and subsequent confirmation in the Init stage, which is highly secure.

[0025] Further, the step 1 can also include:

[0026] In the initialization stage, the processor configures each sampling interval time Dn of each sensor, the sampling number Wn in the sampling window time, the clearable error count threshold T1n, the non-clearable error count threshold T2n, the reasonable range of the sampling value REFn, and the processor confirmation timeout time Tout by configuring the register of the security monitoring module.

[0027] Dn represents the sampling interval time of sensor n; Wn represents the number of times of sampling the sensor value of sensor n in a sampling window time Ln, wherein the sampling window time Ln = Wn*Dn, and Wn can be an integer from 1 to a positive integer; the number Pn of times of counting the sensor value not in the REFn is counted in a complete sampling window time, and if Pn exceeds T1n, a clearable error is triggered, and if Pn exceeds T2n, an uncleared error is triggered. After the sampling window time Ln ends, Pn is cleared, and another sampling window is started.

[0028] As shown in FIG. 2, in step 2, in the monitoring phase, the initial state of each sensor is set as the monitoring (Monitor) state; and step 2 can include: Figures 1-2

[0029] Step 21: for each sensor, a sampling window is started, and the number Pn of times of counting the sensor value not in the sampling value reasonable range REFn is set to zero, and the current sampling number Cn is set to zero;

[0030] Step 22: waiting for Dn time, and Cn is added by 1;

[0031] Step 23: judging whether the current sensor is in the error (Error) state and the processor has confirmed, and if not, the next step is executed;

[0032] Step 24: judging whether the current sensor is in the Error state and the processor confirmation timeout time Tout is reached, and if not, the next step is executed;

[0033] Preferably, the step 24 includes:

[0034] Step 241: if the current sensor is in the Error state and the processor confirmation timeout time Tout is reached, the system is set to the Fatal state.

[0035] Step 25: sampling the current sensor to obtain a sensor value Sn;

[0036] Step 26: judging whether the sensor value Sn is in the sampling value reasonable range REFn, and if not, the next step is executed;

[0037] Further, the step 26 can include:

[0038] If the sensor value Sn is in the sampling value reasonable range REFn, go to step 28.

[0039] Step 27: the number Pn is added by 1;

[0040] Step 28: judging whether the number Pn is greater than or equal to the clearable error count threshold T1n, and if not, the next step is executed; ​

[0041] Further, the step 28 can include:

[0042] Step 281: If the count Pn is greater than or equal to the correctable error count threshold T1n, determine whether the count Pn is greater than or equal to the uncorrectable error count threshold T2n, if not, execute the next step;

[0043] The step 281 preferably includes: if the count Pn is greater than or equal to the uncorrectable error count threshold T2n, set the system to Fatal state.

[0044] Step 282: Determine whether the current sensor is in Error state, if not, execute the next step;

[0045] The step 282 preferably includes: if the current sensor is in Error state, go to step 29.

[0046] Step 283: Set the current sensor to Error state, the safety monitoring module triggers a system correctable error interrupt, notifies the processor to process, starts timing, and goes to step 29.

[0047] At this time, the step 23 preferably includes:

[0048] Step 231: If the current sensor is in Error state and the processor has confirmed, set the current sensor to Monitor state, stop timing, and go to the step 25.

[0049] Step 29: Determine whether the current sampling number Cn is greater than or equal to the sampling number Wn within the sampling window time, if yes, go to the step 21, if not, go to the step 22.

[0050] Further, in the steps 241 and 281 above:

[0051] The system enters Fatal state irreversibly;

[0052] And / or, in Fatal state, the system performs clean-up operation to clear critical sensitive information.

[0053] As can be seen from the above flow steps:

[0054] In the Monitor phase, each sensor independently detects, and the safety monitoring module respectively counts the count Pn of the sensor value out of the range REFn within the sampling window time Ln, after the count Pn exceeds the correctable error count threshold T1n, the sensor enters Error state, and the safety monitoring module triggers a system correctable error interrupt to notify the processor to process. If Pn does not exceed T1n at the end of Ln time, the abnormal count value Pn is cleared, and a new sampling window time starts.

[0055] After the sensor enters the Error state, the abnormal sensor value times Pn accumulation count is continued before the current sampling window Ln ends.

[0056] When the sensor enters the Error state, the safety monitoring module triggers a clearable error interrupt and performs timing.

[0057] After the sensor n enters the Error state, the SoC processor confirms the key within the time Tout, and the abnormal count Pn does not reach T2n when the sampling window Ln ends, the sensor returns to the Monitor state.

[0058] The SoC processor can directly make the system enter the Fatal state through the register of the safety monitoring module.

[0059] In summary, the present application has the following beneficial effects:

[0060] 1、The present application takes into account a variety of attack detection means, and can perform multi-dimensional protection on the system.

[0061] 2、The present application establishes an Init phase before the Monitor phase, and can be applied to various external environments.

[0062] 3、The safety monitoring module proposed in the present application has multiple registers that can be configured, which not only can control the sensor sampling method, but also can make the processor have reasonable permission control state jump.

[0063] 4、The present application proposes a two-level error method, which processes different errors at different levels.

[0064] 5、The application uses random number as processor confirmation key in Init stage, and the security is high.

[0065] 6、The application can be applied to the field of SoC chip security monitoring hardware design, and is especially suitable for preventing fault injection attack, physical attack and the like of security Soc chip.

[0066] The above is the preferred embodiment of the application, and it should be pointed out that, for those skilled in the art, without departing from the principles of the application, a number of improvements and refinements can be made, which should also be considered as the protection scope of the application.

Claims

1. A method for implementing secure environment monitoring in a SoC system, characterized in that, The SoC system comprises a processor and a security monitoring module connected with the processor, the security monitoring module is internally provided with at least two of a temperature sensor, a voltage sensor, a frequency sensor, an electromagnetic sensor and an active defense layer, and the method comprises the following steps: Step 1: After the SoC system is powered on or reset, the security monitoring module enters an initialization stage, in which the security monitoring module performs sensor configuration and peripheral environment detection, and the processor configures sensor threshold values according to sensor data acquired in this stage as a reference; In the initialization stage, the processor configures the registers of the security monitoring module according to application, and configures the sampling interval time Dn of each sensor, the sampling times Wn in the sampling window time, the clearable error count threshold T1n, the non-clearable error count threshold T2n, the reasonable sampling value range REFn and the processor confirmation timeout time Tout respectively; Step 2: After the processor completes the configuration, the security monitoring module enters a monitoring stage, in which each sensor independently performs detection; In the monitoring stage, the initial state of each sensor is set to the monitoring state Monitor; The step 2 comprises the following steps: Step 21: for each sensor, the sampling window is started, the count Pn of the sensor which is not in the reasonable sampling value range REFn is set to zero, and the current sampling times Cn is set to zero; Step 22: wait for Dn time, and Cn is added by 1; Step 23: judge whether the current sensor is in the error state and the processor has confirmed: if the current sensor is in the error state and the processor has confirmed, the current sensor is set to the monitoring state Monitor, the timing is stopped, and the step 25 is executed; if not, the next step is executed; Step 24: judge whether the current sensor is in the error state and the processor confirmation timeout time Tout is reached: if the current sensor is in the error state and the processor confirmation timeout time Tout is reached, the system is set to the fatal state; if not, the next step is executed; Step 25: sample the current sensor to obtain a sensor value Sn; Step 26: judge whether the sensor value Sn is in the reasonable sampling value range REFn: if the sensor value Sn is in the reasonable sampling value range REFn, the step 28 is executed; if not, the next step is executed; Step 27: the count Pn is added by 1; Step 28: judge whether the count Pn is greater than or equal to the clearable error count threshold T1n: If the count Pn is greater than or equal to the clearable error count threshold T1n, judge whether the count Pn is greater than or equal to the non-clearable error count threshold T2n, if the count Pn is greater than or equal to the non-clearable error count threshold T2n, the system is set to the fatal state; if not, judge whether the current sensor is in the error state, if the current sensor is in the error state, the step 29 is executed; if not, the current sensor is set to the error state, the security monitoring module triggers the system clearable error interrupt to inform the processor to process, the timing is started, and the step 29 is executed; If the count Pn is less than the clearable error count threshold T1n, then the next step is performed; Step 29: determining whether the current sampling number Cn is greater than or equal to the sampling number Wn in the sampling window time, if yes, then turning to the step 21, if no, then turning to the step 22.

2. The method of claim 1, wherein, The step 1 comprises: In the initialization phase, if an abnormal situation occurs, the processor directly enters a fatal Fatal state by configuring a register of the security monitoring module; And / or, in the initialization phase, the SoC system generates a random number, which is used as a key for the processor to configure the security monitoring module.

3. The method of claim 1, wherein, In the steps 24 and 28: The system entering the Fatal state is irreversible; And / or, in the Fatal state, the system performs a clean-up operation to clear critical sensitive information.

Images