A bandgap startup circuit and a bandgap circuit including the same

Abstract

The present invention discloses a bandgap startup circuit and a bandgap circuit including the bandgap startup circuit. The startup circuit includes an impedance load, a startup control tube, a bias voltage output circuit and a startup current output circuit branched from between the impedance load and the startup control tube via an inverter. One end of the impedance load is connected to a power supply; the startup control tube is connected to the other end of the impedance load and is used to turn on or off the bias voltage output circuit and the startup current output circuit under the bias action of the bandgap voltage output by the bandgap voltage generating circuit; the bias voltage output circuit is used to provide a voltage bias for the operational amplifier; and the startup current output circuit is used to provide a startup current for the operational amplifier. The bandgap circuit includes a startup circuit and an operational amplifier and a bandgap voltage generating circuit connected to the startup circuit in stages. The bandgap startup circuit of the present invention has a simple structure and reliable startup, a simple operational amplifier structure, and does not require a special current source for the operational amplifier, and the power consumption of the bandgap circuit is relatively low.

Description

Technical Field

[0001] The present invention relates to an analog circuit, in particular to a bandgap startup circuit and a bandgap circuit comprising the bandgap startup circuit. Background Art

[0002] A bandgap voltage reference is a circuit that provides a high-precision voltage reference for other functional modules in a circuit system, or converts it into a high-precision current reference to provide a precise and stable bias for other functional modules. It is a very important module in analog integrated circuits and hybrid integrated circuits. Generally speaking, a bandgap voltage generator circuit is used to generate a precise voltage whose value is virtually unaffected by temperature.

[0003] Figure 1 The most basic bandgap circuit 1 is shown, which includes a bandgap voltage generating circuit and an operational amplifier 11. The bandgap voltage generating circuit includes a transistor Q11, a transistor Q12, a resistor R11, a resistor R12, and a resistor R13. The emitter of the transistor Q11 is grounded, and the base and collector are connected to the resistor R13; the other end of the resistor R13 is connected to the resistor R11; the other end of the resistor R11 is connected to the output voltage V REF The emitter of transistor Q12 is grounded, and the base and collector are connected to resistor R12; the other end of resistor R12 is connected to the output voltage V REF The reverse input terminal of the operational amplifier 11 is connected between the resistor R11 and the resistor R13, the positive input terminal of the operational amplifier 11 is connected between the resistor R12 and the transistor Q12, and the output voltage of the operational amplifier 11 is V REF .

[0004] Figure 1 The most basic bandgap circuit 1 shown generates a voltage of V across transistor Q11. BE (Q11), due to the characteristics of Bipolar Junction Transistor (BJT), V BE (Q11) is a negative temperature coefficient voltage. The voltage drop across resistor R13 is ΔV BE =V BE (Q12)-V BE (Q11), ΔV BE It is a positive temperature coefficient voltage. The voltage drop across resistor R11 is R11 / R13 times the voltage drop across resistor R13, i.e. (R11 / R13)ΔV BE Output voltage V REF =V(R11)+V(R13)+V BE (Q11) is the sum of the negative temperature coefficient voltage and the positive temperature coefficient voltage, which can be adjusted to obtain a voltage close to zero temperature coefficient.

[0005] Existing bandgap circuits are almost all developed from the most basic bandgap circuit. Bandgap circuits are self-biased circuits that may encounter a zero-bias state during startup, preventing current from flowing through the bandgap circuit. Therefore, bandgap circuits require a startup circuit to overcome this problem. The bandgap startup circuit activates the bandgap voltage generation circuit to generate the bandgap voltage. After the bandgap voltage is generated, the startup circuit automatically shuts down to reduce overall power consumption.

[0006] The current bandgap startup circuit has a complex structure, and the operational amplifier requires a dedicated current source. How to effectively start the bandgap voltage generation circuit and reduce power consumption while simplifying the startup circuit and operational amplifier while saving chip area is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a bandgap startup circuit with a simple structure and a bandgap circuit including the bandgap startup circuit.

[0008] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0009] The present invention provides a bandgap startup circuit, comprising an impedance load and a startup control tube connected in series with the impedance load. The bandgap startup circuit also comprises a bias voltage output circuit and a startup current output circuit branched from between the impedance load and the startup control tube via an inverter, wherein:

[0010] One end of the impedance load is connected to the power supply;

[0011] The start-up control tube is connected to the other end of the impedance load and is used to turn on or off the bias voltage output circuit and the start-up current output circuit under the bias action of the bandgap voltage output by the bandgap voltage generating circuit;

[0012] The bias voltage output circuit is used to provide a voltage bias for the operational amplifier in the preceding stage of the bandgap voltage generating circuit;

[0013] The startup current output circuit is used to provide a startup current for the operational amplifier in the preceding stage of the bandgap voltage generating circuit.

[0014] The bandgap circuit further includes an operational amplifier and a bandgap voltage generating circuit electrically connected to the bandgap starting circuit in stages.

[0015] The bandgap voltage generating circuit includes a current mirror unit, a voltage detection circuit and a bandgap voltage output circuit, wherein:

[0016] The voltage detection circuit is used to detect the change of the bandgap output voltage caused by temperature or voltage change and output it to the operational amplifier for amplification.

[0017] The operational amplifier is used to amplify the voltage change transmitted from the voltage detection circuit and drive the current mirror unit.

[0018] The current mirror unit is used to feed back the amplified voltage change to the operational amplifier to reduce the voltage change and send the current to the output circuit.

[0019] The output circuit is used for generating a bandgap voltage from the current delivered by the current mirror unit.

[0020] The operational amplifier includes an input pair of transistors and two self-bias circuits corresponding to the input pair of transistors.

[0021] The first self-bias circuit includes a first PMOS transistor and a first NMOS transistor connected in series, the second self-bias circuit includes a second PMOS transistor and a second NMOS transistor connected in series, and the current mirror unit includes a first group of transistors with common source and common gate.

[0022] The first self-bias circuit includes a third PMOS transistor arranged between a first PMOS transistor and a first NMOS transistor connected in series, the second self-bias circuit includes a fourth PMOS transistor arranged between a second PMOS transistor and a second NMOS transistor connected in series, and the current mirror unit includes a second group of cascode transistors connected in series with the first group of cascode transistors, wherein the common gate end of the second group of transistors is connected to the gate-drain short-circuit point of the third and fourth PMOS transistors, where the gates and drains of the PMOS transistors are short-circuited.

[0023] Compared with the prior art, the main advantages of the technical solution of the present invention are as follows:

[0024] 1) The bandgap startup circuit has a simple structure and reliable startup;

[0025] 2) The operational amplifier (OP) has a simple structure and does not require a dedicated current source;

[0026] 3) The bandgap circuit of the present invention has relatively low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0028] Figure 1This is a structural diagram of the most basic existing bandgap circuit;

[0029] Figure 2 It is a circuit module diagram of a bandgap circuit;

[0030] Figure 3 1 is a schematic structural diagram of a bandgap circuit according to an embodiment of the present invention;

[0031] Figure 4 2 is a schematic structural diagram of a bandgap circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0033] like Figure 2 As shown, generally, the bandgap circuit includes a bandgap startup circuit, an operational amplifier, and a bandgap voltage generating circuit electrically connected in stages.

[0034] Below, refer to Figure 3 Embodiment 1 of the present invention will be described.

[0035] The bandgap startup circuit 21 of Example 1 includes an impedance load 211, a startup control transistor 212 connected in series with the impedance load 211, and a bias voltage output circuit 213 and a startup current output circuit 214 branching from the impedance load 211 and the startup control transistor 212 via an inverter IVN. The startup control transistor 212 is configured to turn on or off the bias voltage output circuit 213 and the startup current output circuit 214 under the bias of the bandgap voltage VBG output by the bandgap voltage generating circuit 23. The startup control transistor 212 can be an N-type metal oxide semiconductor (NMOS) transistor, such as MN1. The impedance load includes a plurality of P-type metal oxide semiconductor (PMOS) transistors MP1, MP2, MP3, and MP4 connected in series. The gates of these PMOS transistors are connected together and biased by the output voltage VBG of the bandgap voltage generating circuit 23. One end of the impedance load 211 is connected to a power supply, such as the source of MP1, and the other end of the impedance load 211 is connected to the drain of MN1, such as the drain of MP4. The drain of MN1 is connected to one end of an impedance load 211 and the input of inverter INV1. The output of inverter INV leads to a bias voltage output circuit 213 and a startup current output circuit 214. Bias voltage output circuit 213 is used to provide a voltage bias for the operational amplifier 22 in the preceding stage of bandgap voltage generation circuit 23, and startup current output circuit 214 is used to provide a startup current for the operational amplifier 22 in the preceding stage of bandgap voltage generation circuit 23. Bias voltage output circuit 213 includes a series-connected MP5 and a switching transistor MP7. Startup current output circuit 214 includes a series-connected MP6 and a switching transistor MP8. The gates of PMOS transistors MP5 and MP6 are both connected to the output of inverter INV, the sources of MP5 and MP6 are both connected to a power supply, and the drains of MP5 and MP6 are connected to the sources of MP7 and MP8, respectively. The PD control signal is the inverse of the enable signal EN. The gates of MP7 and MP8 are connected to the PD control signal, and the drains of MP7 and MP8 are respectively connected to the VN node and the VT node of the operational amplifier 22. The source of MN1 is grounded.

[0036] The bandgap start-up circuit 21 can be used in conjunction with any existing operational amplifier and any existing bandgap voltage generating circuit, and is not limited to Figure 3 The operational amplifier 22 and the bandgap voltage generating circuit 23 shown are not limited to Figure 4 An operational amplifier 22' and a bandgap voltage generating circuit 23' are shown.

[0037] The following describes the operating principle of the bandgap startup circuit 21. When the enable signal EN is high, the bandgap voltage generating circuit 23 begins to start. At this point, the bandgap voltage VBG output by the bandgap voltage generating circuit 23 is 0, VS1 is high, and VS2 is low. At this point, power is supplied to the VN node through MP5, causing it to rise high. Since the VN node is the negative terminal of the operational amplifier and the VP node is the positive terminal, the tail current for the operational amplifier's input transistors MP9 and MP10 is supplied by MP6. The entire operational amplifier (OP) 22 begins to operate, and the operating point of OP 22 begins to establish. The output node OPOUT of OP 22 goes low. Current sources MP12-MP16 begin to operate, and the current begins to increase. VBG gradually increases. As the voltage of VBG reaches the threshold of MN1, VS1 goes low, VS2 goes high, and MP5 and MP6 turn off. At this point, the tail current source for OP 22 has become MP17. When the VN node and the VP node reach about 0.7V, the operating point of the entire circuit is stable, VBG is established, and the entire circuit startup is completed.

[0038] In Example 1, the bandgap startup circuit 21 is connected to an operational amplifier 22 at the next stage, and the operational amplifier 22 is connected to a bandgap voltage generating circuit 23 at the next stage. The bandgap voltage generating circuit 23 includes a current mirror unit 231, a voltage detection circuit 232, and a bandgap voltage output circuit 233. The voltage detection circuit 232 is used to detect changes in the bandgap output voltage caused by temperature or voltage changes and output the changes to the operational amplifier 22 for amplification. The operational amplifier 22 is used to amplify the voltage changes transmitted from the voltage detection circuit 232 and drive the current mirror unit 231. The current mirror unit 231 is used to feed back the amplified voltage changes to the operational amplifier 22 to reduce the voltage changes and send a stable current to the output circuit 233, which generates a stable reference voltage VBG.

[0039] Specifically, the operational amplifier 22 includes an input pair of transistors MP9 and MP10, PMOS transistors MP11, MP12, and MP13, NMOS transistors MN2, MN3, MN4, and MN5, and optionally PMOS transistors MP17, MP18, MN6, and MN7 used as switches. The current mirror unit 231 includes PMOS transistors MP14, MP15, and MP16, which form a cascode structure. The sources of MP9 and MP10 are connected together to form a node VT, the gate of MP9 forms a node VN, and the gate of MP10 forms a node VP. The VT node is connected to the startup current output circuit 214 in the bandgap startup circuit 21, and the VN node is connected to the bias voltage output circuit 213 in the bandgap startup circuit 21. The gate of MP12 is connected to the output node OPOUT of the operational amplifier 22. The drains of MP9 and MP10 are connected to the drains of NMOS transistors MN3 and MN4, respectively. The gate and drain of MN3 are interconnected and connected to the gate of MN2 and the drain of MN6. The gate and drain of MN4 are interconnected and connected to the gate of MN5 and the drain of MN7. The drain of MN2 is connected to the drain of MP11, and the drain of MN5 is connected to the drain of MP13 and to the output node OPOUT of the operational amplifier. The drain and gate of MP11 are interconnected and connected to the gate of MP13 and to the drains of MP17 and MP18. The series circuit of MP11 and MN2 serves as a self-bias circuit for operational amplifier 22, and the series circuit of MP13 and MN5 also serves as a self-bias circuit for operational amplifier 22, used to generate tail current for operational amplifier 22 after the bandgap circuit is enabled. The gates of MP17 and MP18 are both connected to the control signal EN, and the gates of MN6 and MN7 are both connected to the control signal PD. The sources of MP11, MP12, MP13, MP17, MP18, MP14, MP15, and MP16 are all connected to a power supply. The sources of MN6 and MN7 are both grounded, the sources of MN3 and MN4 are both grounded, and the sources of MN2 and MN5 are both grounded. Capacitor C is connected between the power supply and the output node OPOUT of operational amplifier 22. The gate of MP12 is also connected to the gates of MP14, MP15, and MP16. The drains of MP14 and MP15 are connected to voltage detection circuit 232, and the drain of MP16 is connected to bandgap voltage output circuit 233.

[0040] Here, the PMOS transistors MP17 and MP18 as switching transistors can be divided into the bandgap startup circuit 21 or the operational amplifier 22. The NMOS transistors MN6 and MN7 as switching transistors can be divided into the bandgap startup circuit 21 or the operational amplifier 22.

[0041] The voltage detection circuit 232 includes a first PNP transistor Q1, a second PNP transistor Q2, and a first resistor R1, a second resistor R2, and a third resistor R3. The bandgap voltage output circuit 233 includes a fourth resistor R4. One end of the first resistor R1 is connected to the emitter of the first PNP transistor Q1, and the other end is grounded. The emitter of the first PNP transistor Q1 is connected to the VN node of the operational amplifier 22, and the emitter of the second PNP transistor Q2 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the VP node of the operational amplifier 22 and is grounded through the first resistor R1. The collectors of Q1 and Q2 are grounded. The base of the first PNP transistor Q1 is connected to the base of the second PNP transistor Q2, and the other end of the third resistor R3 is connected to the drain of MP15. One end of the fourth resistor R4 is connected to the drain of the PMOS transistor MP16, and the other end is grounded. The fourth resistor R4 determines the output voltage VBG at the output terminal.

[0042] The operating principle of the aforementioned bandgap circuit is described below. The bandgap voltage output by the bandgap circuit is VBG. When the enable signal EN is high, the bandgap voltage generating circuit 23 begins to operate. At this point, VBG is 0, VS1 is high, and VS2 is low. At this point, power is supplied to the VN node through MP5, causing it to rise high. Since the VN node is the negative terminal of the operational amplifier and the VP node is the positive terminal, the tail current for the op amp's input transistors MP9 and MP10 is supplied by MP6. The entire operational amplifier (OP) 22 begins to operate, and the operating point of OP 22 begins to establish. OP 22's output node, OPOUT, goes low. Current sources MP12-MP16 begin to operate, and the current begins to increase. VBG gradually increases. As the voltage of VBG reaches the threshold of MN1, VS1 goes low, VS2 goes high, and MP5 and MP6 turn off. At this point, the tail current source for OP 22 has become MP17. When the VN node and the VP node reach about 0.7V, the operating point of the entire circuit is stable, VBG is established, and the entire circuit startup is complete.

[0043] Below, refer to Figure 4 Embodiment 2 of the present invention will now be described. The bandgap startup circuit of Embodiment 2 is identical to that of Embodiment 1, while the operational amplifier 22' and bandgap voltage generating circuit 23' of Embodiment 2 differ from the operational amplifier 22 and bandgap voltage generating circuit 23 of Embodiment 1. Embodiment 2 differs from Embodiment 1 in that two bias transistors are added to the operational amplifier, and three cascode transistors are added to the bandgap voltage generating circuit 23, each connected in series with the three transistors of the current mirror unit 231.

[0044] In this embodiment, the two bias transistors added to the operational amplifier are PMOS transistors MP22 and MP23. MP23 is located between MP11 and MN2, and MP22 is located between MP13 and MN6. The source of MP23 and the source of MP22 are connected to the drain of MP11 and the drain of MP13, respectively. The gate and drain of MP23 are interconnected and connected to the drain of MN2. The gate and drain of MP22 are interconnected and connected to the drain of MN5, forming node VB.

[0045] The three transistors added to the bandgap voltage generating circuit 23 are PMOS transistors MP19, MP20, and MP21 added to the current mirror unit 231. MP19 and MP14 are connected in series to form a mirrored current circuit, MP20 and MP15 are connected in series to form a mirrored current circuit, and MP21 and MP16 are connected in series to form a mirrored current circuit. The gates of MP19, MP20, and MP21 are all connected to node VB. The sources of MP19, MP20, and MP21 are respectively connected to the drains of MP14, MP15, and MP16. The drains of MP19, MP20, and MP21 are respectively connected to the emitter of Q1, the emitter of Q2, and the bandgap voltage output terminal.

[0046] Compared with the first embodiment, the second embodiment adds the above circuit to make the mirror current of the current mirror unit more accurate. The added circuit structure is that the current source adopts a cascode structure. The reference VB of the cascode is provided by short-circuiting the gate and drain of MP22.

[0047] The operating principle of the bandgap circuit of Example 2 is similar to the operating principle of the bandgap circuit of Example 1.

[0048] It can be seen that the startup circuit in the bandgap circuit of the present invention has a simple structure and reliable startup; the operational amplifier (OP) has a simple structure and does not require a special current source; and the power consumption of the bandgap circuit is relatively low.

[0049] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention's description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A bandgap startup circuit, comprising an impedance load and a startup control tube connected in series with the impedance load, characterized in that: The bandgap startup circuit also includes a bias voltage output circuit and a startup current output circuit branched out from between the impedance load and the startup control tube via an inverter, wherein: One end of the impedance load is connected to the power supply; The start-up control tube is connected to the other end of the impedance load and is used to turn on or off the bias voltage output circuit and the start-up current output circuit under the bias effect of the bandgap voltage output by the bandgap voltage generating circuit, wherein the start-up control tube is used to turn on the bias voltage output circuit and the start-up current output circuit when the bandgap voltage is not established, and turn off the bias voltage output circuit and the start-up current output circuit when the bandgap voltage is established; The output end of the bias voltage output circuit is connected to the VN node of the operational amplifier of the previous stage of the bandgap voltage generating circuit, so as to provide a voltage bias for the operational amplifier; The output end of the startup current output circuit is connected to the VT node of the operational amplifier in the previous stage of the bandgap voltage generating circuit, so as to provide startup current for the operational amplifier.

2. A bandgap circuit comprising the bandgap startup circuit according to claim 1, characterized in that: The bandgap circuit further includes an operational amplifier and a bandgap voltage generating circuit electrically connected to the bandgap starting circuit in stages.

3. The bandgap circuit according to claim 2, wherein: The bandgap voltage generating circuit includes a current mirror unit, a voltage detection circuit and a bandgap voltage output circuit, wherein: The voltage detection circuit is used to detect the change of the bandgap output voltage caused by temperature or voltage change and output it to the operational amplifier for amplification. The operational amplifier is used to amplify the voltage change transmitted from the voltage detection circuit and drive the current mirror unit. The current mirror unit is used to feed back the amplified voltage change to the operational amplifier to reduce the voltage change and send the current to the output circuit. The output circuit is used for generating a bandgap voltage from the current delivered by the current mirror unit.

4. The bandgap circuit according to claim 2 or 3, wherein: The operational amplifier includes an input pair of transistors and two self-bias circuits corresponding to the input pair of transistors respectively.

5. The bandgap circuit according to claim 4, wherein: The first self-bias circuit includes a first PMOS transistor and a first NMOS transistor connected in series, the second self-bias circuit includes a second PMOS transistor and a second NMOS transistor connected in series, and the current mirror unit includes a first group of transistors with cascodes.

6. The bandgap circuit according to claim 5, wherein: The first self-bias circuit includes a third PMOS transistor arranged between a first PMOS transistor and a first NMOS transistor connected in series. The second self-bias circuit includes a fourth PMOS transistor arranged between a second PMOS transistor and a second NMOS transistor connected in series. The current mirror unit includes a second group of cascode transistors connected in series with the first group of cascode transistors. The common gate end of the second group of transistors is connected to the gate-drain short-circuit point of the third and fourth PMOS transistors, where the gates and drains of the PMOS transistors are short-circuited.

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