A new bandgap reference temperature compensation circuit

Abstract

A novel bandgap reference temperature compensation circuit includes a startup circuit, a reference core circuit, a dual reference selection circuit and a reference switching circuit; the startup circuit provides a startup signal for the reference core circuit, the startup circuit provides a bias signal for the dual reference selection circuit, the dual reference selection circuit has a first signal input port and a second signal input port, and the dual reference selection circuit outputs a first reference signal Vref1 and a second reference signal Vref2; the reference switching circuit outputs a control signal to the first signal input port and the second signal input port of the dual reference selection circuit through a signal control port; the temperature compensation circuit provides temperature compensation for the first reference signal Vref1 and the second reference signal Vref2 respectively. The second-order compensation circuit of the temperature switching mode of the present invention is simple and easy to design. It has high compatibility, and the unique over-temperature switching structure circuit is easy to design and can be used in parallel with other compensation circuits.

Description

Technical Field

[0001] The invention relates to the field of circuit design, and in particular to a novel bandgap reference temperature compensation circuit. Background Art

[0002] In the design of analog integrated circuits, bandgap reference circuits are often indispensable, but common reference voltage sources are often accompanied by problems such as large temperature drift at too low or too high temperatures, unstable resistance, etc. Therefore, it is necessary to overcome these shortcomings as much as possible to design a more precise bandgap reference circuit. The characteristics of the reference voltage source, such as the reference voltage value VREF, temperature drift, and power consumption, determine its performance. Among them, the temperature drift determines the practicality of the reference voltage source. Lower temperature drift makes the reference voltage of the external circuit more applicable under different temperature conditions, with lower uncontrollable factors, and the power consumption will also be reduced to a certain extent. Therefore, it is necessary to perform temperature compensation on the bandgap reference to reduce the temperature drift. Since the voltage of the bandgap reference is actually composed of many high-order terms, the temperature characteristics of its output voltage are also a curve. Therefore, the temperature stability of the first-order temperature-compensated bandgap reference voltage has certain limitations. In order to improve this defect, some compensation technologies such as second-order curvature compensation and exponential curvature compensation have slowly developed, but these circuits are compensated for a single reference, and the compensation is limited. Summary of the invention

[0003] The present invention aims to provide a compensation circuit with a simple circuit structure and strong compatibility, which can reduce the ppm / ℃ index to one third of the original value, from 14.1ppm / ℃ to 5.51ppm / ℃, within the temperature range of -55℃-125℃.

[0004] A new bandgap reference temperature compensation circuit is proposed. The specific technical solution is as follows:

[0005] A novel bandgap reference temperature compensation circuit, characterized in that it comprises a startup circuit, a reference core circuit, a dual reference selection circuit and a reference switching circuit;

[0006] The startup circuit provides a startup signal for the reference core circuit, the dual reference selection circuit has a first signal input port and a second signal input port, and the dual reference selection circuit outputs a first reference signal Vref1 and a second reference signal Vref2;

[0007] The reference switching circuit outputs a control signal to a first signal input port and a second signal input port of the dual reference selection circuit through a signal control port;

[0008] The temperature compensation circuit provides temperature compensation for the first reference signal Vref1 and the second reference signal Vref2 respectively.

[0009] To better implement the present invention, it can be further provided that: the startup circuit includes a startup circuit 1 and a startup circuit 2, the startup circuit 1 and the startup circuit 2 have the same structure, the reference core circuit includes a reference core circuit 1 and a reference core circuit 2, the reference core circuit 1 and the reference core circuit 2 have the same structure;

[0010] The startup circuit 1 provides a startup signal for the reference core circuit 1 , and the startup circuit 2 provides a startup signal for the reference core circuit 2 .

[0011] In order to better realize the present invention, it is possible to further:

[0012] The startup circuit includes MOS tubes M1, M2 and M3, the source of MOS tube M1 is connected to the power supply terminal VDD, the drain of MOS tube M1 is connected to the gate of MOS tube M2, and the drain and source of MOS tube M2 are respectively connected to the ground terminal GND.

[0013] Further:

[0014] The reference core circuit includes MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, triode Q1, triode Q2, triode Q3, resistor R1 and resistor R2;

[0015] The gate of the MOS tube M8 is connected to the gate of the MOS tube M9, the source of the MOS tube M8 is connected to the power supply terminal VDD, the drain of the MOS tube M8 is connected to the drain of the MOS tube M6, the source of the MOS tube M6 is connected to the emitter of the transistor Q2 via the resistor R1, and the collector of the transistor Q2 is connected to the ground terminal GND;

[0016] The source of the MOS tube M9 is connected to the power supply terminal VDD, the drain of the MOS tube M9 is connected to the drain of the MOS tube M7, the source of the MOS tube M7 is connected to the emitter of the transistor Q3, and the collector of the transistor Q3 is connected to the ground terminal GND;

[0017] The source of the MOS tube M7 is connected to the gate of the MOS tube M10, the source of the MOS tube M10 is connected to the power supply terminal VDD, the drain of the MOS tube M10 is connected to the source of the MOS tube M11, the drain of the MOS tube M11 is connected to the emitter of the transistor Q4 via the resistor R2, the collector of the transistor Q4 is connected to the ground terminal GND, and the gate of the MOS tube M11 is connected to the drain of the MOS tube M8.

[0018] The source of the MOS tube M4 is connected to the power supply terminal VDD, the gate of the MOS tube M4 is connected to the drain of the MOS tube M8, the drain of the MOS tube M4 is connected to the drain of the MOS tube M5, the source of the MOS tube M5 is connected to the emitter of the transistor Q1, and the base and collector of the transistor Q1 are connected to the ground terminal GND.

[0019] Further:

[0020] The dual reference selection circuit includes a MOS tube M12, a MOS tube M13 and a MOS tube M17;

[0021] The source of the MOS transistor M12 is connected to the drain of M10, the drain of the MOS transistor M12 is connected to the source of the MOS transistor M13, the gate of the MOS transistor 12 is connected to the drain of the MOS transistor M8, the source of the MOS transistor M13 provides a first reference signal Vref1, the drain of the MOS transistor M13 is connected to the source of the MOS transistor M17, and the gate of the MOS transistor M13 is a first signal input port;

[0022] The gate of the MOS transistor M17 is a second signal input port, the source of the MOS transistor M17 provides a second reference signal Vref2, and the source of the MOS transistor M17 is connected to the output end of the temperature compensation circuit.

[0023] Further:

[0024] The reference switching circuit includes a MOS tube M14, a MOS tube M15, a transistor Q5, a transistor Q6, a resistor R3 and a resistor R4;

[0025] The source of the MOS tube M14 is connected to the power supply terminal VDD, the drain of the MOS tube M14 is connected to the ground terminal GND via the resistor R3, the drain of the MOS tube M14 is connected to the base of the transistor Q5, the collector of the transistor Q5 is connected to the power supply terminal VDD, the emitter of the transistor Q5 is connected to the ground terminal GND via the resistor R4, the emitter of the transistor Q5 is connected to the base of the transistor Q6, the collector of the transistor Q6 is connected to the drain of the MOS tube M15, the source of the MOS tube M15 is connected to the power supply terminal VDD, the common end of the drain of the MOS tube M15 and the collector of the transistor is a signal control port, and the emitter of the transistor Q6 is connected to the ground terminal GND.

[0026] The beneficial effects of the present invention are as follows: First, the second-order compensation circuit of the temperature switching mode of the present invention is simple and easy to design.

[0027] Second, it has high compatibility, and the unique over-temperature switching structure circuit is easy to design and can be used in parallel with other compensation circuits.

[0028] Third, it has strong adaptability. For different circuits, better compensation effects can be obtained by adjusting the temperature drift point, changing the resistor type, or adjusting the resistor value. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A circuit diagram of the present invention;

[0030] Figure 2 It is a schematic diagram of the effect of the present invention;

[0031] Figure 3 is the new bandgap benchmark. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] like Figure 1 As shown:

[0034] A novel bandgap reference temperature compensation circuit comprises a startup circuit, a reference core circuit, a dual reference selection circuit and a reference switching circuit;

[0035] The startup circuit includes startup circuit 1 and startup circuit 2, and the startup circuit 1 and startup circuit 2 have the same structure. The reference core circuit includes reference core circuit 1 and reference core circuit 2, and the reference core circuit 1 and reference core circuit 2 have the same structure. In order to facilitate the distinction, the electronic component numbers in the startup circuit 2 and the reference core circuit 2 are represented by adding "`" to the upper right corner of the corresponding component numbers in the startup circuit 1 and the reference core circuit 1, for example, "MOS tube M1" in the driving circuit 1 is represented as "MOS tube M1`" in the startup circuit 2.

[0036] The startup circuit 1 provides a startup signal for the reference core circuit 1, the startup circuit 2 provides a startup signal for the reference core circuit 2, the dual reference selection circuit has a first signal input port and a second signal input port, and the dual reference selection circuit outputs a first reference signal Vref1 and a second reference signal Vref2;

[0037] The reference switching circuit outputs a control signal to a first signal input port and a second signal input port of the dual reference selection circuit through a signal control port;

[0038] The temperature compensation circuit provides temperature compensation for the first reference signal Vref1 and the second reference signal Vref2 respectively.

[0039] The startup circuit includes MOS tubes M1, M2 and M3. The source of MOS tube M1 is connected to the power supply terminal VDD, the drain of MOS tube M1 is connected to the gate of MOS tube M2, and the drain and source of MOS tube M2 are respectively connected to the ground terminal GND.

[0040] The reference core circuit includes MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, triode Q1, triode Q2, triode Q3, resistor R1 and resistor R2;

[0041] The gate of the MOS tube M8 is connected to the gate of the MOS tube M9, the source of the MOS tube M8 is connected to the power supply terminal VDD, the drain of the MOS tube M8 is connected to the drain of the MOS tube M6, the source of the MOS tube M6 is connected to the emitter of the transistor Q2 via the resistor R1, and the collector of the transistor Q2 is connected to the ground terminal GND;

[0042] The source of the MOS tube M9 is connected to the power supply terminal VDD, the drain of the MOS tube M9 is connected to the drain of the MOS tube M7, the source of the MOS tube M7 is connected to the emitter of the transistor Q3, and the collector of the transistor Q3 is connected to the ground terminal GND;

[0043] The source of the MOS tube M7 is connected to the gate of the MOS tube M10, the source of the MOS tube M10 is connected to the power supply terminal VDD, the drain of the MOS tube M10 is connected to the source of the MOS tube M11, the drain of the MOS tube M11 is connected to the emitter of the transistor Q4 via the resistor R2, the collector of the transistor Q4 is connected to the ground terminal GND, and the gate of the MOS tube M11 is connected to the drain of the MOS tube M8.

[0044] The source of the MOS tube M4 is connected to the power supply terminal VDD, the gate of the MOS tube M4 is connected to the drain of the MOS tube M8, the drain of the MOS tube M4 is connected to the drain of the MOS tube M5, the source of the MOS tube M5 is connected to the emitter of the transistor Q1, and the base and collector of the transistor Q1 are connected to the ground terminal GND.

[0045] The dual reference selection circuit includes a MOS tube M12, a MOS tube M13 and a MOS tube M17;

[0046] The source of the MOS transistor M12 is connected to the drain of M10, the drain of the MOS transistor M12 is connected to the source of the MOS transistor M13, the gate of the MOS transistor 12 is connected to the drain of the MOS transistor M8, the source of the MOS transistor M13 provides a first reference signal Vref1, the drain of the MOS transistor M13 is connected to the source of the MOS transistor M17, and the gate of the MOS transistor M13 is a first signal input port;

[0047] The gate of the MOS tube M17 is the second signal input port, the source of the MOS tube M17 provides the second reference signal Vref2, the drain of the MOS tube M17 is connected to the output end of the temperature compensation circuit, the drain of the MOS tube M17 is connected to the drain of the MOS tube M11`` in the reference core circuit, and the source of the MOS tube M17 is connected to the drain of the MOS tube M13.

[0048] The reference switching circuit includes a MOS tube M14, a MOS tube M15, a transistor Q5, a transistor Q6, a resistor R3 and a resistor R4;

[0049] The source of the MOS tube M14 is connected to the power supply terminal VDD, the drain of the MOS tube M14 is connected to the ground terminal GND via the resistor R3, the drain of the MOS tube M14 is connected to the base of the transistor Q5, the collector of the transistor Q5 is connected to the power supply terminal VDD, the emitter of the transistor Q5 is connected to the ground terminal GND via the resistor R4, the emitter of the transistor Q5 is connected to the base of the transistor Q6, the collector of the transistor Q6 is connected to the drain of the MOS tube M15, the source of the MOS tube M15 is connected to the power supply terminal VDD, the common end of the drain of the MOS tube M15 and the collector of the transistor is a signal control port, and the emitter of the transistor Q6 is connected to the ground terminal GND.

[0050] The working process of the present invention is:

[0051] The high temperature compensation effect of the used benchmark is better than the low temperature compensation effect. By adjusting the benchmark core resistor R2 and resistor R2` of the two benchmarks to change the zero temperature drift point and adjust the temperature switching point at the same time, the temperature drift correction of the circuit is more dependent on high temperature compensation.

[0052] The resistance adjustment is as follows:

[0053] According to the resistance formula:

[0054] R=ρL / S

[0055] ρ represents the resistivity of the resistor, which is determined by its own properties, L represents the length of the resistor, and S represents the cross-sectional area of ​​the resistor.

[0056] Among them, the relationship between ρ and temperature t (℃) is

[0057] ρt=ρ0(1+αt)

[0058] Where ρt and ρ0 are the resistivity at t℃ and 0℃ respectively. The temperature coefficient α of semiconductor materials is generally negative and has a large value. The temperature coefficients of different resistor types are different, so at the same temperature drift point, the reference voltage values ​​corresponding to different resistor types are also different.

[0059] Based on the temperature characteristics of the resistors mentioned above, the resistance value of a resistor usually decreases as the temperature increases, but the temperature coefficient α of different types of resistors is different, so the actual resistance value at the same temperature will be different. Therefore, using different types of resistors and adjusting the resistance value can produce two bandgap references with the same temperature drift point but different reference voltage values, such as Figure 1 As shown. Since M11 mirrors the PTAT current of M8, by reducing the reference core resistor R2 of reference 1, its temperature drift point can be shifted to the left, accompanied by a decrease in the reference voltage value, and the overall circuit moves to the lower left; by increasing the reference core resistor R2' of reference 2, its temperature drift point can be shifted to the right, accompanied by an increase in the reference voltage value, and the overall circuit moves to the upper right, as shown. Figure 3 As shown in the figure, the reference voltage values ​​of the two references can be made almost equal after adjustment, Tr1 = -5°, Tr2 = 65°.

[0060] Then use high temperature compensation with better effect to compensate, and produce a bandgap reference with smaller temperature drift. The switching of this invention is based on the reference switcher. The switching of the reference switcher is a circuit that is easy to design. The three-temperature switching mode can be realized through the over-temperature comparator, so that the switching of three references can be realized, and the reference with lower temperature drift can be further generated. Similarly, this can also be extended to a larger number, which varies according to the actual reference circuit. It has certain applicability, but it will be accompanied by some problems of increased power consumption.

[0061] The specific process is as follows:

[0062] The purpose of the reference startup circuit is to drive the circuit out of the degenerate bias point. A key problem of the reference circuit is the existence of the "degenerate" bias point.

[0063] When the power supply starts to power on, all transistors output zero current. In order to solve the above problem, a startup circuit is provided to drive the circuit out of the degenerate bias point.

[0064] MOS tubes M1, M2 and M3 form the startup circuit of the reference core. When the power starts to be powered on, MOS tube M2 starts to conduct, forming a path to the ground, and the gate potential of MOS tube M3 is pulled to a low point. G,M3 <VDD-|V THP,M3 |, MOS tube M3 starts to conduct, and at the same time pulls the drain of MOS tube M3 to a high potential. D,M3 >VTHN +V EB When , MOS tube M7, transistor Q3 branch, MOS tube M6, resistor R1, transistor Q2, MOS tube M5 and transistor Q1 branch begin to conduct, and the gate of MOS tube M5 begins to discharge, so that MOS tube M5 is turned off, and the bandgap reference circuit leaves the degenerate state.

[0065] When the power is on, the MOS tube M2 is equivalent to a capacitor, so that the gate potential of the MOS tube M3 is raised, and the startup circuit is disconnected from the circuit without causing additional power consumption.

[0066] MOS tubes M4, M8 and M9 are all PMOS tubes, and MOS tubes M5, M6 and M7 are all NMOS tubes. They form a PTAT current generating circuit with resistor R1, and the result is:

[0067]

[0068] Since the output branch M11 tube mirrors M8, the output voltage is:

[0069] V RFE =K*I PTAT *R2+V BE4

[0070] Where K is the ratio of the width to length ratio of M11 to M4. The complete output voltage is:

[0071] V REF =R2*V T *ln8 / R1+V BE4

[0072] The output circuit is composed of a MOS tube M10, a MOS tube M11, a resistor R2 and a transistor Q4, wherein the MOS tube M10 and the MOS tube M11 are both PMOS tubes.

[0073] The positive temperature current and the negative temperature current are superimposed on the resistor R2 to generate a reference output voltage, while providing a bias current for the subsequent circuit.

[0074] MOS tube M10 works in the deep linear region, has a large width-to-length ratio, and a small on-resistance. Its main function is to increase the impedance from MOS tube M11 upward from ro11 to gm11ro11Ron10, which can effectively improve the PSRR of output VREF. At the same time, when designing MOS tube M10, its on-resistance cannot be too large, otherwise it will increase Vds10, and under the influence of the channel length modulation effect, the mirror image of MOS tube M11 will be inaccurate.

[0075] The drain terminal of MOS transistor M13 is connected to the source terminal of MOS transistor M17 to serve as the new output reference after second-order compensation. The gate terminals of MOS transistor M13 and MOS transistor M17 are both controlled by the output signal out of the overtemperature comparator. When the temperature is higher than 45 °C, a high potential is output, MOS transistor M13 is turned off, and MOS transistor M17 is turned on, and the second reference signal Vref2 controls the circuit.

[0076] When the temperature is lower than 45 °C, a low potential is output, MOS transistor M13 is turned on, and MOS transistor M17 is turned off, and the first reference signal Vref1 controls the circuit.

[0077] For different references, better temperature compensation effects can be obtained by changing the overtemperature point of the overtemperature comparator.

[0078] The overtemperature comparator circuit consists of MOS transistor M14 and MOS transistor M15, transistor Q5, transistor Q6, resistor R3, and resistor R4. Among them, both MOS transistor M14 and MOS transistor M15 are PMOS transistors.

[0079] As the temperature rises, VBE6 decreases, IC6 decreases, and when IC6 < ID15, the output of the overtemperature comparator reverses.

[0080] The present invention uses a reference switcher for switching, selects the parts of two references close to their respective zero-temperature drift points. The temperature drift of this part is small, and second-order compensation is performed on the reference, thereby generating a new reference with a lower temperature drift. The original temperature drifts of the selected reference circuits are different, and the generated effects will also be different. Due to the unique temperature switching mode, the compensation part of the circuit can be adjusted according to requirements.

[0081] For different references, the low-temperature compensation and high-temperature compensation effects of the circuit are different, and there are differences according to the different high- and low-temperature compensation effects. Adjusting the switching point of the reference switcher can make the degrees of compensation required for high and low temperatures different, and then compensation can be performed in the temperature range with better compensation effects.

[0082] As Figure 3 shown in the simulation results, according to the simulation results, the temperature drift of the original reference from -55 °C to 125 °C is (3.06 mV) 14.1 ppm / °C, and the temperature drift of the new reference after second-order compensation has been reduced to (1.19 mV)

[0083] 5.51 ppm / °C.

[0084] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0085] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A novel bandgap reference temperature compensation circuit, characterized in that: It includes a startup circuit, a reference core circuit, a dual reference selection circuit and a reference switching circuit; The startup circuit provides a startup signal for the reference core circuit, the dual reference selection circuit has a first signal input port and a second signal input port, and the dual reference selection circuit outputs a first reference signal Vref1 and a second reference signal Vref2; The reference switching circuit outputs a control signal to a first signal input port and a second signal input port of the dual reference selection circuit through a signal control port; The temperature compensation circuit provides temperature compensation for the first reference signal Vref1 and the second reference signal Vref2 respectively; The startup circuit includes a startup circuit 1 and a startup circuit 2, the startup circuit 1 and the startup circuit 2 have the same structure, the reference core circuit includes a reference core circuit 1 and a reference core circuit 2, the reference core circuit 1 and the reference core circuit 2 have the same structure; The startup circuit 1 provides a startup signal for the reference core circuit 1, and the startup circuit 2 provides a startup signal for the reference core circuit 2; The startup circuit includes a MOS tube M1, a MOS tube M2 and a MOS tube M3, the source of the MOS tube M1 is connected to the power supply terminal VDD, the drain of the MOS tube M1 is connected to the gate of the MOS tube M2, and the drain and source of the MOS tube M2 are respectively connected to the ground terminal GND; The reference core circuit includes MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, triode Q1, triode Q2, triode Q3, resistor R1 and resistor R2; The gate of the MOS tube M8 is connected to the gate of the MOS tube M9, the source of the MOS tube M8 is connected to the power supply terminal VDD, the drain of the MOS tube M8 is connected to the drain of the MOS tube M6, the source of the MOS tube M6 is connected to the emitter of the transistor Q2 via the resistor R1, and the collector of the transistor Q2 is connected to the ground terminal GND; The source of the MOS tube M9 is connected to the power supply terminal VDD, the drain of the MOS tube M9 is connected to the drain of the MOS tube M7, the source of the MOS tube M7 is connected to the emitter of the transistor Q3, and the collector of the transistor Q3 is connected to the ground terminal GND; The source of the MOS tube M7 is connected to the gate of the MOS tube M10, the source of the MOS tube M10 is connected to the power supply terminal VDD, the drain of the MOS tube M10 is connected to the source of the MOS tube M11, the drain of the MOS tube M11 is connected to the emitter of the transistor Q4 via the resistor R2, the collector of the transistor Q4 is connected to the ground terminal GND, and the gate of the MOS tube M11 is connected to the drain of the MOS tube M8; The source of the MOS tube M4 is connected to the power supply terminal VDD, the gate of the MOS tube M4 is connected to the drain of the MOS tube M8, the drain of the MOS tube M4 is connected to the drain of the MOS tube M5, the source of the MOS tube M5 is connected to the emitter of the transistor Q1, and the base and collector of the transistor Q1 are connected to the ground terminal GND; The dual reference selection circuit includes a MOS tube M12, a MOS tube M13 and a MOS tube M17; The source of the MOS transistor M12 is connected to the drain of M10, the drain of the MOS transistor M12 is connected to the source of the MOS transistor M13, the gate of the MOS transistor M12 is connected to the drain of the MOS transistor M8, the source of the MOS transistor M13 provides a first reference signal Vref1, the drain of the MOS transistor M13 is connected to the source of the MOS transistor M17, and the gate of the MOS transistor M13 is a first signal input port; The gate of the MOS tube M17 is a second signal input port, the source of the MOS tube M17 provides a second reference signal Vref2, and the source of the MOS tube M17 is connected to the output end of the temperature compensation circuit; The reference switching circuit includes a MOS tube M14, a MOS tube M15, a transistor Q5, a transistor Q6, a resistor R3 and a resistor R4; The source of the MOS tube M14 is connected to the power supply terminal VDD, the drain of the MOS tube M14 is connected to the ground terminal GND via the resistor R3, the drain of the MOS tube M14 is connected to the base of the transistor Q5, the collector of the transistor Q5 is connected to the power supply terminal VDD, the emitter of the transistor Q5 is connected to the ground terminal GND via the resistor R4, the emitter of the transistor Q5 is connected to the base of the transistor Q6, the collector of the transistor Q6 is connected to the drain of the MOS tube M15, the source of the MOS tube M15 is connected to the power supply terminal VDD, the common end of the drain of the MOS tube M15 and the collector of the transistor is a signal control port, and the emitter of the transistor Q6 is connected to the ground terminal GND.

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