Regulating device and memory therefor, regulator

Abstract

The application provides a regulating device, a memory thereof and a regulator. The regulating device comprises N comparators, a primary regulating circuit and N secondary regulating circuits. A first input end of each comparator is used for inputting a data signal, and a second input end of each comparator is used for inputting a secondary regulating voltage. The primary regulating circuit is used for outputting a primary regulating voltage according to a regulating signal. An output end of each secondary regulating circuit is connected with an output end of the primary regulating circuit, and the output end of each secondary regulating circuit is connected with the second input end of one comparator. Each secondary regulating circuit has a variable resistance, and the maximum equivalent resistance of the variable resistance of each secondary regulating circuit is different. The primary regulating voltage is used for controlling the size of the variable resistance in each secondary regulating circuit, and the size of the variable resistance determines the size of the secondary regulating voltage. The regulating device provided by the application can make the square wave signal output by the comparator optimal.

Description

Technical Field

[0001] This application relates to integrated circuit technology, and more particularly to a regulating device and its memory and regulator. Background Technology

[0002] Double Data Rate (DDR) memory, with its advantages of high speed and low power consumption, has been widely used in data communication fields with data storage requirements. During memory read and write operations, the memory controller performs write or read operations on the data in the memory through the memory's physical layer (PHY). The data slice module in the DDR PHY is responsible for high-speed data transmission and reception, and the maximum operating rate of the data slice directly determines the performance of the DDR PHY.

[0003] In DATASLICE design, the design of the data receiver is extremely important. A typical DATASLICE has eight data receivers, each corresponding to a data path. Each data path outputs a comparator that produces a square wave signal. The quality of this square wave signal determines the maximum operating speed of the DATASLICE, and this quality is determined by the comparator's output voltage, positive terminal voltage, and negative terminal voltage. During DATASLICE manufacturing, the common-mode voltage, output voltage, and reference voltage of each comparator are fixed. The closer the positive terminal voltage of a comparator is to its negative terminal common-mode voltage (center voltage), the better the quality of the square wave signal output, and consequently, the better the performance of the DATASLICE, DDR PHY, and memory.

[0004] During the data slicing process, due to manufacturing deviations or other factors, the eight comparators at the data receiver terminals have different common-mode voltages, reference voltages, and output voltages. Therefore, adjusting the input voltage of the comparators to adapt to their different performance characteristics and optimize the quality of the square wave signal output becomes a pressing problem. Summary of the Invention

[0005] This application provides an adjustment device and its memory and regulator to adjust the input voltage of the comparator according to the performance of different comparators, so that the square wave signal output by the comparator has the best quality.

[0006] An adjusting device, comprising:

[0007] There are N comparators, each with its first input terminal for inputting a data signal and its second input terminal for inputting a two-stage regulating voltage, where N is a positive integer.

[0008] A primary regulation circuit, wherein the input terminal of the primary regulation circuit is used to receive an externally input regulation signal, and the primary regulation circuit is used to output a primary regulation voltage according to the regulation signal;

[0009] There are N secondary regulation circuits, the input of each secondary regulation circuit is connected to the output of the primary regulation circuit, and the output of each secondary regulation circuit is connected to the second input of a comparator.

[0010] Each secondary regulation circuit has a variable resistance value, and the maximum equivalent resistance value of the variable resistance values ​​of every two secondary regulation circuits is different. The primary regulation voltage is used to control the magnitude of the variable resistance value in each secondary regulation circuit, and the magnitude of the variable resistance value determines the magnitude of the secondary regulation voltage.

[0011] The adjustment device provided in this embodiment includes N comparators, a primary adjustment circuit, and N secondary adjustment circuits. The first input terminal of each comparator is used to input a data signal, and the second input terminal is used to input the secondary adjustment voltage. The primary adjustment circuit receives the adjustment signal and outputs the primary adjustment voltage to the secondary adjustment circuit. Each of the N comparators is connected to one secondary adjustment circuit, and each secondary adjustment circuit has a variable resistance value adapted to the connected comparator. The equivalent resistance values ​​of the variable resistance values ​​of each of the N secondary adjustment circuits are different.

[0012] Therefore, this two-stage regulation circuit can adjust the primary regulation voltage to different degrees, and the final secondary regulation voltage output to the connected comparator is closer to the common-mode voltage (center voltage) of the sinusoidal signal received by the comparator. This results in a higher quality output signal from the comparator during use, a higher maximum operating speed for the DATASLICE, and better read / write performance for the memory containing the DATASLICE.

[0013] In one embodiment, the secondary regulation circuit includes:

[0014] A two-stage comparator, wherein the output of the two-stage comparator is connected to the second input of the comparator;

[0015] A fixed resistor is connected to the first input terminal of the secondary comparator;

[0016] The variable resistance unit is connected to the second input terminal of the secondary comparator.

[0017] In one embodiment, the variable resistance unit includes:

[0018] A sliding rheostat, wherein the first end of the sliding rheostat is connected to the output end of the first-stage regulating circuit, and the second end of the sliding rheostat is grounded;

[0019] Multiple transistors, the source of each transistor is connected to the resistance wire of the sliding rheostat, and the source of each transistor is located at a different position on the resistance wire; the drain of each transistor is connected to the second input terminal of the secondary comparator.

[0020] The primary regulation voltage is used to control one of the plurality of transistors to turn on, thereby controlling the magnitude of the secondary regulation voltage.

[0021] In one embodiment, the N secondary regulation circuits contain multiple transistors arranged in different ways.

[0022] In one embodiment, the maximum equivalent resistance values ​​of the sliding rheostats included in the N secondary adjustment circuits are different.

[0023] In one embodiment, the fixed resistor includes:

[0024] A first resistor, with its first end grounded and its second end connected to the first input terminal of the second-stage comparator;

[0025] The second resistor has its first end connected to the second end of the first resistor, and its second end connected to the output of the second-stage comparator.

[0026] In one embodiment, the maximum equivalent resistance of the variable resistance unit of each secondary adjustment circuit is equal to the resistance of the first input terminal of the connected secondary comparator, and the resistance of the first input terminal of the secondary comparator is equal to the sum of the resistances of the first resistor and the second resistor.

[0027] In one embodiment, the primary regulation circuit includes:

[0028] A signal receiving unit is used to receive the adjustment signal;

[0029] Multiple third resistors are provided, with the first end of each third resistor connected to the signal receiving unit and the second end of each third resistor serving as the output terminal of the first-stage adjustment circuit.

[0030] The signal receiving unit is used to control at least one of the plurality of third resistors to have current flowing through it according to the adjustment signal.

[0031] In one embodiment, the adjustment signal is a binary signal.

[0032] On the other hand, this application provides a memory including the adjustment device as described in the first aspect.

[0033] On the other hand, this application provides a regulator including the memory as described in the first aspect, the regulator further including:

[0034] A signal processor is provided, wherein its input terminal is connected to the output terminals of the N comparators, and its output terminal is connected to the input terminal of the first-stage adjustment circuit. The signal processor is used to receive N square wave signals output by the N comparators, generate the adjustment signal based on the N square wave signals, and input the adjustment signal to the first-stage adjustment circuit.

[0035] The signal processor 41 in the regulator 40 provided in this embodiment can generate the adjustment signal according to the square wave signal output by each comparator 100. The adjustment signal does not need to be manually input to the first-level adjustment circuit 200 by the operator, thus realizing automatic adjustment of the memory and greatly enhancing the data read and write capability of the memory. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0037] Figure 1 A schematic diagram illustrating the principle of the comparator outputting a square wave signal provided in this application.

[0038] Figure 2 Another schematic diagram of the comparator output square wave signal provided in this application.

[0039] Figure 3 This is a schematic diagram of the adjustment device provided in Embodiment 1 of this application.

[0040] Figure 4 This is a schematic diagram of the adjustment device provided in Embodiment 1 of this application.

[0041] Figure 5 This is a schematic diagram of the adjustment device provided in Embodiment 2 of this application.

[0042] Figure 6 This is a schematic diagram of the adjustment device provided in Embodiment 3 of this application.

[0043] Figure 7 This is a diagram showing the relationship between the adjustment signal and the primary adjustment voltage provided in Embodiment 3 of this application.

[0044] Figure 8 A schematic diagram of a memory provided for one embodiment of this application.

[0045] Figure 9 A schematic diagram of a regulator provided for one embodiment of this application.

[0046] Explanation of reference numerals in the attached figures

[0047] Adjustment device 10

[0048] Comparator 100

[0049] Primary regulating circuit 200

[0050] Signal receiving unit 210

[0051] Third resistor 220

[0052] 300-stage regulating circuit

[0053] 310 Second-level comparator

[0054] 320 fixed resistor

[0055] First resistor 321

[0056] Second resistor 322

[0057] Variable resistance unit 330

[0058] Sliding rheostat 331

[0059] Transistor 332

[0060] Memory 20

[0061] Regulator 30

[0062] Signal Processor 31

[0063] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0064] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0065] During the read and write operations of Double Data Rate (DDR) memory, the memory controller performs write or read operations on the data in the memory through the memory's physical layer (PHY). The data slice module (or DDR data slice module) in the DDR PHY is responsible for high-speed data transmission and reception, and the maximum operating rate of the data slice directly determines the performance of the DDR PHY.

[0066] A DATASLICE has eight data receivers, each corresponding to a data path. Each data path has a comparator at its output, which outputs a square wave signal. The quality of this square wave signal determines the maximum operating speed of the DATASLICE, and the quality of the square wave signal is determined by the voltage at the comparator's output, positive terminal, and negative terminal.

[0067] During the fabrication of a DATASLICE, the common-mode voltage, output voltage, and reference voltage of each comparator are fixed. The closer the common-mode voltage calculated from the voltage at the comparator's negative terminal, output voltage, and reference voltage is to the comparator's fixed common-mode voltage, the better the quality of the square wave signal output by that comparator, and consequently, the better the performance of the DATASLICE, DDR PHY, and memory.

[0068] During the fabrication of a data SLICE, due to manufacturing variations or other factors, the eight comparators at the data receiver terminals have different common-mode voltages, reference voltages, and output voltages. Therefore, the input voltages of the comparators need to be adjusted to optimize the quality of the square wave signal output by each comparator, taking into account the performance of each individual comparator. However, current technology does not allow for the adjustment of the input voltage of each comparator individually.

[0069] Based on this, this application provides an adjustment device and its memory and regulator for adjusting a DDR data chip module. The adjustment device has a two-stage adjustment circuit. The first-stage adjustment circuit receives an externally input adjustment signal to generate a primary adjustment voltage. Then, a second-stage adjustment circuit connected to each comparator inputs a secondary adjustment voltage adapted to that comparator to each comparator. As a result, the voltage at the second input terminal of each comparator becomes closer to the common-mode voltage (center voltage) of the first input terminal of each comparator. This makes the high and low level widths in the square wave signal output by each comparator more equal, thereby improving the quality of the square wave signal, increasing the maximum operating speed of the DATASLICE, and improving the read / write performance of the memory containing the DATASLICE.

[0070] like Figure 1 and Figure 2 The diagram shows the correspondence between the voltage at the first input terminal (sine wave signal) and the voltage at the second input terminal (ref) of the comparator and the square wave signal of the comparator.

[0071] Figure 1 In the middle, the voltage at the second input terminal of the comparator ( Figure 1 Point B shown) and the common-mode voltage of the first input terminal voltage ( Figure 1 The significant difference between point A and the low level in the square wave signal results in a narrower high-level width than low-level width, leading to poor signal quality. Figure 2 In this context, the common-mode voltage (center voltage) of the second input voltage of the comparator and the first input voltage are... Figure 1 If the high and low level widths of the square wave signal are equal (point A in the middle), the square wave signal has better quality.

[0072] Please refer to Figure 3 and Figure 4 The adjustment device 10 provided in Embodiment 1 of this application includes N comparators 100, a first-stage adjustment circuit 200, and N second-stage adjustment circuits 300, where N is an integer greater than zero. Optionally, such as... Figure 4 As shown, the memory's DATASLICE includes eight of these comparators 100, N=8. See also Figure 3 It can be known that, Figure 4 The diagram shows the adjustment device 10 when N=8, but does not limit the adjustment device 10.

[0073] Figure 4In this diagram, I0, I1, I2, I3, I4, I5, I6, and I7 each represent one of the comparators 100. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DQ7 are the data signals at the first input terminals of comparators I0, I1, I2, I3, I4, I5, I6, and I7, respectively. The ports of each comparator connected to the secondary adjustment circuit 300 are the second input terminals of comparators I0, I1, I2, I3, I4, I5, I6, and I7. Z0, Z1, Z2, Z3, Z4, Z5, Z6, and Z7 are the digital square wave signals output by comparators I0, I1, I2, I3, I4, I5, I6, and I7, respectively. The first input terminals of comparators I0, I1, I2, I3, I4, I5, I6, and I7 are all negative terminals of the comparators, and the second input terminals of comparators I0, I1, I2, I3, I4, I5, I6, and I7 are all positive terminals of the comparators; or, the first input terminals of comparators I0, I1, I2, I3, I4, I5, I6, and I7 are all positive terminals of the comparators, and the second input terminals of comparators I0, I1, I2, I3, I4, I5, I6, and I7 are all negative terminals of the comparators.

[0074] The first input terminal of each comparator 100 is used to input a data signal, and the second input terminal of each comparator 100 is used to input a secondary adjustment voltage, which is input to the second input terminal of the comparator 100 by the connected secondary adjustment circuit 300. The data signal is a sinusoidal signal. The first input terminal can be the positive terminal of the comparator 100, and correspondingly, the second input terminal is the negative terminal of the comparator 100. Alternatively, the first input terminal can be the negative terminal of the comparator 100, and correspondingly, the second input terminal is the positive terminal of the comparator 100. The specifications and model of the comparator 100 are selected according to actual needs and are not limited in this application. Optionally, the value of N can also be selected according to actual needs and is not limited in this application.

[0075] The input terminal of the first-stage regulation circuit 200 is used to receive an externally input regulation signal, and the first-stage regulation circuit 200 then outputs a primary regulation voltage based on the regulation signal. The regulation signal is determined based on the square wave signals output by the N comparators 100. The other input terminals of the first-stage regulation circuit 200 are connected to a power supply terminal 20, which provides current to the first-stage regulation circuit 200 so that the first-stage regulation circuit 200 outputs the primary regulation voltage based on the regulation signal and the received current.

[0076] Optionally, the primary regulating circuit 200 may be configured with multiple branches to be turned on, and the number of branches to be turned on can determine the magnitude of the primary regulating voltage.

[0077] Optionally, resistors can be installed on the multiple branches to be conducted. The resistance value of each branch to be conducted can be selected according to actual needs, and this application does not impose any limitations. The voltage at the power supply terminal 20 can be selected according to actual needs, and this application does not impose any limitations.

[0078] The input terminal of each secondary regulation circuit 300 is connected to the output terminal of the primary regulation circuit 100, and the output terminal of each secondary regulation circuit 300 is connected to the second input terminal of a comparator 100. Each secondary regulation circuit 300 has a variable resistance value, and the maximum equivalent resistance values ​​of the N secondary regulation circuits 300 are different. The primary regulation voltage is used to control the magnitude of the variable resistance value of each secondary regulation circuit 300, and the magnitude of the variable resistance value determines the magnitude of the secondary regulation voltage.

[0079] That is, when the primary regulation voltage passes through the secondary regulation circuit 300, the variable resistance of the secondary regulation circuit 300 can control and regulate the primary regulation voltage that has been input to the secondary regulation circuit 300, and the regulated primary regulation voltage is connected to the comparator 100 as the output value of the secondary regulation voltage.

[0080] The secondary regulation circuit 300 needs to be selected based on the connected comparator 100. Since the reference voltage, common-mode voltage, etc., of each of the N comparators 100 are different, the maximum equivalent resistance of the variable resistance of the secondary regulation circuit 300 is different. Thus, when the N secondary regulation circuits 300 receive the primary regulation voltage, they can adjust the primary regulation voltage according to the connected comparator 100, making the secondary regulation voltage of the connected comparator 100 closer to the common-mode voltage corresponding to the data signal of the connected comparator 100. For ease of description, when the secondary regulation voltage of the connected comparator 100 is closer to the common-mode voltage corresponding to the data signal of the connected comparator 100 (e.g., the difference between the secondary regulation voltage and the common-mode voltage is within a preset range), it can also be described as the secondary regulation voltage of the connected comparator 100 and the voltage corresponding to the data signal of the connected comparator 100 being more matched. The aforementioned preset range is a value preset according to the actual circuit conditions.

[0081] When the secondary adjustment voltage received at the second input terminal of the comparator 100 is more matched with the voltage corresponding to the data signal received at the first input terminal of the comparator 100, the quality of the square wave signal output by the comparator 100 is better, the maximum operating rate of the DATASLICE is higher, and the read / write performance of the memory containing the DATASLICE is also better.

[0082] For example, if the data signal at the first input of comparator 100 is a sinusoidal signal, and the peak value of this data signal is 0.3V and the center voltage (common-mode voltage) is 1.2V, then when the square wave signal output by comparator 100 has optimal quality, the secondary adjustment voltage at the second input of comparator 100 should be 1.2V. Therefore, the function of the primary adjustment circuit 200 provided in this embodiment is to control the primary adjustment voltage to be within a certain range based on 1.2V, for example, the primary adjustment voltage could be 1.35V. The function of the secondary adjustment circuit 300 provided in this embodiment is to adjust the primary adjustment voltage closer to 1.2V, meaning the secondary adjustment voltage output by the secondary adjustment circuit 300 is closer to 1.2V. Thus, the quality of the square wave signal output by comparator 100 during use is better, the maximum operating speed of the DATASLICE is higher, and the read / write performance of the memory containing the DATASLICE is also better.

[0083] Furthermore, if N secondary regulation circuits 300 are not provided between the N comparators 100 and the primary regulation circuit 200, the voltage at the second input terminal of each comparator 100 will all originate from the same reference voltage. Typically, the same reference voltage input to different second input terminals of the comparators 100 constitutes a large-swing signal. A large-swing signal will cause significant noise at the first input terminal of the comparator 100. In this case, since the second input terminals of all N comparators 100 are connected to the output of the primary regulation circuit, if the noise at different comparators 100 is independent, the primary regulation voltage will be unstable. This instability in the primary regulation voltage will result in significant distortion of the square wave signal output by each comparator 100, degrading the performance of the memory containing the N comparators 100.

[0084] Therefore, the secondary regulation circuit 300 provided in this embodiment can not only further regulate the primary regulation voltage output by the primary regulation circuit 200, but also isolate the noise between each comparator 100, thereby stabilizing the primary regulation voltage.

[0085] The regulating device 10 provided in this embodiment includes N comparators 100, a primary regulating circuit 200, and N secondary regulating circuits 300. The first input terminal of each comparator 100 is used to input the data signal, and the second input terminal of each comparator 100 is used to input the secondary regulating voltage. The primary regulating circuit 200 is connected to a power supply terminal 20 and receives the regulating signal before outputting a primary regulating voltage to the secondary regulating circuit 300. Optionally, the range of the primary regulating voltage can be 0.5 to 1 times the rated voltage of the power supply terminal 20 to which the primary regulating circuit 200 is connected. Each of the N comparators 100 is connected to one secondary regulating circuit 300, and each secondary regulating circuit 300 has a variable resistance value, and the maximum equivalent resistance values ​​of the variable resistance values ​​of the N secondary regulating circuits 300 are different.

[0086] Therefore, the secondary regulation circuit 300 can adjust the primary regulation voltage to different degrees, and the final secondary regulation voltage output to the connected comparator is also closest to the common-mode voltage of the first input terminal of the comparator, thereby making the quality of the square wave signal output by the connected comparator better during use. Therefore, the regulation device 10 provided in this embodiment can enable the DATASLICE to operate at a higher maximum speed and improve the read / write performance of the memory containing the DATASLICE.

[0087] Please refer to Figure 5 Based on Embodiment 1, Embodiment 2 of this application further describes the secondary adjustment circuit 300 in the DDR data chip module 10. The secondary adjustment circuit 300 includes a secondary comparator 310, a fixed resistor 320, and a variable resistance unit 330.

[0088] The output terminal of the secondary comparator 310 is connected to the second input terminal of the comparator 100. The fixed resistor 320 is connected to the first input terminal of the secondary comparator 310, and the resistance value of the fixed resistor 320 is fixed. Optionally, the fixed resistor 320 includes a first resistor 321 and a second resistor 322. The first terminal of the first resistor 321 is grounded, and the second terminal of the first resistor 321 is connected to the first input terminal of the secondary comparator 310. The first terminal of the second resistor 322 is connected to the second terminal of the first resistor 321, and the second terminal of the second resistor 322 is connected to the output terminal of the secondary comparator 310. Figure 2 As shown, the first resistor 321 is resistor R1, and the second resistor 322 is resistor R2. Optionally, the first input terminal of the second-level comparator 310 is the negative terminal of the second-level comparator 310.

[0089] The variable resistance unit 330 is connected to the second input terminal of the secondary comparator 300, and the maximum equivalent resistance of the variable resistance unit 330 is equal to the resistance of the fixed resistor 320. The magnitude of the secondary regulated voltage output by the secondary comparator 310 can be adjusted by adjusting the resistance of the variable resistance unit 330.

[0090] Optionally, the variable resistance unit 330 further includes a sliding rheostat 331 and a plurality of transistors 332. The first terminal of the sliding rheostat 331 is connected to the output terminal of the first-stage adjustment circuit 200, and the second terminal of the sliding rheostat 331 is grounded. The source of each transistor 332 is connected to the resistance wire of the sliding rheostat 331, and the position of the source of each transistor 332 on the resistance wire is different. The drain of each transistor 332 is connected to the second input terminal of the second-stage comparator 310. The primary adjustment voltage is used to control the conduction of one of the plurality of transistors 332, thereby controlling the magnitude of the secondary adjustment voltage. The transistor 332 can be a PMOS transistor, an NMOS transistor, or other types of transistors, as long as it can cut off current in the off state and can be normally turned on.

[0091] For example Figure 5 As shown, the plurality of transistors 332 includes transistors SW0, SW1, ..., SW(n-1) and SWn. The primary regulating voltage is used to control the conduction of one of the transistors SW0, SW1, ..., SW(n-1) and SWn. The sliding rheostat 331 includes resistors Ra and Rb, both of which have variable values. Resistor Rb is the effective resistance of the sliding rheostat 331.

[0092] Optionally, the equivalent resistance of the variable resistance of each of the secondary regulation circuits 300 is equal to the resistance of the first input terminal of the connected secondary comparator 310, and the resistance of the first input terminal is equal to the sum of the resistances of the first resistor 321 and the second resistor 322. That is, R1 + R2 = Ra + Rb. The relationship between the secondary regulation voltage VREF_SEC and the primary regulation voltage VREF_FST is: VREF_SEC = VREF_FST * Rb / R1. Since the resistance of the first resistor R1 is fixed, the resistance of Rb determines the value of the secondary regulation voltage VREF_SEC.

[0093] The resistance value of Rb depends on the arrangement of the plurality of transistors 332 and / or the resistance value of the sliding rheostat 331 itself.

[0094] In one alternative approach, the arrangement of the transistors 332 within the N secondary regulation circuits 300 can differ. This arrangement can be understood as the different contact positions of the sources of the transistors 332 on the sliding rheostat 331. Since the source of each transistor 332 is connected to the resistance wire of the sliding rheostat 331, when the source of each transistor 332 is located at different positions on the resistance wire of the sliding rheostat 331, the Rb value will also be different after each transistor 332 is turned on. If the transistors in each of the N secondary regulation circuits 300 are arranged differently, even if the primary regulation voltage only turns on one transistor in each secondary regulation circuit 300, the secondary regulation voltage output by each secondary regulation circuit 300 will be different.

[0095] In another alternative approach, the sliding rheostats 331 included in the N secondary regulation circuits 300 are different, meaning that the maximum equivalent resistance values ​​of the sliding rheostats 331 are different. In this case, the transistors in each of the N secondary regulation circuits 300 can be arranged in the same way, and the secondary regulation voltage output by each transistor after it is turned on is different. The equivalent resistance value of the sliding rheostat 331 in each secondary regulation circuit 300 can be selected according to actual needs, and this application does not impose any limitations on it.

[0096] Please see Figure 6 This application provides a further description of the first-stage adjustment circuit 200 based on embodiment one or embodiment two. The first-stage adjustment circuit 200 includes a signal receiving unit 210 and a plurality of third resistors 220.

[0097] The signal receiving unit 210 receives the adjustment signal. The first end of the third resistor 220 is connected to the signal receiving unit 210, and the second end of the third resistor 220 is the output terminal of the first-stage adjustment circuit 200. The signal receiving unit 210 controls at least one of the plurality of third resistors 220 to have current flowing through it according to the adjustment signal. The signal receiving unit 210 can be a circuit module that performs simple processing on the adjustment signal and controls at least one of the plurality of third resistors 220 to have current flowing through it based on the processed result.

[0098] Optionally, the adjustment signal can be a binary signal, and the signal receiving unit 210 is a circuit module that can process binary signals.

[0099] The relationship between the regulation signal and the primary regulation voltage is as follows: Figure 7As shown. Assuming there are four third resistors 220 in this primary regulating circuit, when the regulating signal is

[1111] , the primary regulating voltage is smaller, and it can be assumed that all of the third resistors 220 have current flowing through them. When the regulating signal is

[1110] , the primary regulating voltage increases, and it can be assumed that three of the four third resistors 220 have current flowing through them. When the regulating signal is

[0000] , the primary regulating voltage is at its maximum, and it can be assumed that one of the third resistors 220 has current flowing through it.

[0100] Please see Figure 8 This application also provides a memory 30, which includes the adjustment device 10 described in any one of embodiments one to three above. The memory 30 may also include other devices to adapt to the adjustment device 10, which can be selected according to actual conditions, and this application does not limit them.

[0101] Please see Figure 9 This application also provides a regulator 40, which includes the memory 30 and a signal processor 41. The input terminal of the signal processor 41 is connected to the output terminals of the N comparators 100, and the output terminal of the signal processor 41 is connected to the input terminal of the first-stage regulation circuit 200. The signal processor 41 receives N square wave signals output by the N comparators 100, generates a regulation signal based on the N square wave signals, and inputs the regulation signal to the first-stage regulation circuit 200. The signal processor 41 has a preset standard square wave signal that each comparator 100 should output.

[0102] The signal processor 41 can generate the adjustment signal based on the actual square wave signal output by each comparator 100 and the standard square wave signal of each comparator 100, and then input the adjustment signal to the first-stage adjustment circuit 200, which then outputs the primary adjustment voltage based on the adjustment signal.

[0103] The signal processor 41 in the regulator 40 provided in this embodiment can generate the adjustment signal according to the square wave signal output by each comparator 100. The adjustment signal does not need to be manually input to the first-level adjustment circuit 200 by the operator, thus realizing automatic adjustment of the memory and greatly enhancing the data read and write capability of the memory.

[0104] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0105] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An adjusting device, characterized in that, include: There are N comparators, each with its first input terminal for inputting a data signal and its second input terminal for inputting a two-stage regulating voltage, where N is a positive integer. A primary regulation circuit, wherein the input terminal of the primary regulation circuit is used to receive an externally input regulation signal, and the primary regulation circuit is used to output a primary regulation voltage according to the regulation signal; There are N secondary regulation circuits, the input of each secondary regulation circuit is connected to the output of the primary regulation circuit, and the output of each secondary regulation circuit is connected to the second input of a comparator. Each secondary regulation circuit has a variable resistance value, and the maximum equivalent resistance value of the variable resistance value of each secondary regulation circuit is different. The primary regulation voltage is used to control the magnitude of the variable resistance value in each secondary regulation circuit, and the magnitude of the variable resistance value determines the magnitude of the secondary regulation voltage.

2. The apparatus according to claim 1, characterized in that, The secondary regulation circuit also includes: A two-stage comparator, wherein the output of the two-stage comparator is connected to the second input of the comparator; A fixed resistor is connected to the first input terminal of the secondary comparator; The variable resistance unit is connected to the second input terminal of the secondary comparator.

3. The apparatus according to claim 2, characterized in that, The variable resistance unit includes: A sliding rheostat, wherein the first end of the sliding rheostat is connected to the output end of the first-stage regulating circuit, and the second end of the sliding rheostat is grounded; Multiple transistors, the source of each transistor is connected to the resistance wire of the sliding rheostat, and the source of each transistor is located at a different position on the resistance wire; the drain of each transistor is connected to the second input terminal of the secondary comparator. The primary regulation voltage is used to control one of the plurality of transistors to turn on, thereby controlling the magnitude of the secondary regulation voltage.

4. The apparatus according to claim 2, characterized in that, The transistors in the N secondary regulation circuits are arranged in different ways.

5. The apparatus according to claim 2, characterized in that, The maximum equivalent resistance values ​​of the sliding rheostats included in the N secondary adjustment circuits are different.

6. The apparatus according to claim 2, characterized in that, The fixed resistor includes: A first resistor, with its first end grounded and its second end connected to the first input terminal of the second-stage comparator; The second resistor has its first end connected to the second end of the first resistor, and its second end connected to the output of the second-stage comparator.

7. The apparatus according to claim 6, characterized in that, The maximum equivalent resistance of the variable resistance unit in each secondary adjustment circuit is equal to the resistance of the first input terminal of the connected secondary comparator, and the resistance of the first input terminal of the secondary comparator is equal to the sum of the resistances of the first resistor and the second resistor.

8. The apparatus according to any one of claims 1-7, characterized in that, The primary regulation circuit includes: A signal receiving unit is used to receive the adjustment signal; Multiple third resistors are provided, with the first end of each third resistor connected to the signal receiving unit and the second end of each third resistor serving as the output terminal of the first-stage adjustment circuit. The signal receiving unit is used to control at least one of the plurality of third resistors to have current flowing through it according to the adjustment signal.

9. The adjusting device according to any one of claims 1-7, characterized in that, The adjustment signal is a binary signal.

10. A memory, characterized in that, Includes the regulating device as described in any one of claims 1-9.

11. A regulator, characterized in that, Including the memory as described in claim 10, the regulator further includes: A signal processor is provided, wherein its input terminal is connected to the output terminals of the N comparators, and its output terminal is connected to the input terminal of the first-stage adjustment circuit. The signal processor is used to receive N square wave signals output by the N comparators, generate the adjustment signal based on the N square wave signals, and input the adjustment signal to the first-stage adjustment circuit.

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