An all-in-one memory-computing circuit, chip system and electronic device

Abstract

The application discloses a memory-computing integrated circuit for realizing memory-computing integrated complex multiply-accumulate calculation with smaller area and power consumption. The memory-computing integrated circuit comprises at least one memory-computing sub-array and at least one multiply-accumulate (MAC) processing circuit. Each memory-computing sub-array comprises n*m memory-computing units arranged in n rows and m columns. Each memory-computing unit is connected with a group of row signal lines and a group of column signal lines. The group of row signal lines is connected with m memory-computing units in the same row, and the group of column signal lines is connected with n memory-computing units in the same column. Each memory-computing unit is used for calculating the product of the real part and the imaginary part of a first complex number, the real part and the imaginary part of a second complex number, and the inverse data of the imaginary part of the second complex number, to obtain a first product result and a second product result. The target MAC processing circuit is used for accumulating a plurality of first product results and a plurality of second product results.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a memory-computing integrated circuit, a chip system and an electronic device. BACKGROUND

[0002] In recent years, big data and artificial intelligence technologies have rapidly developed in various fields, and the communication and computing demands of data have sharply increased, which has posed higher challenges to the energy efficiency of integrated circuits. The emerging new computing-in-memory (CIM) computing architecture has attracted widespread attention. It solves the energy consumption problems such as data transfer in computing tasks by integrating computing circuits in storage circuits. With the development of artificial intelligence (AI) algorithms and signal processing algorithms, the memory-computing integrated architecture needs to solve the basic operations of complex number operations.

[0003] The current memory-computing integrated architecture for solving complex number operations is usually implemented based on static random access memory (SRAM). In the complex number operation, the input signal in the form of a complex number is input into the SRAM unit, and the SRAM unit stores two positive real parts of another complex number and one positive imaginary part and one negative imaginary part. The input signal in the form of a complex number is multiplied by the real part and the imaginary part of the two complex numbers stored in the SRAM unit, respectively, and then accumulated to obtain the multiplication and accumulation result. Because two real parts and imaginary parts need to be stored, twice the storage array resources are required, and each memory array needs a peripheral resource (such as peripheral driving circuit and back-end wiring resources), which leads to a large volume, high power consumption and low computing efficiency of the current memory-computing integrated circuit. SUMMARY

[0004] The present application provides a memory-computing integrated circuit for implementing complex number multiplication and accumulation computing in memory-computing integration with smaller area and power consumption. The present application also provides a corresponding chip system and an electronic device.

[0005] The first aspect of the present application provides a memory-computing integrated circuit, which comprises a memory-computing array and a data processing circuit. The memory-computing array comprises at least one memory-computing sub-array, wherein each memory-computing sub-array comprises n*m memory-computing units arranged in n rows and m columns. The data processing circuit comprises at least one multiplication-and-accumulation (MAC) processing circuit. Each memory-computing sub-array corresponds to one MAC processing circuit. N and M are integers greater than 1. Each memory-computing unit is connected to a group of row signal lines and a group of column signal lines. The group of row signal lines is connected to m memory-computing units in the same row. The group of column signal lines is connected to n memory-computing units in the same column. The memory-computing sub-array where the n memory-computing units are located corresponds to a target MAC processing circuit.

[0006] Each memory-computing unit is configured to receive first real part bit data and first imaginary part bit data of a first complex number from the connected group of row signal lines, and perform operations on second real part bit data of a second complex number and related data of target bit data to obtain a first product result and a second product result. The second real part bit data and the target bit data are stored in the memory-computing unit. The target bit data includes the second imaginary part bit data or inverse data of the second imaginary part bit data. The related data of the target bit data includes the second imaginary part bit data and inverse data of the second imaginary part bit data.

[0007] The target MAC processing circuit is configured to receive a plurality of first product results and a plurality of second product results from the connected m groups of column signal lines, and accumulate the plurality of first product results to obtain first output data and accumulate the plurality of second product results to obtain second output data.

[0008] In the present application, the memory-computing integrated circuit refers to integrating a computing circuit in a memory circuit to realize memory-computing integration. The memory-computing integrated circuit can be applied to complex number operation or real number operation. The memory-computing unit is used to realize the multiplication of two complex numbers. The MAC processing circuit is used to accumulate the results of a plurality of memory-computing units.

[0009] In the present application, the memory-computing integrated circuit can be any form of bit array structure memory, such as a register, a random access memory (RAM), etc. The random access memory includes a static random access memory (SRAM), an embedded dynamic random access memory (EDRAM), etc.

[0010] In the present application, the first complex number can also be referred to as the first operand, and the second complex number can also be referred to as the second operand. The first complex number can be represented by x r +x i i, where x r is the real part of the first complex number, and x i is the imaginary part of the first complex number. The second complex number can be represented by w r +w i i, where w r is the real part of the second complex number, and w i is the imaginary part of the second complex number. The first real part bit data can be the bit data of different significant bits of the two's complement form of the binary conversion of the real part of the first complex number, such as x r,1 …x r,b . The first imaginary part bit data can be the bit data of different significant bits of the binary conversion of the imaginary part of the first complex number, such as x i,1 …x i,b . The second real part bit data can be the bit data of different significant bits of the binary conversion of the real part of the second complex number, such as w r,1 …w r,m . The second imaginary part bit data can be the bit data of different significant bits of the binary conversion of the imaginary part of the second complex number, such as w i,1 …w i,m . The inverse data of the second imaginary part bit data refers to the data obtained by taking the inverse of the second imaginary part bit data, such as where subscript r represents the real part, subscript i represents the imaginary part, subscript b represents the bit width of the first complex number, and subscript m represents the bit width of the second complex number.

[0011] It should be noted that in the present application, the first real part bit data, the first imaginary part bit data, the second real part bit data, the second imaginary part bit data, and the inverse data of the second imaginary part bit data can all be analog signals represented by a level. The real part of the first complex number refers to the numerical value of the real part of the first complex number, the imaginary part of the first complex number refers to the numerical value of the imaginary part of the first complex number, the real part of the second complex number refers to the numerical value of the real part of the second complex number, and the imaginary part of the second complex number refers to the numerical value of the imaginary part of the second complex number.

[0012] In the present application, the first product result refers to the product result containing imaginary numbers after multiplication, such as x r,p ·w i,q and x i,p ·w r,q , and the second product result refers to the product result not including imaginary numbers after multiplication, such as x r,p ·w r,q and p is any value in 1…b, and q is any value in 1…m.

[0013] In the present application, the first output data can be the accumulation result of a plurality of (x r,p ·w i,q +x i,p ·w r,q ) and the second output data can be the accumulation result of a plurality of .

[0014] As can be known from the above first aspect, in the storage and computing unit, the second imaginary part bit data or the inverse data of the second imaginary part bit data is stored, and the second imaginary part bit data and the inverse data of the second imaginary part bit data can be obtained by negation. Thus, in the complex multiplication operation, the second imaginary part bit data and the inverse data of the second imaginary part bit data can be directly used for multiplication operation, and only one copy of the real part and the imaginary part of the second complex number is stored to complete the multiplication and accumulation operation of two complex numbers, without storing two copies of the positive real part of the second complex number, one copy of the positive imaginary part of the second complex number, and one copy of the negative imaginary part of the second complex number. Thus, the volume of the storage and computing integrated circuit is effectively reduced, the power consumption is reduced, two data do not need to be calculated, and the calculation efficiency is improved.

[0015] In a possible implementation manner of the first aspect, each storage and computing unit includes a first computing cell (LCC), a second computing cell, a third computing cell, a fourth computing cell, a first storage unit, and a second storage unit.

[0016] The first storage unit is connected to the first computing cell and the third computing cell, and the second storage unit is connected to the second computing cell and the fourth computing cell.

[0017] At least one first row signal line in a group of row signal lines is connected to the first computing cell and the fourth computing cell, at least one second row signal line is connected to the second computing cell and the third computing cell, a first column signal line in a group of column signal lines is connected to the first computing cell and the second computing cell, and a second column signal line is connected to the third computing cell and the fourth computing cell.

[0018] The first storage unit is configured to store target bit data, and the second storage unit is configured to store second real part bit data.

[0019] In the possible implementation, the storage and calculation unit includes first to fourth calculation units, each of which can be understood as a local computing cell (LCC), and the first to fourth calculation units can be represented as LCC1, LCC2, LCC3 and LCC4 respectively. The first storage unit connected to LCC1 and LCC3 in the row direction stores second imaginary part bit data or inverse data of the second imaginary part bit data, and the second storage unit connected to LCC2 and LCC4 in the row direction stores second real part bit data. The first row signal line can have one or more, and the second row signal line can also have one or more. No matter how many first row signal lines or second row signal lines there are, each first row signal line is connected to LCC1 and LCC4 respectively, and inputs first real part bit data x r,p to LCC1 and LCC4, and each second row signal line is connected to LCC2 and LCC3 respectively, and inputs first imaginary part bit data x i,p The difference is that the first real part bit data on different first row signal lines can be different, and the first imaginary part bit data on different second row signal lines can be different. The first column signal line is connected to LCC1 and LCC2, and is used to transmit the product results calculated by LCC1 and LCC2 respectively to the target MAC processing circuit. The second column signal line is connected to LCC3 and LCC4, and is used to transmit the product results calculated by LCC3 and LCC4 respectively to the target MAC processing circuit. As can be seen from the above description, the connection line mode between the row signal line, the column signal line and the four LCCs in the storage and calculation unit, and the connection line mode between the storage unit and the four LCCs can simplify the circuit connection and optimize the circuit structure of the storage and calculation unit.

[0020] In a possible implementation of the first aspect, the first storage unit is configured to output the second imaginary part bit data to the first calculation unit and output inverse data of the second imaginary part bit data to the third calculation unit, and the second storage unit is configured to output the second real part bit data to the second calculation unit and the fourth calculation unit.

[0021] The first calculation unit is configured to calculate the product of the first real part bit data and the second imaginary part bit data, the second calculation unit is configured to calculate the product of the first imaginary part bit data and the second real part bit data, the third calculation unit is configured to calculate the product of the first imaginary part bit data and the inverse data of the second imaginary part bit data, and the fourth calculation unit is configured to calculate the product of the first real part bit data and the second real part bit data.

[0022] The first product result includes the product of the first real part bit data and the second imaginary part bit data, and the product of the first imaginary part bit data and the second real part bit data, and the second product result includes the product of the first real part bit data and the second real part bit data, and the product of the first imaginary part bit data and the inverted data of the second imaginary part bit data.

[0023] In the possible implementation, the first storage unit outputs w i,q to the LCC1, and outputs to the LCC3. The second storage unit outputs w r,q to the LCC2 and the LCC4. r,p The LCC1 is configured to calculate x i,q ·w i,p The LCC2 is configured to calculate x r,q ·w r,p The LCC3 is configured to calculate The LCC4 is configured to calculate x r,q ·w From the description of the implementation, it can be seen that storing one copy of the real part bit data and the imaginary part bit data of the second complex number in the two storage units can realize the multiplication of two complex numbers, and effectively reduces the size of the storage-computing integrated circuit.

[0024] In a possible implementation of the first aspect, the target MAC processing circuit includes an imaginary part processing circuit and a real part processing circuit, the imaginary part processing circuit is connected with the m first column signal lines, and the real part processing circuit is connected with the m second column signal lines.

[0025] The imaginary part processing circuit is configured to receive, through each first column signal line, a first product result from a storage-computing unit of each column, accumulate a plurality of first product results from a same column to obtain a first column accumulation result, perform weighted operation on first column accumulation results of different columns, and then accumulate the first column accumulation results of the different columns after the weighted operation to obtain first output data.

[0026] The real part processing circuit is configured to receive, through each second column signal line, a second product result from a storage-computing unit of each column, accumulate a plurality of second product results from a same column to obtain a second column accumulation result, perform weighted operation on second column accumulation results of different columns, and then accumulate the second column accumulation results of the different columns after the weighted operation to obtain second output data.

[0027] In the possible implementation, the target MAC processing circuit includes two circuits for accumulating the product result containing the imaginary number after multiplication and accumulating the real part product result after multiplication, for example, the imaginary part processing circuit is configured to accumulate a plurality of (x r,p ·w i,q +x i,p ·w r,q) is used to accumulate The order of accumulation can be to accumulate the product results on the same column first to obtain corresponding column accumulation results, then to perform weighted operation on the column accumulation results, and then to accumulate the weighted accumulation results of different columns. This accumulation manner can give different weights in combination with the importance of bit data on different columns, so as to obtain more accurate output data.

[0028] In a possible implementation manner of the first aspect, the data processing circuit further includes a compensation circuit, one end of the compensation circuit being connected with the N second row signal lines through the target column signal line, and the other end being connected with the real part processing circuit in each of the at least one MAC processing circuit.

[0029] The compensation circuit is used to receive a plurality of first imaginary part bit data from the N second row signal lines, accumulate the plurality of first imaginary part bit data, and transmit the accumulation result of the plurality of first imaginary part bit data to the real part processing circuit.

[0030] The real part processing circuit is used to perform summation operation on the accumulation result of the plurality of first imaginary part bit data and the second output data, to obtain third output data.

[0031] In this possible implementation manner, considering that the inverse data of the second imaginary part bit data x is used in the multiplication operation of two complex numbers i,p , the second output data will be affected to a certain extent, therefore, the compensation circuit is used to accumulate x i,p transmitted through the second row signal line, and transmit the accumulation result to the real part processing circuit, so as to compensate the second output data, and the accuracy of the output third output data after compensation is higher.

[0032] In a possible implementation manner of the first aspect, the m storage and calculation units in the same row are used to store bit data of different significant bits after binary conversion of the real part and the imaginary part of the second complex number respectively, and the n storage and calculation units in the same column are used to store bit data of the same significant bit of different second complex numbers.

[0033] In this possible implementation manner, the m storage and calculation units in the same row in the N-row-by-M-column storage and calculation subarray store w r,1 …w r,m , w i,1 …w i,m , or , w i,1 …w i,m , or The arrangement order in the m storage and calculation units can be from low bit to high bit, or from high bit to low bit. The arrangement order of the storage and calculation units in the same column from top to bottom can be w1…wn.

[0034] In a possible implementation of the first aspect, the first real part bit data of the first complex number comprises bit data of different significant bits of the real part of the first complex number after binary conversion; and the first imaginary part bit data of the first complex number comprises bit data of different significant bits of the imaginary part of the first complex number after binary conversion.

[0035] In the possible implementation, the first real part bit data comprises at least one bit data in x r,1 …x r,b , and the first imaginary part bit data comprises at least one bit data in x i,1 …x i,b .

[0036] In a possible implementation of the first aspect, the first storage unit comprises a first transistor and a second transistor, and a first inverter or / and a second inverter.

[0037] The gate of the first transistor and the gate of the second transistor are connected with a word line (WL) respectively, the word line being used to activate the first transistor and the second transistor; the source of the first transistor is connected with the input end of the first inverter or the output end of the second inverter, and the drain of the first transistor is connected with a first bit line (BL).

[0038] The source of the second transistor is connected with a second bit line BLB, and the drain of the second transistor is connected with the output end of the first inverter or the input end of the second inverter.

[0039] When the target bit data is the second imaginary part bit data: the first inverter is used to convert the second imaginary part bit data stored between the source of the first transistor and the input end of the first inverter into inverse data of the second imaginary part bit data, and output to the second transistor; the first bit line and the second bit line are used to read or write the second imaginary part bit data from the first storage unit and read or write the second real part bit data from the second storage unit.

[0040] When the target bit data is the inverse data of the second imaginary part bit data: the second inverter is used to convert the inverse data of the second imaginary part bit data stored between the drain of the second transistor and the input end of the second inverter into the second imaginary part bit data, and output to the first transistor; the first bit line and the second bit line are used to read or write the second imaginary part bit data from the first storage unit and read or write the second real part bit data from the second storage unit.

[0041] In the possible implementation, the first storage unit in the storage and calculation unit can quickly and effectively obtain the other one in the case of storing the second imaginary part bit data or the inverse data thereof through two transistors and one or two inverters, so as to realize the complex multiplication and accumulation operation with a small volume of circuit.

[0042] In a possible implementation of the first aspect, the first calculation unit includes a third transistor and a fourth transistor, the gate of the third transistor is connected with the first storage unit to receive the second imaginary part bit data from the first storage unit, the source of the third transistor is grounded, the drain of the third transistor is connected with the source of the fourth transistor, the gate of the fourth transistor is connected with the first row signal line, and the drain of the fourth transistor is connected with the first column signal line.

[0043] The second calculation unit includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is connected with the second storage unit to receive the second real part bit data from the second storage unit, the source of the fifth transistor is grounded, the drain of the fifth transistor is connected with the source of the sixth transistor, the gate of the sixth transistor is connected with the second row signal line, and the drain of the sixth transistor is connected with the first column signal line.

[0044] The third calculation unit includes a seventh transistor and an eighth transistor, the gate of the seventh transistor is connected with the first storage unit to receive the inverse data of the second imaginary part bit data from the first storage unit, the source of the seventh transistor is grounded, the drain of the seventh transistor is connected with the source of the eighth transistor, the gate of the eighth transistor is connected with the second row signal line, and the drain of the eighth transistor is connected with the second column signal line.

[0045] The fourth calculation unit includes a ninth transistor and a tenth transistor, the gate of the ninth transistor is connected with the second storage unit to receive the second real part bit data from the second storage unit, the source of the ninth transistor is grounded, the drain of the ninth transistor is connected with the source of the tenth transistor, the gate of the tenth transistor is connected with the first row signal line, and the drain of the tenth transistor is connected with the second column signal line.

[0046] It should be noted that the connection relationship between the source and the drain of the third transistor to the tenth transistor and other devices can be interchanged, and the position relationship described above is not limited.

[0047] In the possible implementation, the four LCCs can each include two transistors, the multiplication operation is implemented through the two transistors, and the product result is transmitted on the column signal line.

[0048] In a possible implementation of the first aspect, the target column signal line is connected with the second row signal line through an eleventh transistor, a gate of the eleventh transistor is connected with the second row signal line, a source of the eleventh transistor is grounded, and a drain of the eleventh transistor is connected with the target column signal line.

[0049] In the possible implementation, the first imaginary part bit data on each second row signal line is transferred to the target column signal line through a transistor.

[0050] In a possible implementation of the first aspect, the imaginary part processing circuit or the real part processing circuit includes a digital post-processing circuit and m analog-to-digital conversion circuits, the digital post-processing circuit is connected with the m analog-to-digital conversion circuits, and each analog-to-digital conversion circuit is connected with a column signal line.

[0051] Each analog-to-digital conversion circuit includes a switch, a capacitor, a power supply, and an analog-to-digital converter; a fixed terminal of the switch is connected with one end of the capacitor, a movable terminal of the switch is connected with the power supply or the corresponding column signal line, the other end of the capacitor is connected with an analog signal input terminal of the analog-to-digital converter, a digital signal output terminal of the analog-to-digital converter is connected with the digital post-processing circuit, and the analog-to-digital converter is configured to convert the first product result or the second product result in the analog signal state into a digital signal and transmit the digital signal to the digital post-processing circuit.

[0052] In the possible implementation, an analog-to-digital converter (ADC) is arranged on each analog-to-digital conversion circuit, and after the analog signal on the corresponding column signal line is converted into a digital signal on each analog-to-digital conversion circuit, the digital post-processing circuit performs accumulation operation.

[0053] In a possible implementation of the first aspect, the imaginary part processing circuit or the real part processing circuit includes a digital post-processing circuit, an analog-to-digital converter, and m capacitor circuits, the digital post-processing circuit is connected with the m capacitor circuits, and each capacitor circuit is connected with a column signal line.

[0054] Each capacitor circuit includes a switch, a capacitor, and a power supply; a fixed terminal of the switch is connected with one end of the capacitor, a movable terminal of the switch is connected with the power supply or the corresponding column signal line, the other end of the capacitor is connected with an analog signal input terminal of the analog-to-digital converter, a digital signal output terminal of the analog-to-digital converter is connected with the digital post-processing circuit, and the analog-to-digital converter is configured to convert the accumulation result of the first product result or the accumulation result of the second product result in the analog signal state into a digital signal and transmit the digital signal to the digital post-processing circuit.

[0055] In the possible implementation manner, the analog signals on the m capacitive circuits are collected to an ADC, and the collected analog signals are converted into digital signals by the ADC. In this way, the number of ADCs can be reduced, and the area of the storage-computing integrated circuit can be further reduced.

[0056] In a possible implementation manner of the first aspect, the digital post-processing circuit in the real part processing circuit further receives a compensation digital signal from an analog-to-digital conversion circuit of the compensation circuit.

[0057] In the possible implementation manner, the compensation circuit is also configured with an analog-to-digital conversion circuit, and after the compensation circuit converts the analog signal into a digital signal, the digital signal is transmitted to the digital post-processing circuit of the real part processing circuit for accumulation operation.

[0058] The second aspect of the present application provides a chip system, which comprises a storage-computing integrated circuit and a peripheral circuit, wherein the storage-computing integrated circuit is connected with the peripheral circuit, and the storage-computing integrated circuit is the storage-computing integrated circuit in the first aspect or any possible implementation manner of the first aspect.

[0059] The third aspect of the present application provides an electronic device, which comprises the storage-computing integrated circuit in the first aspect or any possible implementation manner of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0060] Figure 1 FIG. 1 is a structural schematic diagram of a storage-computing integrated circuit provided by an embodiment of the present application;

[0061] Figure 2A FIG. 2 is a structural schematic diagram of a storage-computing unit provided by an embodiment of the present application;

[0062] Figure 2B FIG. 3 is a structural schematic diagram of a storage-computing unit provided by an embodiment of the present application;

[0063] Figure 3 FIG. 4 is another structural schematic diagram of a storage-computing unit provided by an embodiment of the present application;

[0064] Figure 4 FIG. 5 is a structural schematic diagram of a first storage unit in a storage-computing unit provided by an embodiment of the present application;

[0065] Figures 5A to 5D FIG. 6 is a structural schematic diagram of four LCCs in a storage-computing unit provided by an embodiment of the present application;

[0066] Figure 6 FIG. 7 is another structural schematic diagram of a storage-computing integrated circuit provided by an embodiment of the present application;

[0067] Figure 7 FIG. 8 is a circuit structural schematic diagram for connecting a compensation circuit and a second row signal line provided by an embodiment of the present application;

[0068] Figure 8 is another structural schematic diagram of the storage-computing integrated circuit provided by an embodiment of the present application.

[0069] Figure 9 is a structural schematic diagram of the real part processing circuit provided by an embodiment of the present application.

[0070] Figure 10 is another structural schematic diagram of the real part processing circuit provided by an embodiment of the present application.

[0071] Figure 11 is another structural schematic diagram of the storage-computing integrated circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0072] The embodiments of the present application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Those skilled in the art can know that with the development of technology and the emergence of new scenes, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0073] The terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0074] The embodiments of the present application provide a complex multiply-accumulate calculation that realizes storage and computing integration with smaller area and power consumption. The embodiments of the present application also provide a corresponding chip and electronic device. The following are described in detail respectively.

[0075] In the embodiments of the present application, the storage-computing integrated circuit refers to integrating a computing circuit in a storage circuit to realize storage and computing integration. The storage-computing integrated circuit can be applicable to complex number operation or real number operation. The storage-computing unit is used to realize the calculation process of multiplying two complex numbers, and the MAC processing circuit is used to realize the accumulation process of the calculation results of multiple storage-computing units.

[0076] In the embodiments of the present application, the storage-computing integrated circuit can be any form of bit array structure memory, such as a register, a random access memory (RAM), and the like. The random access memory includes a static random access memory (SRAM), an embedded dynamic random access memory (EDRAM), and the like.

[0077] The structure of the storage-computing integrated circuit provided in the embodiments of the present application can be referred to Figure 1 for understanding. As shown in the figure, Figure 1 The structure of the storage-computing integrated circuit includes a storage-computing array 10 and a data processing circuit 20. The storage-computing array 10 includes at least one storage-computing sub-array 101, wherein each storage-computing sub-array includes n*m storage-computing units 1011 arranged in n rows and m columns, and the data processing circuit 20 includes at least one multiplication-and-accumulation (MAC) processing circuit 201. The at least one storage-computing sub-array 101 corresponds to the at least one MAC processing circuit 201 one by one, and N and M are integers greater than 1. Each storage-computing unit 1011 is connected to a group of row signal lines and a group of column signal lines. A group of row signal lines is connected to m storage-computing units 1011 located in the same row, a group of column signal lines is connected to n storage-computing units 1011 located in the same column, and the storage-computing sub-array 101 where the n storage-computing units 1011 are located corresponds to a target MAC processing circuit 201.

[0078] Each storage-computing unit 1011 is configured to receive first real part bit data and first imaginary part bit data of a first complex number from the connected group of row signal lines, and perform operations with second real part bit data of a second complex number and related data of target bit data to obtain a first product result and a second product result. The second real part bit data and the target bit data are stored in the storage-computing unit. The target bit data includes the second imaginary part bit data or inverse data of the second imaginary part bit data, and the related data of the target bit data includes the second imaginary part bit data and inverse data of the second imaginary part bit data.

[0079] The target MAC processing circuit 201 is configured to receive a plurality of first product results and a plurality of second product results from the connected m groups of column signal lines, and accumulate the plurality of first product results to obtain first output data and accumulate the plurality of second product results to obtain second output data.

[0080] In the embodiments of the present application, the first complex number can also be referred to as a first operand, and the second complex number can also be referred to as a second operand. The first complex number can be represented as x r+x i i, where x r is a real part of the first complex number, and x i is an imaginary part of the first complex number. The second complex number can be represented as w r +w i i, where w r is a real part of the second complex number, and w i is an imaginary part of the second complex number. The first real part bit data can be bit data of different significant bits of the real part of the first complex number after binary conversion, such as x r,1 …x r,b . The first imaginary part bit data can be bit data of different significant bits of the imaginary part of the first complex number after binary conversion, such as x i,1 …x i,b . The second real part bit data can be bit data of different significant bits of the real part of the second complex number after binary conversion, such as w r,1 …w r,m . The second imaginary part bit data can be bit data of different significant bits of the imaginary part of the second complex number after binary conversion, such as w i,1 …w i,m . The inverse data of the second imaginary part bit data refers to data obtained by taking inverse of the second imaginary part bit data, such as where subscript r represents a real part, subscript i represents an imaginary part, subscript b represents a bit width of the first complex number, and subscript m represents a bit width of the second complex number.

[0081] It should be noted that in the embodiments of the present application, the first real part bit data, the first imaginary part bit data, the second real part bit data, the second imaginary part bit data, and the inverse data of the second imaginary part bit data can all be analog signals represented by a level. The real part of the first complex number refers to a numerical value of the real part of the first complex number, the imaginary part of the first complex number refers to a numerical value of the imaginary part of the first complex number, the real part of the second complex number refers to a numerical value of the real part of the second complex number, and the imaginary part of the second complex number refers to a numerical value of the imaginary part of the second complex number.

[0082] In the embodiments of the present application, the first product result refers to a product result containing an imaginary number after multiplication, such as x r,p ·w i,q and x i,p ·w r,q , and the second product result refers to a product result not containing an imaginary number after multiplication, such as x r,p ·w r,q and p is any numerical value in 1…b, and q is any numerical value in 1…m.

[0083] In the embodiments of the present application, the first output data can be a plurality of (x r,p ·wi,q +x i,p ·w r,q ) of the accumulation result, the second output data can be the accumulation result of a plurality of ) of the accumulation result.

[0084] As can be known from the embodiment, the second imaginary bit data w i,q or the inverse data of the second imaginary bit data The second imaginary bit data and the inverse data of the second imaginary bit data can be obtained by negation of each other, so that when the complex multiplication operation is performed, the second imaginary bit data and the inverse data of the second imaginary bit data can be directly used for multiplication operation, and only one copy of the real part and the imaginary part of the second complex number is stored to complete the multiplication and accumulation operation of two complex numbers, without storing two copies of the positive real part of the second complex number, one copy of the positive imaginary part of the second complex number, and one copy of the negative imaginary part of the second complex number, thereby effectively reducing the size of the storage and calculation integrated circuit, reducing power consumption, not needing to calculate two copies of data, and improving calculation efficiency.

[0085] The structure of the storage and calculation unit 1011 in the embodiment shown in the above Figure 1 may be understood with reference to Figure 2A . As shown in Figure 2A , the storage and calculation unit 1011 can include a first calculation unit 10111, a second calculation unit 10112, a third calculation unit 10113, a fourth calculation unit 10114, a first storage unit 10115, and a second storage unit 10116. The first storage unit 10115 is connected to the first calculation unit 10111 and the third calculation unit 10113, and the second storage unit 10116 is connected to the second calculation unit 10112 and the fourth calculation unit 10114.

[0086] At least one first row signal line in a group of row signal lines is connected to the first calculation unit 10111 and the fourth calculation unit 10114, and at least one second row signal line is connected to the second calculation unit 10112 and the third calculation unit 10113. A first column signal line in a group of column signal lines is connected to the first calculation unit 10111 and the second calculation unit 10112, and a second column signal line is connected to the third calculation unit 10113 and the fourth calculation unit 10114.

[0087] The first storage unit 10115 is configured to store target bit data, and the second storage unit 10116 is configured to store second real bit data. The target bit data and the second real bit data can be preconfigured in the first storage unit 10115 and the second storage unit 10116, and of course, the data stored in the first storage unit 10115 and the second storage unit 10116 can be updated according to the requirements of different application scenarios.

[0088] The first storage unit 10115 is configured to output the second imaginary part bit data to the first calculation unit 10111 and output the inverse data of the second imaginary part bit data to the third calculation unit 10113, and the second storage unit 10116 is configured to output the second real part bit data to the second calculation unit 10112 and the fourth calculation unit 10114.

[0089] The first calculation unit 10111 is configured to calculate the product of the first real part bit data and the second imaginary part bit data, the second calculation unit 10112 is configured to calculate the product of the first imaginary part bit data and the second real part bit data, the third calculation unit 10113 is configured to calculate the product of the first imaginary part bit data and the inverse data of the second imaginary part bit data, and the fourth calculation unit 10114 is configured to calculate the product of the first real part bit data and the second real part bit data.

[0090] The first product result includes the product of the first real part bit data and the second imaginary part bit data and the product of the first imaginary part bit data and the second real part bit data, and the second product result includes the product of the first real part bit data and the second real part bit data and the product of the first imaginary part bit data and the inverse data of the second imaginary part bit data.

[0091] The above Figure 2A The first row signal line and the second row signal line are included in the group of row signal lines, in fact, the first row signal line can have one or more, and the second row signal line can also have one or more, no matter how many the first row signal line or the second row signal line, each first row signal line is connected to the first calculation unit 10111 and the fourth calculation unit 10114 respectively, and inputs the first real part bit data x r,p Each second row signal line is connected to the second calculation unit 10112 and the third calculation unit 10113 respectively, and inputs the first imaginary part bit data x i,p The difference is that the first real part bit data on different first row signal lines can be different, and the first imaginary part bit data on different second row signal lines can be different.

[0092] The following Figure 2B Taking two first row signal lines and two second row signal lines as an example, the connection relationship between each first row signal line and each second row signal line and the first calculation unit 10111 to the fourth calculation unit 10114 is shown.

[0093] As Figure 2BAs shown, the two first row signal lines are connected to the first computing unit 10111 and the fourth computing unit 10114 respectively, and the two second row signal lines are connected to the second computing unit 10112 and the third computing unit 10113 respectively.

[0094] The first to fourth computing units in the in-memory computing unit can be local computing cells (LCCs). The first computing unit 10111 to the fourth computing unit 10114 can be respectively used... Figure 3 The LCC1, LCC2, LCC3, and LCC4 shown indicate that the first storage cell stores w. i,q or The second storage unit stores w r,q The first storage unit inputs w into LCC1. i,q Input to LCC3 The second storage unit inputs w to LCC2 and LCC4 respectively. r,q LCC1 receives x from the first line of signal lines. r,p Then calculate x r,p with w i,q The product x r,p ·w i,q LCC2 receives x from the second line of signal lines. i,p Then calculate x i,p with w r,q The product x i,p ·w r,q LCC3 receives x from the second line of signal lines. i,p Then calculate x i,p and product LCC4 receives x from the first line of signal lines. r,p Then calculate x r,p with w r,q The product x r,p ·w r,q Then, LCC1 transmits x to the target MAC processing circuit through the first column of signal lines. r,p ·w i,q LCC1 transmits x to the target MAC processing circuit through the first column of signal lines. i,p ·w r,q LCC3 transmits data to the target MAC processing circuit via the second column of signal lines. LCC4 transmits x to the target MAC processing circuit via the second column of signal lines. r,p ·w i,q .

[0095] From the above Figure 2A , Figure 2B and Figure 3As can be known from the description of the corresponding embodiments, the connection wire mode between the row signal line, the column signal line and the four LCCs in the storage and calculation unit and the wire mode between the storage unit and the four LCCs can simplify the circuit connection and optimize the circuit structure of the storage and calculation unit, and storing one copy of the real part bit data and the imaginary part bit data of the second complex number in the two storage units can realize the multiplication of two complex numbers, effectively reducing the size of the storage and calculation integrated circuit.

[0096] Figure 2A 、 Figure 2B or Figure 3 The structure of the first storage unit shown in Figure 4 may be understood with reference to Figure 4 . As shown in the figure, the first storage unit includes a first transistor T1 and a second transistor T2, and a first inverter S1 and a second inverter S2. The first inverter S1 and the second inverter S2 can generate complementary inverted signals, and two inverters are usually included in an SRAM. Similarly, for a register or Latch type memory, since the data holding node thereof usually also includes two inverters, complementary inverted signals can be generated. In a non-complementary signal memory (such as a DRAM or eDRAM), an inverter needs to be additionally provided to generate an inverted signal, which is used to implement the multiplication and accumulation calculation. It should be noted that in the embodiments of the present application, the inverted signal can also be replaced by inverted data.

[0097] The gate of the first transistor T1 and the gate of the second transistor T2 are connected to a word line (WL), which is used to activate the first transistor and the second transistor. The source of the first transistor T1 is connected to the input end of the first inverter S1 or the output end of the second inverter S2, and the drain of the first transistor T1 is connected to a first bit line (BL).

[0098] The source of the second transistor T2 is connected to a second bit line BLB, and the drain of the second transistor T2 is connected to the output end of the first inverter S1 or the input end of the second inverter S2.

[0099] When the target bit data is the second imaginary part bit data w i,q , the first inverter S1 is used to convert the second imaginary part bit data stored between the source of the first transistor T1 and the input end of the first inverter S1 into inverted data of the second imaginary part bit data and output to the second transistor T2; the first bit line and the second bit line are used to read or write the second imaginary part bit data w i,q from the first storage unit and read or write the second real part bit data w r,q from the second storage unit.

[0100] When the target bit data is the inverse data of the second imaginary part bit data : the second inverter S2 is used to convert the inverse data of the second imaginary part bit data stored between the drain of the second transistor T2 and the input terminal of the second inverter S2 into the second imaginary part bit data w i,q , and output to the first transistor T1; the first bit line and the second bit line are used to read or write the second imaginary part bit data w i,q from the first storage unit and the second real part bit data w r,q from the second storage unit.

[0101] In this embodiment, the first storage unit in the storage and calculation unit can be realized by two transistors and one or two inverters to quickly and effectively obtain the other party in the case of storing one second imaginary part bit data or its inverse data, so as to realize the complex multiplication and accumulation operation with a smaller volume of circuit.

[0102] Figure 3 The structure of LCC1 to LCC4 shown in the above embodiment can be understood by referring to Figures 5A to 5D .

[0103] As shown in the structure of LCC1 Figure 5A , LCC1 includes a third transistor T3 and a fourth transistor T4, the gate of the third transistor T3 is connected with the first storage unit to receive the second imaginary part bit data w i,q from the first storage unit, the source of the third transistor T3 is grounded, the drain of the third transistor T3 is connected with the source of the fourth transistor T4, the gate of the fourth transistor T4 is connected with the first row signal line to receive the first real part bit data x r,p from the first row signal line, and the drain of the fourth transistor T4 is connected with the first column signal line to output x r,p ·w i,q .

[0104] As shown in the structure of LCC2 Figure 5B , LCC2 includes a fifth transistor T5 and a sixth transistor T6, the gate of the fifth transistor T5 is connected with the second storage unit to receive the second real part bit data w r,q from the second storage unit, the source of the fifth transistor T5 is grounded, the drain of the fifth transistor T5 is connected with the source of the sixth transistor T6, the gate of the sixth transistor T6 is connected with the second row signal line to receive the first imaginary part bit data x i,p from the second row signal line, and the drain of the sixth transistor T6 is connected with the first column signal line to output x i,p ·w r,q .

[0105] As​Figure 5C The LCC3 structure shown includes a seventh transistor T7 and an eighth transistor T8. The gate of the seventh transistor T7 is connected to the first memory cell and receives the inverted data of the second imaginary bit data from the first memory cell. The source of the seventh transistor T7 is grounded, and its drain is connected to the source of the eighth transistor T8. The gate of the eighth transistor T8 is connected to the second row of signal lines, and it receives the first imaginary bit data x from the second row of signal lines. i,p The drain of the eighth transistor T8 is connected to the second column of signal lines, and outputs to the second column of signal lines.

[0106] like Figure 5D The LCC4 structure shown includes a ninth transistor T9 and a tenth transistor T10. The gate of the ninth transistor T9 is connected to the second memory cell and receives the second real part bit data w from the second memory cell. r,q The source of the ninth transistor T9 is grounded, the drain of the ninth transistor T9 is connected to the source of the tenth transistor T10, and the gate of the tenth transistor T10 is connected to the first row of signal lines, receiving the first real part bit data x from the first row of signal lines. r,p The drain of the tenth transistor is connected to the second column of signal lines, outputting x to the second column of signal lines. r,p ·w r,q .

[0107] It should be noted that the connection relationships between the source and drain of the third to tenth transistors mentioned above can be interchanged with those of other devices, and the positional relationships described above are not limited.

[0108] In this possible implementation, each of the four LCCs can include two transistors, through which the multiplication operation is performed and the product result is transmitted on the column signal line.

[0109] Optionally, such as Figure 6 As shown, the target MAC processing circuit includes an imaginary part processing circuit 2011 and a real part processing circuit 2012. The imaginary part processing circuit 2011 is connected to m first column signal lines, and the real part processing circuit 2012 is connected to m second column signal lines.

[0110] The virtual part processing circuit 2011 is used to receive the first product result from the storage unit of each column through each first column signal line, and accumulate multiple first product results from the same column to obtain the first column accumulation result. Then, it performs a weighted operation on the first column accumulation results of different columns, and then accumulates the first column accumulation results of different columns after the weighted operation to obtain the first output data.

[0111] The real part processing circuit 2012 is used to calculate the second product result received from the storage unit of each column through each second column signal line, and to accumulate multiple second product results from the same column to obtain the second column accumulation result. Then, the second column accumulation results of different columns are weighted and then the weighted second column accumulation results of different columns are accumulated to obtain the second output data.

[0112] Optionally, the data processing circuit further includes a compensation circuit 203, one end of which is connected to N second row signal lines via a target column signal line, and the other end is connected to the real part processing circuit 2012 in each of the at least one MAC processing circuits 201.

[0113] The compensation circuit 203 is used to receive multiple first imaginary bit data from N second row signal lines, accumulate the multiple first imaginary bit data, and transmit the accumulation result of the multiple first imaginary bit data to the real part processing circuit.

[0114] The real part processing circuit 2012 is used to sum the accumulated result of multiple first imaginary bit data with the second output data to obtain the third output data.

[0115] The target column signal line and the second row signal line can be connected via an eleventh transistor. The gate of the eleventh transistor is connected to the second row signal line, the source of the eleventh transistor is grounded, and the drain of the eleventh transistor is connected to the target column signal line. The connection relationship between the target signal line and the eleventh transistor can be found in [reference needed]. Figure 7 To understand, such as Figure 7 As shown, the second row of signal lines is connected to the gate of the eleventh transistor T11, the source of T11 is grounded, and the drain of T11 is connected to the target column signal line.

[0116] To better understand the above-mentioned in-memory computing circuit, the following will combine... Figure 8 This paper describes the multiplication and accumulation operation process of complex numbers by this in-memory computing circuit.

[0117] like Figure 8 As shown, in the data preparation stage, the real and imaginary parts of the second complex number with a bit width of m are converted into binary values ​​to obtain m imaginary bits and real bits arranged from the least significant bit to the most significant bit in two's complement form. Figure 8 The imaginary bit data and real bit data on the same row shown are arranged from low bit to high bit, or they can be arranged from high bit to low bit. This application does not limit the arrangement.

[0118] In the embodiments of this application, the n second complex numbers w r +w iThe form of the imaginary part bit data and the real part bit data after the binary conversion can be understood with reference to Table 1 below.

[0119] Table 1: Imaginary part bit data and real part bit data of n second complex numbers

[0120]

[0121] In Figure 8 In the storage-computation integrated circuit shown, in the same row of storage-computation units, the same dimension of real part bit data and imaginary part bit data are stored, for example: w1 i,1 , w1 r,1 is stored in the first storage-computation unit in the first row, w1 i,2 , w1 r,2 is stored in the second storage-computation unit in the same row, …, w1 i,m , w1 r,m is stored in the mth storage-computation unit in the same row. w2 i,1 , w2 r,1 is stored in the first storage-computation unit in the second row, w2 i,2 , w2 r,2 is stored in the second storage-computation unit in the same row, …, w2 i,m , w2 r,m is stored in the mth storage-computation unit in the same row. wn i,1 , wn r,1 is stored in the first storage-computation unit in the nth row, wn i,2 , wn r,2 is stored in the second storage-computation unit in the same row, …, wn i,m , wn r,m is stored in the mth storage-computation unit in the same row. That is, the m storage-computation units in the same row are used to store the bit data of different significant bits of the real part and the imaginary part of the second complex number after the binary conversion. From Table 1 above and Figure 8 It can also be seen that the n storage-computation units in the same column are used to store the bit data of the same significant bit of different second complex numbers.

[0122] The imaginary part bit data in Table 1 can be understood as the second imaginary part bit data in the foregoing embodiments, and the real part bit data is the second real part bit data in the foregoing embodiments.

[0123] Table 1 lists the case of storing the second imaginary part bit data in the storage-computation unit. Actually, the second imaginary part bit data can also be replaced with inverted data of the second imaginary part bit data, for example: w1 is replaced with wn i,m . This case is not specifically expanded here, and can be referred to and wn i,mThe anti-correlation relationship between n and m can be understood.

[0124] The representation of the real part bit data and the imaginary part bit data of the first complex number with bit width b as the input signal can be understood with reference to Table 2.

[0125] Table 2: Imaginary part bit data and real part bit data of n first complex numbers

[0126]

[0127] The imaginary part bit data in Table 1 can be understood as the first imaginary part bit data in the foregoing embodiment, and the real part bit data is the first real part bit data in the foregoing embodiment.

[0128] In the multiplication accumulation calculation process, in the first row, x1 r,1 …x1 r,b is input to each storage and calculation unit through the second signal line in turn. i,1 …x1 i,b In the second row, x2 r,1 …x2 r,b is input to each storage and calculation unit through the first signal line in turn, and x2 i,1 …x2 i,b is input to each storage and calculation unit through the second signal line in turn. r,1 …xn r,b In the nth row, xn i,1 …xn i,b is input to each storage and calculation unit through the first signal line in turn, and xn r,b …xn i,b is input to each storage and calculation unit through the second signal line in turn.

[0129] After the first imaginary part bit data and the first real part bit data of the first complex number are input into the storage and calculation unit, the storage and calculation unit performs multiplication operation on the first imaginary part bit data and the first real part bit data of the first complex number, the second imaginary part bit data, the second real part bit data of the second complex number, and the inverse data of the second imaginary part bit data. The specific operation process can be understood with reference to the process described in Figure 3 , for example: the multiplication process of xn r,b , xn i,b , wn r,m , wn i,m , The multiplication of these bit data will obtain the following products: xn r,b ·wn i,m , xn i,b ·wn r,m , xn r,b ·wn r,mThen, xn r,b ·wn i,m , xn i,b ·wn r,m , through the second column signal line to the real part processing circuit 2012 transmission xn r,b ·wn r,m .

[0130] The imaginary part processing circuit 2011 will be received by the first column signal line to each storage and calculation unit product result of the accumulation, the real part processing circuit 2012 will be received by the second column signal line to each storage and calculation unit product result of the accumulation.

[0131] The accumulation process in the imaginary part processing circuit 2011 can be first accumulated in the same column of the first product result, to get the first column accumulation result, then the weighted operation is carried out on the first column accumulation result of different columns, and then the first column accumulation result of different columns after the weighted operation is accumulated to get the first output data. The process can be represented by the formula:

[0132]

[0133] The formula represents the first column accumulation result of the first complex number in the bth significant bit data in the mth column. The formula of the accumulation of the first column accumulation result of different columns after the weighted operation can be represented as:

[0134]

[0135] The accumulation process in the real part processing circuit 2012 can be first accumulated in the same column of the second product result, to get the second column accumulation result, then the weighted operation is carried out on the second column accumulation result of different columns, and then the second column accumulation result of different columns after the weighted operation is accumulated to get the second output data. The process can be represented by the formula:

[0136]

[0137] The accumulation result in the compensation circuit 203 can be represented by the formula:

[0138]

[0139] The two formulas represent the second column accumulation result of the first complex number in the bth significant bit data in the mth column. The formula of the accumulation of the second column accumulation result of different columns after the weighted operation can be represented as:

[0140]

[0141]

[0142] The weight coefficient c in the above formula m,b = c m · c b , wherein

[0143]

[0144]

[0145] The third output data y r = y′ r + y″ r .

[0146] The structure of the imaginary part processing circuit 2011 or the real part processing circuit 2012 can be understood with reference to the real part processing circuit shown in Figure 9 or Figure 10 .

[0147] As shown in Figure 9 , the real part processing circuit 2012 includes a digital post-processing circuit 20121 and m analog-to-digital conversion circuits 20122, the digital post-processing circuit 20121 is connected with the m analog-to-digital conversion circuits 20122, and each analog-to-digital conversion circuit 20122 is connected with a column signal line.

[0148] Each analog-to-digital conversion circuit 20122 includes a switch K, a capacitor C, a power supply VDD and an analog-to-digital converter (ADC); one end of the switch K is connected with one end of the capacitor C, the movable end of the switch K is connected with the power supply VDD or the corresponding column signal line; the other end of the capacitor C is connected with the analog signal input end of the analog-to-digital converter ADC; the digital signal output end of the analog-to-digital converter ADC is connected with the digital post-processing circuit 20121; and the analog-to-digital converter ADC is used to convert the second product result in the analog signal state into a digital signal and transmit it to the digital post-processing circuit 20121.

[0149] The digital post-processing circuit 20121 also receives the compensation digital signal of the analog-to-digital conversion circuit from the compensation circuit.

[0150] The digital post-processing circuit 20121 performs the accumulation operation according to the accumulation process in the foregoing embodiment to obtain the third output data.

[0151] The Figure 9 , if it is an imaginary part processing circuit, only the compensation circuit needs to be removed, and other parts can be understood with reference to the real part processing circuit shown in Figure 9 .

[0152] As shown in Figure 10As shown, the real part processing circuit 2012 includes a digital post-processing circuit 20121, an analog-to-digital converter (ADC), and m capacitor circuits 20123. The digital post-processing circuit 20121 is connected to the m capacitor circuits 20123, and each capacitor circuit 20123 is connected to a column signal line.

[0153] Each capacitor circuit 20123 includes a switch K, a capacitor C, and a power supply VDD; the stationary terminal of switch K is connected to one end of capacitor C, and the moving terminal of switch K is connected to the power supply VDD or the corresponding column signal line; the other end of capacitor C is connected to the analog signal input terminal of analog-to-digital converter (ADC); the digital signal output terminal of ADC is connected to digital post-processing circuit 20121; ADC is used to convert the accumulation result of the second product in analog signal state into a digital signal and transmit it to digital post-processing circuit 20121.

[0154] The digital post-processing circuit 20121 performs an accumulation operation according to the accumulation process in the aforementioned embodiment to obtain the first output data.

[0155] Should Figure 10 The circuit shown is for processing the real part. For processing the imaginary part, simply remove the compensation circuit. Other parts can be found in [reference needed]. Figure 10 The real part processing circuit shown is explained.

[0156] Depend on Figure 9 and Figure 10 The comparison shows that the analog signals from m capacitor circuits are aggregated into one ADC, and then converted into digital signals by this ADC. This reduces the number of ADCs and further reduces the area of ​​the in-memory computing circuit.

[0157] Optionally, such as Figure 11 As shown, in addition to the aforementioned components, the in-memory computing circuit may also include a data input driver interface, a row input driver circuit, a control circuit, a column output driver and processing circuit, and a data processing driver interface.

[0158] Data input and data output interfaces are used to enable digital communication between the in-memory computing circuit and other modules of the chip system.

[0159] Row input drive circuit: provides N sets of row input signals required for the memory array to perform operations, and controls the corresponding voltage or current amplitude, signal pulse width and other parameters according to the data input control signal.

[0160] Column output drive and processing circuit: Provides the column drive signals required for the operation of the memory array, and further processes the column calculation output signals of the memory array to obtain the complete multiplication and accumulation operation results.

[0161] Control circuit: including clock and other circuits, control the above function modules with corresponding timing.

[0162] In the embodiments of the present application, a chip system is also provided, which comprises a memory-computing integrated circuit and a peripheral circuit, the memory-computing integrated circuit is connected with the peripheral circuit, and the memory-computing integrated circuit is any of the memory-computing integrated circuits of the optional structures described above.

[0163] In the embodiments of the present application, an electronic device is also provided, which comprises any of the memory-computing integrated circuits of the optional structures described above.

[0164] The electronic device can be a terminal device, a server or a virtual machine.

[0165] The above is only a specific implementation manner of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto.

Claims

1. An in-memory computing circuit, comprising: The memory-computing integrated circuit comprises a memory-computing array and a data processing circuit, the memory-computing array comprises at least one memory-computing sub-array, each memory-computing sub-array comprises n*m memory-computing units arranged in n rows and m columns, the data processing circuit comprises at least one multiply-accumulate (MAC) processing circuit, the at least one memory-computing sub-array corresponds to the at least one MAC processing circuit one by one, and n and m are integers greater than 1; Each memory-computing unit is connected to a group of row signal lines and a group of column signal lines, the group of row signal lines is connected to m memory-computing units in the same row, the group of column signal lines is connected to n memory-computing units in the same column, and the memory-computing sub-array where the n memory-computing units are located corresponds to a target MAC processing circuit; The memory-computing unit is configured to receive first real part bit data and first imaginary part bit data of a first complex number from the connected group of row signal lines, and perform operations on second real part bit data of a second complex number and related data of target bit data to obtain a first product result and a second product result, the second real part bit data and the target bit data are stored in the memory-computing unit, the target bit data comprises second imaginary part bit data or inverse data of the second imaginary part bit data, and the related data of the target bit data comprises the second imaginary part bit data and inverse data of the second imaginary part bit data; The target MAC processing circuit is configured to receive a plurality of the first product results and a plurality of the second product results from the connected m groups of column signal lines, accumulate the plurality of the first product results to obtain first output data, and accumulate the plurality of the second product results to obtain second output data; The memory-computing unit comprises a first calculation unit, a second calculation unit, a third calculation unit, a fourth calculation unit, a first storage unit, and a second storage unit; The first storage unit is connected to the first calculation unit and the third calculation unit, and the second storage unit is connected to the second calculation unit and the fourth calculation unit; At least one first row signal line in the group of row signal lines is connected to the first calculation unit and the fourth calculation unit, at least one second row signal line is connected to the second calculation unit and the third calculation unit, a first column signal line in the group of column signal lines is connected to the first calculation unit and the second calculation unit, and a second column signal line is connected to the third calculation unit and the fourth calculation unit; The first storage unit is configured to store the target bit data, and the second storage unit is configured to store the second real part bit data; if the target bit data is the second imaginary part bit data, the first storage unit is configured to output inverse data of the second imaginary part bit data after taking inverse of the second imaginary part bit data, and if the target bit data is the inverse data of the second imaginary part bit data, the first storage unit is configured to output the second imaginary part bit data after taking inverse of the inverse data of the second imaginary part bit data.

2. The memory-computing integrated circuit of claim 1, wherein The first storage unit is configured to output the second imaginary part bit data to the first calculation unit and output inverted data of the second imaginary part bit data to the third calculation unit; The second storage unit is configured to output the second real part bit data to the second calculation unit and the fourth calculation unit; The first calculation unit is configured to calculate a product of the first real part bit data and the second imaginary part bit data; The second calculation unit is configured to calculate a product of the first imaginary part bit data and the second real part bit data; The third calculation unit is configured to calculate a product of the first imaginary part bit data and the inverted data of the second imaginary part bit data; The fourth calculation unit is configured to calculate a product of the first real part bit data and the second real part bit data; The first product result includes the product of the first real part bit data and the second imaginary part bit data and the product of the first imaginary part bit data and the second real part bit data, and the second product result includes the product of the first real part bit data and the second real part bit data and the product of the first imaginary part bit data and the inverted data of the second imaginary part bit data.

3. The storage and computing integrated circuit of claim 1, wherein, The target MAC processing circuit includes an imaginary part processing circuit and a real part processing circuit, the imaginary part processing circuit is connected with m first column signal lines, and the real part processing circuit is connected with m second column signal lines; The imaginary part processing circuit is configured to receive, through each of the first column signal lines, the first product result from the storage and calculation unit of each column, accumulate a plurality of first product results from the same column to obtain a first column accumulation result, perform weighted operation on the first column accumulation results of different columns, and then accumulate the first column accumulation results of different columns after the weighted operation to obtain the first output data; The real part processing circuit is configured to calculate the second product result received through each of the second column signal lines from the storage and calculation unit of each column, accumulate a plurality of second product results from the same column to obtain a second column accumulation result, perform weighted operation on the second column accumulation results of different columns, and then accumulate the second column accumulation results of different columns after the weighted operation to obtain the second output data.

4. The storage and computing integrated circuit of claim 3, wherein, The data processing circuit further includes a compensation circuit, one end of the compensation circuit is connected with N second row signal lines through a target column signal line, and the other end is connected with the real part processing circuit in each of the at least one MAC processing circuit; The compensation circuit is configured to receive a plurality of first imaginary part bit data from the N second row signal lines, accumulate the plurality of first imaginary part bit data, and transmit an accumulation result of the plurality of first imaginary part bit data to the real part processing circuit; The real part processing circuit is configured to perform summation operation on the accumulation result of the plurality of first imaginary part bit data and the second output data to obtain third output data.

5. The storage and computing integrated circuit of claim 4, wherein, The m storage and calculation units located in the same row are configured to store bit data of different significant bits after binary conversion of the real part and the imaginary part of the second complex number respectively; The n storage and calculation units in the same column are used for storing bit data of the same significant bit of different second complex numbers.

6. The storage and computing integrated circuit of claim 4, wherein, The first real part bit data of the first complex number comprises bit data of different significant bits after binary conversion of a real part of the first complex number. The first imaginary part bit data of the first complex number comprises bit data of different significant bits after binary conversion of an imaginary part of the first complex number.

7. The storage and computing integrated circuit of any one of claims 1-6, wherein, The first storage unit comprises a first transistor and a second transistor, and a first inverter or / and a second inverter. The gate of the first transistor and the gate of the second transistor are connected with a word line WL respectively, and the word line is used for activating the first transistor and the second transistor. The source of the first transistor is connected with the input end of the first inverter or the output end of the second inverter, and the drain of the first transistor is connected with a first bit line BL. The source of the second transistor is connected with a second bit line BLB, and the drain of the second transistor is connected with the output end of the first inverter or the input end of the second inverter. When the target bit data is the second imaginary part bit data: The first inverter is used for converting the second imaginary part bit data stored between the source of the first transistor and the input end of the first inverter into inverse data of the second imaginary part bit data, and outputting to the second transistor. The first bit line and the second bit line are used for reading or writing the second imaginary part bit data from the first storage unit and reading or writing the second real part bit data from the second storage unit. When the target bit data is inverse data of the second imaginary part bit data: The second inverter is used for converting the inverse data of the second imaginary part bit data stored between the drain of the second transistor and the input end of the second inverter into the second imaginary part bit data, and outputting to the first transistor. The first bit line and the second bit line are used for reading or writing the second imaginary part bit data from the first storage unit and reading or writing the second real part bit data from the second storage unit.

8. The storage and calculation integrated circuit according to any one of claims 1-6, wherein The first calculation unit comprises a third transistor and a fourth transistor, the gate of the third transistor is connected with the first storage unit to receive the second imaginary part bit data, the source of the third transistor is grounded, the drain of the third transistor is connected with the source of the fourth transistor, the gate of the fourth transistor is connected with the first row signal line, and the drain of the fourth transistor is connected with the first column signal line. The second calculation unit comprises a fifth transistor and a sixth transistor, the gate of the fifth transistor is connected with the second storage unit to receive the second real part bit data, the source of the fifth transistor is grounded, the drain of the fifth transistor is connected with the source of the sixth transistor, the gate of the sixth transistor is connected with the second row signal line, and the drain of the sixth transistor is connected with the first column signal line. The third calculation unit comprises a seventh transistor and an eighth transistor, the gate of the seventh transistor is connected with the first storage unit, the seventh transistor receives the inverted data of the second imaginary part bit data from the first storage unit, the source of the seventh transistor is grounded, the drain of the seventh transistor is connected with the source of the eighth transistor, the gate of the eighth transistor is connected with the second row signal line, and the drain of the eighth transistor is connected with the second column signal line; The fourth calculation unit comprises a ninth transistor and a tenth transistor, the gate of the ninth transistor is connected with the second storage unit, the ninth transistor receives the second real part bit data from the second storage unit, the source of the ninth transistor is grounded, the drain of the ninth transistor is connected with the source of the tenth transistor, the gate of the tenth transistor is connected with the first row signal line, and the drain of the tenth transistor is connected with the second column signal line.

9. The storage and computing integrated circuit of claim 4, wherein, The target column signal line is connected with the second row signal line through an eleventh transistor, the gate of the eleventh transistor is connected with the second row signal line, the source of the eleventh transistor is grounded, and the drain of the eleventh transistor is connected with the target column signal line.

10. The storage and computing integrated circuit of claim 4, wherein, The imaginary part processing circuit or the real part processing circuit comprises a digital post-processing circuit and m analog-to-digital conversion circuits, the digital post-processing circuit is connected with the m analog-to-digital conversion circuits, and each analog-to-digital conversion circuit is connected with a column signal line. Each analog-to-digital conversion circuit comprises a switch, a capacitor, a power supply and an analog-to-digital converter. The fixed end of the switch is connected with one end of the capacitor, and the movable end of the switch is connected with the power supply or the corresponding column signal line. The other end of the capacitor is connected with the analog signal input end of the analog-to-digital converter. The digital signal output end of the analog-to-digital converter is connected with the digital post-processing circuit. The analog-to-digital converter is used for converting the first product result or the second product result in an analog signal state into a digital signal and transmitting the digital signal to the digital post-processing circuit.

11. The storage and computing integrated circuit of claim 4, wherein, The imaginary part processing circuit or the real part processing circuit comprises a digital post-processing circuit, an analog-to-digital converter and m capacitor circuits, the digital post-processing circuit is connected with the m capacitor circuits, and each capacitor circuit is connected with a column signal line. Each capacitor circuit comprises a switch, a capacitor and a power supply. The fixed end of the switch is connected with one end of the capacitor, and the movable end of the switch is connected with the power supply or the corresponding column signal line. The other end of the capacitor is connected with the analog signal input end of the analog-to-digital converter. The digital signal output end of the analog-to-digital converter is connected with the digital post-processing circuit. The analog-to-digital converter is used for converting the accumulated result of the first product result or the accumulated result of the second product result in an analog signal state into a digital signal and transmitting the digital signal to the digital post-processing circuit.

12. The storage and computing integrated circuit according to claim 10 or 11, wherein, The digital post-processing circuit in the real part processing circuit also receives the compensation digital signal from the analog-to-digital conversion circuit of the compensation circuit.

13. A chip system, characterized by The storage and calculation integrated circuit of any one of claims 1-12. The storage and calculation integrated circuit of any one of claims 1-12.

14. An electronic device, comprising: ​

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