Layer allocation method based on multiple strategies and considering bus skew

Abstract

This invention proposes a multi-strategy layer allocation method considering bus deviation, including a priority allocation strategy based on congestion value in the initial layer allocation stage, a priority adjustment strategy based on bus deviation, and a layer swapping strategy based on bus deviation; the method includes the following steps: Step S1: In the layer allocation stage, the priority of each net is evaluated according to the congestion situation to obtain different layer allocation orders, and routing is performed according to the priority order; Step S2: For the routing results generated in the initial layer allocation stage, the bus deviation factor of the initial routing results is introduced into the evaluation of the routing priority adjustment order to adjust the layer allocation order of each net and optimize the timing matching of the routing results; Step S3: The bus deviation is calculated, and for nets with bus deviation, under the condition of a given number of track resources, the path that satisfies the timing matching of each net is found to optimize the bus deviation; This invention can effectively reduce the line length deviation of the bus, thereby obtaining a high-quality overall routing result.

Description

Technical Field

[0001] This invention relates to the technical field of overall routing design for very large-scale integrated circuits in computer-aided design of integrated circuits, and in particular to a multi-strategy layer allocation method that takes into account bus deviation. Background Technology

[0002] With the rapid development of the integrated circuit industry, the number of components that chips can accommodate is becoming increasingly larger, and the proportion of buses within the network is gradually increasing. The quality of bus routing directly affects the timing matching, routing efficiency, and other performance characteristics of the chip. At the same time, a single 2D metal layer structure can no longer meet the needs of routing design. Therefore, in current multi-layer routing designs, judging and optimizing bus deviations during the layer allocation stage can better meet the timing characteristics requirements of the chip and improve chip performance.

[0003] With the rapid development of VLSI technology, the technical complexity of the challenges in the routing phase of integrated circuit design is constantly increasing. Due to the massive scale of the routing, routing design typically employs two phases: the overall routing phase and the detailed routing phase. Overall routing is a crucial phase in the entire physical design, as its result determines the quality of subsequent detailed routing, thus impacting the overall physical design outcome. Furthermore, based on the multi-layered routing structures of current chip applications, an intermediate layer allocation phase is incorporated into the overall routing process as a transition to detailed routing. Specifically, the layer allocation algorithm, based on the 2D overall routing result, considers the routing hierarchy of net placement, assuming no overflow, to generate the layer allocation result, i.e., the 3D overall routing result. This result further serves as the foundation for subsequent phases, providing specific guidance for detailed routing.

[0004] The function of a bus is to transmit control signals or data in parallel to the corresponding functional modules. Modern manufacturing processes can integrate billions of components inside a chip, resulting in extremely high bus density as the chip gains more functionality. Therefore, it is of great significance to consider how to effectively unify the handling of bus deviations during the layer allocation stage, effectively reducing the probability of chip timing disorders, reduced routing efficiency, and excessive power consumption caused by excessive bus deviations, and better meeting design requirements.

[0005] During layer allocation routing, nets are routed according to a prescribed routing order. Since the routing resources for a circuit are limited, these resources gradually decrease as routing progresses. In other words, nets allocated earlier in the layer allocation process have more available routing resources, while subsequently allocated nets have fewer. This means the routing order of nets directly impacts the routing quality of layer allocation. Therefore, finding an appropriate layer allocation order before routing begins can improve the efficiency of routing resource utilization, resulting in the best layer allocation outcome. The net attributes selected by the priority algorithm will vary depending on the desired optimization objective. Summary of the Invention

[0006] This invention proposes a layer allocation method based on multiple strategies that takes into account bus deviation, which can effectively reduce bus length deviation and thus obtain a high-quality overall routing result.

[0007] The present invention adopts the following technical solution.

[0008] A multi-strategy layer allocation method considering bus deviation is used to reduce bus length deviation in routing design. The method includes a priority allocation strategy based on congestion value in the initial layer allocation stage, a priority adjustment strategy based on bus deviation, and a layer swapping strategy based on bus deviation; and includes the following steps.

[0009] Step S1: In the layer allocation stage, the priority of each net is evaluated according to the congestion situation to obtain different layer allocation orders, and routing is performed according to the priority order; when a better solution is obtained for the line length, a routing result with smaller bus deviation is also obtained.

[0010] Step S2: For the routing results generated in the initial layer allocation stage, the bus deviation factor of the initial routing results is introduced into the evaluation of the routing priority adjustment order, the layer allocation order of each net is adjusted, and the timing matching of the routing results is optimized.

[0011] Step S3: Calculate bus deviation. For nets with bus deviation, given the number of track resources, increase the length of shorter buses and decrease or keep the length of longer buses to find the path that satisfies timing matching for each net and optimize the bus deviation.

[0012] The layer allocation method is used for 2.5D global routing, which includes a 2D stage and a 3D stage. Based on the 2D routing scheme of the overall routing, the layer allocation stage allocates routing resources, finds a path without overflow in each net, and connects adjacent routing units located in different metal layers of each net through via edges to obtain a 3D routing scheme.

[0013] The method described above for calculating the line length is as follows:

[0014] Given G 0 =(V 0 E 0 ) represents a 2D wiring mesh diagram, where v 0 ∈V 0 For wiring units, e 0 ∈E 0 G is the connection edge between adjacent wiring units. 1 =(V 1 E 1 ) represents a 3D wiring diagram, where V 1 Same as V 0 For the edge of the through hole, E 0 For wiring edges;

[0015] Under the condition of satisfying the constraint rules and without changing the 2D routing result, each routing edge of the bus 2D routing result is assigned to a suitable routing layer in the 3D structure to complete the layer assignment work and obtain the 3D routing result. The 3D routing result has both a shorter bus length and an optimized bus deviation. The formula for the bus length is shown in Formula 1 below.

[0016]

[0017] Where l is the number of metal layers; V cost It is the cost of the via; r(e) is the number of track resources used for each wiring edge.

[0018] The 2.5D global routing includes the following process;

[0019] Process A1: Based on the 2D routing results, the priority order of net layer allocation is determined by comprehensively considering indicators such as congestion level, number of pins and line length. Based on the obtained priority order, the initial layer allocation routing result is obtained by using a layer allocation algorithm based on minimizing the number of vias, and the bus deviation is calculated.

[0020] In process A2, during the layer switching phase, which is the stage where routing resources are allocated, the first step is to determine if there is any deviation. If there is no bus deviation, the 3D routing result is obtained directly. If there is a bus deviation, all nets except those without bus deviation are disassembled.

[0021] Process A3: The priority order of net layer allocation is determined by a priority strategy that integrates bus deviation, pin count, and line length indicators. The obtained priority order is then used to obtain the layer allocation result through a layer allocation algorithm based on minimizing the number of vias. After obtaining the layer allocation result, it is determined whether bus deviation still exists. If it does, the shorter nets are given a certain line length, the routing layer is redistributed, and the routing status is updated. Then, for the longer nets with bus deviation, it is determined whether there is a better path selection, and finally the 3D routing result is obtained.

[0022] The priority allocation strategy based on congestion value in the initial layer allocation phase is as follows: A strategy of processing nets sequentially is adopted, that is, allocating appropriate metal layers to each net according to the allocation order. After each allocation of routing resources, the existing routing resource reserve needs to be updated to avoid actual routing overflow. Specifically, higher-priority nets receive better routing resources to optimize routing results, while lower-priority nets have fewer routing resources available for them. This is achieved by setting a priority function to optimize the routing resource allocation order. Specifically, for net Ni, when calculating its layer allocation priority, the bus length needs to be kept small while reducing bus deviation. The higher the net's order, the earlier the routing resources are allocated to net Ni and the routing results are obtained. The priority setting rule is that the higher the priority, the earlier the order.

[0023] The initial priority P1(Ni) is calculated as follows:

[0024]

[0025] Where pin_number(N) i ) represents the number of pins in the net Ni, and wirelength(N) i ) is N i The line length, congestion(N) i ) is N i The sum of congestion values, where α is the weighting factor.

[0026] When the sum of congestion (N) is used... i ) as the main component, and the comprehensive pin count pin_numer(N) i ), wirelength(N) i When the priority order is determined by multiple factors, the specific evaluation method is as follows: wirelength(N) i The more complex the 2D line length of a net, the more routing resources it requires. Even if the net is prioritized for routing resource allocation to obtain better routing resources, the probability of obtaining a good routing result is still not high. After allocating complex nets, the probability that nets with simpler topologies will need more routing resources to complete metal layer allocation due to insufficient resources is greatly increased, which may maliciously increase the bus length of the routing result. Therefore, the priority of nets with more complex 2D line lengths should be set as low as possible; pin_numer(N i The more pin pairs a net has, the more track resources it requires. For this type of net, if there are fewer routing resources available, the chance of the bus length increasing maliciously after layer allocation will be greatly increased, and it will be difficult to obtain a timing-matching solution. Therefore, a higher priority should be set for bus nets with more pin pairs.

[0027] congestion(N i The higher the congestion level of a network, the more cabling edge and track resources are required. Even if the network can prioritize the cabling layer, it will still waste cabling resources. Therefore, to get better cabling results overall, networks with low congestion values ​​should be prioritized, meaning they tend to be processed later.

[0028] The priority adjustment strategy based on bus offset is as follows:

[0029] For the routing results generated in the initial layer allocation stage, the layer switching stage will determine whether there is a bus deviation. If there is a bus deviation, the layer switching stage will be entered, and all the remaining nets will be disassembled except for the nets without bus deviation.

[0030] To better adjust the layer allocation order, the element of bus offset is introduced; for the bus net set B = {B1, B2, ..., B} n The formula for bus deviation is shown in Formula 3 below;

[0031]

[0032] Among them, WPG i j (k) indicates bus B i From the source pin group (PG) i 0) The k-th signal bit to the j-th destination pin group (PG) i j The distance to the k-th signal bit, MWPG i j Indicates bus B i The maximum distance between all pin pairs, where n represents the number of buses;

[0033] The calculation method for the adjustment priority during the layer switching phase is as follows:

[0034]

[0035] Where, pin_number(N) i ) represents the wire mesh N i The number of pins, wirelength(N) i ) represents the wire mesh N i Bus length, congestion(N) i ) is N i The sum of congestion values, deviation(B) i ) is bus B i The bus deviation, where β and γ are both weighting factors;

[0036] The sum of the overall congestion values ​​is evaluated as congestion(N). i ) and bus deviation (B i The method is as follows: The greater the deviation of the bus, the greater the possibility of timing disorder if it is processed later; therefore, buses with large deviations are prioritized; at the same time, different nets have different levels of congestion, and nets with higher levels of congestion require more via resources to ensure routing connectivity; therefore, in order to obtain better routing results in the overall layer allocation, it is necessary to optimize the bus deviation while reducing the increase in line length, and to comprehensively consider both the degree of congestion and the bus deviation.

[0037] The layer switching strategy based on bus deviation is used to solve the problem that the distance difference between the driving pin group and the receiving pin group in each pin group is widened due to obstacle avoidance, which causes the signal bits in the bus to be unable to deliver the transmitted data at the same time, resulting in timing disorder. The specific method is as follows: for nets with bus deviation and short line length, the number of track resources within a preset range is increased, and it is searched to see if a path can be obtained to reduce the bus deviation. Then, for nets with bus deviation and long line length, it is checked whether there is a new path that can maintain or reduce the line length while optimizing the bus. Through multiple iterations, the final routing result is obtained.

[0038] This invention relates to the construction of an overall routing method for very large-scale integrated circuits in the field of computer-aided design technology of integrated circuits. For current multi-layer routing designs, the invention judges and optimizes bus deviations during the layer allocation stage, which can better meet the timing characteristics requirements of the chip and improve chip performance.

[0039] This invention can be used for overall routing design of very large-scale integrated circuits, effectively reducing bus length deviations and thus obtaining a high-quality overall routing result. Attached Figure Description

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0041] Appendix Figure 1 This is a schematic diagram of the layer allocation process mode of the 2.5D global routing of the present invention;

[0042] Appendix Figure 2 This is a flowchart illustrating the method described in this invention;

[0043] Appendix Figure 3 This is a flowchart illustrating the layer switching strategy in the method described in this invention. Detailed Implementation

[0044] As shown in the figure, a multi-strategy layer allocation method considering bus deviation is used to reduce bus length deviation in routing design. The method includes a priority allocation strategy based on congestion value in the initial layer allocation stage, a priority adjustment strategy based on bus deviation, and a layer swapping strategy based on bus deviation; and includes the following steps.

[0045] Step S1: In the layer allocation stage, the priority of each net is evaluated according to the congestion situation to obtain different layer allocation orders, and routing is performed according to the priority order; when a better solution is obtained for the line length, a routing result with smaller bus deviation is also obtained.

[0046] Step S2: For the routing results generated in the initial layer allocation stage, the bus deviation factor of the initial routing results is introduced into the evaluation of the routing priority adjustment order, the layer allocation order of each net is adjusted, and the timing matching of the routing results is optimized.

[0047] Step S3: Calculate bus deviation. For nets with bus deviation, given the number of track resources, increase the length of shorter buses and decrease or keep the length of longer buses to find the path that satisfies timing matching for each net and optimize the bus deviation.

[0048] The layer allocation method is used for 2.5D global routing, which includes a 2D stage and a 3D stage. Based on the 2D routing scheme of the overall routing, the layer allocation stage allocates routing resources, finds a path without overflow in each net, and connects adjacent routing units located in different metal layers of each net through via edges to obtain a 3D routing scheme.

[0049] 2.5D global routing refines the routing stages compared to 3D global routing and is currently the mainstream routing method for global routing. Figure 1 The layer assignment process for 2.5D global routing was simulated. Figure 1 In diagram (a), given a 2D global routing scheme for a net N with three pins, after applying the layer allocation algorithm, each wire of net N is assigned to an appropriate routing layer without exceeding the constraint of track resources, such as... Figure 1 As shown in (b) above. Conductors from different wiring layers are connected to the network via vias.

[0050] The method described above for calculating the line length is as follows:

[0051] Given G 0 =(V 0 E 0 ) represents a 2D wiring mesh diagram, where v 0 ∈V 0 For wiring units, e 0 ∈E 0 G is the connection edge between adjacent wiring units.1 =(V 1 E 1 ) represents a 3D wiring diagram, where V 1 Same as V 0 For the edge of the through hole, E 0 For wiring edges;

[0052] Under the condition of satisfying the constraint rules and without changing the 2D routing result, each routing edge of the bus 2D routing result is assigned to a suitable routing layer in the 3D structure to complete the layer assignment work and obtain the 3D routing result. The 3D routing result has both a shorter bus length and an optimized bus deviation. The formula for the bus length is shown in Formula 1 below.

[0053]

[0054] Where l is the number of metal layers; V cost It is the cost of the via; r(e) is the number of track resources used for each wiring edge.

[0055] like Figure 2 As shown, the 2.5D global routing includes the following process;

[0056] Process A1: Based on the 2D routing results, the priority order of net layer allocation is determined by comprehensively considering indicators such as congestion level, number of pins and line length. Based on the obtained priority order, the initial layer allocation routing result is obtained by using a layer allocation algorithm based on minimizing the number of vias, and the bus deviation is calculated.

[0057] In process A2, during the layer switching phase, which is the stage where routing resources are allocated, the first step is to determine if there is any deviation. If there is no bus deviation, the 3D routing result is obtained directly. If there is a bus deviation, all nets except those without bus deviation are disassembled.

[0058] Process A3: The priority order of net layer allocation is determined by a priority strategy that integrates bus deviation, pin count, and line length indicators. The obtained priority order is then used to obtain the layer allocation result through a layer allocation algorithm based on minimizing the number of vias. After obtaining the layer allocation result, it is determined whether bus deviation still exists. If it does, the shorter nets are given a certain line length, the routing layer is redistributed, and the routing status is updated. Then, for the longer nets with bus deviation, it is determined whether there is a better path selection, and finally the 3D routing result is obtained.

[0059] The priority allocation strategy based on congestion value in the initial layer allocation phase is as follows: A strategy of processing nets sequentially is adopted, that is, allocating appropriate metal layers to each net according to the allocation order. After each allocation of routing resources, the existing routing resource reserve needs to be updated to avoid actual routing overflow. Specifically, higher-priority nets receive better routing resources to optimize routing results, while lower-priority nets have fewer routing resources available for them. This is achieved by setting a priority function to optimize the routing resource allocation order. Specifically, for net Ni, when calculating its layer allocation priority, the bus length needs to be kept small while reducing bus deviation. The higher the net's order, the earlier the routing resources are allocated to net Ni and the routing results are obtained. The priority setting rule is that the higher the priority, the earlier the order.

[0060] The initial priority P1(Ni) is calculated as follows:

[0061]

[0062] Where pin_number(N) i ) represents the number of pins in the net Ni, and wirelength(N) i ) is N i The line length, congestion(N) i ) is N i The sum of congestion values, where α is the weighting factor.

[0063] When the sum of congestion (N) is used... i ) as the main component, and the comprehensive pin count pin_numer(N) i ), wirelength(N) i When the priority order is determined by multiple factors, the specific evaluation method is as follows: wirelength(N) i The more complex the 2D line length of a net, the more routing resources it requires. Even if the net is prioritized for routing resource allocation to obtain better routing resources, the probability of obtaining a good routing result is still not high. After allocating complex nets, the probability that nets with simpler topologies will need more routing resources to complete metal layer allocation due to insufficient resources is greatly increased, which may maliciously increase the bus length of the routing result. Therefore, the priority of nets with more complex 2D line lengths should be set as low as possible; pin_numer(N i The more pin pairs a net has, the more track resources it requires. For this type of net, if there are fewer routing resources available, the chance of the bus length increasing maliciously after layer allocation will be greatly increased, and it will be difficult to obtain a timing-matching solution. Therefore, a higher priority should be set for bus nets with more pin pairs.

[0064] congestion(N i The higher the congestion level of a network, the more cabling edge and track resources are required. Even if the network can prioritize the cabling layer, it will still waste cabling resources. Therefore, to get better cabling results overall, networks with low congestion values ​​should be prioritized, meaning they tend to be processed later.

[0065] The priority adjustment strategy based on bus offset is as follows:

[0066] For the routing results generated in the initial layer allocation stage, the layer switching stage will determine whether there is a bus deviation. If there is a bus deviation, the layer switching stage will be entered, and all the remaining nets will be disassembled except for the nets without bus deviation.

[0067] To better adjust the layer allocation order, the element of bus offset is introduced; for the bus net set B = {B1, B2, ..., B} n The formula for bus deviation is shown in Formula 3 below;

[0068]

[0069] Among them, WPG i j (k) indicates bus B i From the source pin group (PG) i 0) The k-th signal bit to the j-th destination pin group (PG) i j The distance to the k-th signal bit, MWPG i j Indicates bus B i The maximum distance between all pin pairs, where n represents the number of buses;

[0070] The calculation method for the adjustment priority during the layer switching phase is as follows:

[0071]

[0072] Where, pin_number(N) i ) represents the wire mesh N i The number of pins, wirelength(N) i ) represents the wire mesh N i Bus length, congestion(N) i ) is N i The sum of congestion values, deviation(B) i ) is bus B i The bus deviation, where β and γ are both weighting factors;

[0073] The sum of the overall congestion values ​​is evaluated as congestion(N). i ) and bus deviation (B i The method is as follows: The greater the deviation of the bus, the greater the possibility of timing disorder if it is processed later; therefore, buses with large deviations are prioritized; at the same time, different nets have different levels of congestion, and nets with higher levels of congestion require more via resources to ensure routing connectivity; therefore, in order to obtain better routing results in the overall layer allocation, it is necessary to optimize the bus deviation while reducing the increase in line length, and to comprehensively consider both the degree of congestion and the bus deviation.

[0074] like Figure 3 As shown, the layer switching strategy based on bus deviation is used to solve the problem that the distance difference between the driving pin group and the receiving pin group in each pin group is widened due to obstacle avoidance, which causes the signal bits in the bus to be unable to deliver the transmitted data at the same time, resulting in timing disorder. The specific method is as follows: for nets with bus deviation and short line length, the number of track resources within a preset range is increased, and it is searched to see if a path can be obtained to reduce the bus deviation. Then, for nets with bus deviation and long line length, it is checked whether there is a new path that can maintain or reduce the line length while optimizing the bus. Through multiple iterations, the final routing result is obtained.

Claims

1. A multi-strategy-based layer allocation method considering bus skew, used to reduce bus length skew in routing design, characterized by: The method includes an initial layer allocation phase; Includes the following steps; Step S1: In the layer allocation phase, a priority allocation strategy based on congestion value is used to evaluate the priority of each network according to the congestion situation, obtain different layer allocation orders, and perform cabling according to the priority order. A better solution is obtained for the line length, while simultaneously achieving a wiring result with smaller bus deviation; Step S2: For the routing results generated in the initial layer allocation stage, based on the priority adjustment strategy of bus deviation, the bus deviation factor of the initial routing results is introduced into the evaluation of the routing priority adjustment order, the layer allocation order of each net is adjusted, and the timing matching of the routing results is optimized. Step S3: Calculate bus deviation and implement a layer switching strategy based on bus deviation. For nets with bus deviation, under the condition of a given number of track resources, increase the length of shorter buses and reduce or keep the length of longer buses to find the path that satisfies timing matching for each net and optimize bus deviation. The priority allocation strategy based on congestion value in the initial layer allocation phase is as follows: a strategy of processing nets in order is adopted, that is, metal layers are allocated to each net according to the allocation order. After each allocation of routing resources, the existing reserve of routing resources needs to be updated to avoid actual routing overflow. Specifically, higher priority nets are given better routing resources to optimize the routing result, while lower priority nets have fewer routing resources available for them to choose from. That is, the routing resource allocation order is optimized by setting a priority function. Specifically: for wire network N i When calculating the priority of its layer allocation, it is necessary to reduce bus skew while ensuring a small bus length, so that the net order is prioritized to make net N i The earlier cabling resources are allocated and cabling results are obtained, the higher the priority rule is, the earlier the order. Initial stage priority P1(N) i The calculation method for ) is as follows: Where pin_number(N) i ) represents the number of pins in the net Ni, and wirelength(N) i ) is N i The line length, congestion(N) i ) is N i The sum of congestion values, where α is the weighting factor; The priority adjustment strategy based on bus offset is as follows: For the routing results generated in the initial layer allocation stage, the layer switching stage will determine whether there is a bus deviation. If there is a bus deviation, the layer switching stage will be entered, and all the remaining nets will be disassembled except for the nets without bus deviation. To better adjust the layer allocation order, the element of bus offset is introduced; for the bus net set B = {B1, B2, ..., B} n The formula for bus deviation is shown in Formula 3 below; in, Indicates bus B i From source pin group PG i 0 The k-th signal bit to the j-th destination pin group The distance to the kth signal bit, Indicates bus B i The maximum distance between all pin pairs, where n represents the number of buses; The calculation method for the adjustment priority during the layer switching phase is as follows: Where, pin_number(N) i ) represents the wire mesh N i The number of pins, wirelength(N) i ) represents the wire mesh N i Bus length, congestion(N) i ) is N i The sum of congestion values, deviation(B) i ) is bus B i The bus deviation, where β and γ are both weighting factors.

2. The layer allocation method based on multiple strategies and considering bus deviation according to claim 1, characterized in that: The layer allocation method is used for 2.5D global routing, which includes a 2D stage and a 3D stage. Based on the 2D routing scheme of the overall routing, the layer allocation stage allocates routing resources, finds a path without overflow in each net, and connects adjacent routing units located in different metal layers of each net through via edges to obtain a 3D routing scheme.

3. The layer allocation method based on multiple strategies and considering bus deviation according to claim 2, characterized in that: The method described above for calculating the line length is as follows: Given G 0 =(V 0 E 0 ) represents a 2D wiring mesh diagram, where v 0 ∈V 0 For wiring units, e 0 ∈E 0 G is the connection edge between adjacent wiring units. 1 =(V 1 E 1 ) represents a 3D wiring diagram, where V 1 Same as V 0 For the edge of the through hole, E 0 For wiring edges; Under the condition of satisfying the constraint rules and without changing the 2D routing result, each routing edge of the bus 2D routing result is assigned to the routing layer in the 3D structure to complete the layer assignment work and obtain the 3D routing result. The 3D routing result has both a short bus length and an optimized bus deviation. The formula for bus length is shown in Formula 1 below; Where l is the number of metal layers; V cost It is the cost of the via; r(e) is the number of track resources used for each wiring edge.

4. The layer allocation method based on multiple strategies and considering bus deviation according to claim 3, characterized in that: The 2.5D global routing includes the following process; Process A1: Based on the 2D routing results, the priority order of net layer allocation is determined by comprehensively considering congestion level, pin count and line length. Based on the obtained priority order, the initial layer allocation routing result is obtained by using a layer allocation algorithm based on minimizing the number of vias, and the bus deviation is calculated. In process A2, during the layer switching stage, which is the stage of allocating routing resources in the layer allocation stage, it is first determined whether there is a deviation. If there is no bus deviation, the 3D routing result is obtained directly; if there is a bus deviation, all nets except those without bus deviation are disassembled. Process A3: The priority order of net layer allocation is determined by a priority strategy that integrates bus deviation, pin count, and line length indicators. The obtained priority order is then used to obtain the layer allocation result through a layer allocation algorithm based on minimizing the number of vias. After obtaining the layer allocation result, it is determined whether bus deviation still exists. If it does, the line length of shorter nets is increased, the routing layer is reallocated, and the routing status is updated. Then, it is determined whether there is a better path selection for the longer nets with bus deviation, and finally the 3D routing result is obtained.

5. The layer allocation method based on multiple strategies and considering bus deviation according to claim 1, characterized in that: The sum of the overall congestion values ​​is evaluated as congestion(N). i ) and bus deviation (B i The method is as follows: The greater the deviation of the bus, the greater the possibility of timing disorder if it is processed later; therefore, buses with large deviations are prioritized; at the same time, different nets have different levels of congestion, and nets with higher levels of congestion require more via resources to ensure routing connectivity; therefore, in order to obtain better routing results in the overall layer allocation, it is necessary to optimize the bus deviation while reducing the increase in line length, and to comprehensively consider both the degree of congestion and the bus deviation.

6. The layer allocation method based on multiple strategies and considering bus deviation according to claim 5, characterized in that: The layer switching strategy based on bus deviation is used to solve the problem that the distance difference between the driving pin group and the receiving pin group in each pin group is widened due to obstacle avoidance, which causes the signal bits in the bus to be unable to deliver the transmitted data at the same time, resulting in timing disorder. The specific method is as follows: for nets with bus deviation and short line length, the number of track resources within a preset range is increased, and it is searched to see if a path can be obtained to reduce the bus deviation. Then, for nets with bus deviation and long line length, it is checked whether there is a new path that can optimize the bus while maintaining or reducing the line length. Through multiple iterations, the final routing result is obtained.

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