A memory operation method, a memory and a storage system

Abstract

This application discloses an operation method, a memory, and a storage system for a memory. The memory includes a storage array and peripheral circuitry for controlling the storage array. The operation method includes: obtaining first operating data customized for the peripheral circuitry in a first scenario; the first scenario differs from a default scenario configured for the peripheral circuitry during initialization; and configuring the peripheral circuitry based on the first operating data to ensure that the performance of the memory meets the requirements of the first scenario.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory technology, and in particular to a method for operating a memory, a memory, and a storage system. Background Technology

[0002] Recently, with the development of memory, memory can be either volatile or non-volatile. Non-volatile memory can retain data even when no power is applied, and therefore it is widely used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices, especially 3D NAND flash memory. 3D NAND flash memory achieves data storage by capturing and storing charge in the gate dielectric layer of its contained memory cells. Currently, the configuration of memory operating in specific scenarios requires reconfiguration during memory restarts or other situations, which is not only complex but also time-consuming. Summary of the Invention

[0003] In view of this, embodiments of this application provide an operation method for a memory, a memory, and a storage system to solve the above problems.

[0004] Therefore, the technical solution of this application is implemented as follows:

[0005] Firstly, embodiments of this application provide a method for operating a memory.

[0006] The memory includes a memory array and peripheral circuitry for controlling the memory array, and the operation method includes:

[0007] Obtain first operating data customized for the peripheral circuit in a first scenario; the first scenario is different from the default scenario configured for the peripheral circuit during initialization.

[0008] The peripheral circuit is configured based on the first operating data so that the performance of the memory meets the requirements in the first scenario.

[0009] Secondly, embodiments of this application also provide a memory.

[0010] Includes: storage arrays used to store data;

[0011] and peripheral circuitry coupled to and configured to control the memory array; wherein,

[0012] The peripheral circuit is configured to: obtain first operating data customized for the peripheral circuit in a first scenario; the first scenario is different from the default scenario configured for the peripheral circuit during initialization.

[0013] The peripheral circuit is configured based on the first operating data so that the performance of the memory meets the requirements in the first scenario.

[0014] Thirdly, embodiments of this application also provide a storage system, including: one or more of the aforementioned memories; and a memory controller coupled to the one or more memories;

[0015] The memory controller is configured to send read commands or write commands to the memory.

[0016] The memory is configured to: in response to the read command or write command, obtain first operating data customized for the peripheral circuit in a first scenario; the first scenario is different from the default scenario configured for the peripheral circuit during initialization; and configure the peripheral circuit based on the first operating data so that the performance of the memory meets the requirements in the first scenario.

[0017] This application provides an operation method for a memory, a memory, and a memory system. The memory includes a memory array and peripheral circuitry for controlling the memory array. The operation method includes: obtaining first operating data customized for the peripheral circuitry in a first scenario; the first scenario differs from a default scenario configured for the peripheral circuitry during initialization; and configuring the peripheral circuitry based on the first operating data to ensure the memory's performance meets the requirements of the first scenario. The memory operation method provided in this application stores user-customized configuration data for a specific scenario in the memory array. Therefore, when re-operating the memory in that specific scenario, the configuration data can be directly read from the memory array for configuration, eliminating the need for manual reconfiguration by the user. This not only simplifies user operation but also saves significant configuration time, improving the user experience of using the memory. Attached Figure Description

[0018] Figure 1 A flowchart illustrating a method for operating a memory according to an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of an exemplary memory that includes peripheral circuitry;

[0020] Figure 3 A side view of a cross-section of an exemplary memory array containing strings of memory cells, according to some aspects of this application;

[0021] Figure 4 A block diagram of an exemplary memory including a storage array and peripheral circuitry;

[0022] Figure 5A simplified schematic diagram of the configuration process for memory as peripheral circuitry;

[0023] Figure 6 Schematic diagram of the configuration process for memory as peripheral circuitry Figure 1 ;

[0024] Figure 7 Schematic diagram of the configuration process for memory as peripheral circuitry Figure 2 ;

[0025] Figure 8 Schematic diagram of the configuration process for memory as peripheral circuitry Figure 3 ;

[0026] Figure 9 This application provides a schematic diagram of the structure of a storage system according to an embodiment of the present application.

[0027] Figure 10 A block diagram of an exemplary system with memory in the related art;

[0028] Figure 11 A schematic diagram of an exemplary memory card with memory;

[0029] Figure 12 This is a schematic diagram of an exemplary solid-state drive (SSD) with storage. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The flowcharts in the accompanying drawings show a logical order, but in some cases, the steps shown or described may be performed in a different order than that shown herein.

[0031] For memory to maintain basic operation, POR configuration is essential. To meet specific user requirements in certain scenarios, default values ​​in the POR configuration can be replaced with user-desired values ​​through user configuration, thus enabling the memory to meet user expectations. However, current user configurations are typically manual, and these configurations are lost in the event of memory malfunctions (power outages or restarts, etc.), requiring reconfiguration after power-on, which is not only complex but also time-consuming.

[0032] Therefore, in order to solve the above problems, see [link to relevant documentation]. Figure 1The diagram shows a flowchart illustrating an operation method of a memory provided in an embodiment of this application. Figure 1 The memory shown includes a memory array and peripheral circuitry for controlling the memory array; specifically, the operation method may include:

[0033] S101: Obtain first operating data customized for the peripheral circuit in the first scenario; the first scenario is different from the default scenario configured for the peripheral circuit during initialization.

[0034] S102: Configure the peripheral circuit based on the first operating data so that the performance of the memory meets the requirements in the first scenario.

[0035] It should be noted that the operation method may include some operations for configuring the peripheral circuits of the memory, and may also be referred to as the memory configuration method.

[0036] For an example of the memory structure described in this application, please refer to [reference needed]. Figure 2 , Figure 2 This diagram illustrates a structural schematic of the memory provided in this application. Figure 2 The memory 200 includes a memory array 201 and peripheral circuitry 202 coupled to the memory array. In some embodiments, the memory array 201 may be a NAND flash memory array or other types of volatile memory array, wherein memory cells 206 are provided in the form of an array of NAND memory cell strings 208, each NAND memory cell string 208 extending vertically above a substrate (not shown). In some embodiments, each NAND memory cell string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the storage region of the memory cell 206. Each memory cell 206 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0037] In some embodiments, each memory cell 206 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 206 is a multi-level cell (MLC) capable of storing a single bit of data in multiple four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a trinary level cell (TLC), or four bits per cell (also known as a quadruple level cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to that memory cell. A fourth nominal storage value may be used for the erase state.

[0038] like Figure 2 As shown, each NAND cell string 208 may include a source select gate (SSG) 210 at its source end and a drain select gate (DSG) 212 at its drain end. SSG 210 and DSG 212 can be configured to activate the selected NAND cell string 208 (column of the array) during read and program (or write) operations. In some embodiments, the sources of NAND cell strings 208 in the same block 204 are coupled via the same source line (SL) 214 (e.g., common SL). In other words, according to some embodiments, all NAND cell strings 208 in the same block 204 have an array common source (ACS). According to some embodiments, the DSG 212 of each NAND cell string 208 is coupled to a corresponding bit line 216, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory cell string 208 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG212) or a deselection voltage (e.g., 0 volts (V)) to the corresponding DSG212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG210) or a deselection voltage (e.g., 0V) to the corresponding SSG210 via one or more SSG lines 215.

[0039] like Figure 2As shown, NAND cell strings 208 can be organized into multiple blocks 204, each of which can have a common source line 214 (e.g., coupled to ground). In some embodiments, each block 204 is a basic data unit with an erase operation, i.e., all cells 206 on the same block 204 are erased simultaneously. To erase cells 206 in a selected block 204, a bias voltage (Vers) (e.g., a high positive voltage of 20V or higher) can be used to couple the source line 214 of the selected block 204 and the unselected blocks 204 on the same plane as the selected block 204. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Cells 206 of adjacent NAND cell strings 208 can be coupled via word lines 218, which select which row of cells 206 receives read and program operations. In some embodiments, memory cells 206 coupled to the same word line 218 are referred to as a physical page 220. A physical page 220 can be a basic unit of data used for programming or reading operations, and the size of a physical page 220, measured in bits, can be related to the number of NAND memory cell strings 208 coupled by word lines 218 in a block 204. Each word line 218 may include multiple control gates (gate electrodes) at each memory cell 206 within the corresponding page 220, as well as gate lines coupling the control gates.

[0040] Figure 3 A side view of a cross-section of an exemplary memory array 201 including NAND memory cell strings 208, according to some aspects of the present invention, is shown. Figure 3 As shown, the NAND memory cell string 208 can extend vertically through the memory stack layer 302 above the substrate 301. The substrate 301 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0041] The memory stack 302 may include alternating gate conductive layers 303 and gate-to-gate dielectric layers 804. The number of pairs of gate conductive layers 303 and gate-to-gate dielectric layers 804 in the memory stack 302 determines the number of memory cells 206 in the memory array 201. The gate conductive layers 303 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 303 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 303 includes a doped polysilicon layer. Each gate conductive layer 303 may include a control gate surrounding the memory cell 206 and may extend laterally at the top of the memory stack 302 as a DSG line 213, at the bottom of the memory stack 302 as an SSG line 215, or between DSG lines 213 and SSG lines 215 as a word line 218.

[0042] like Figure 3 As shown, the NAND memory cell string 208 includes a channel structure 305 extending vertically through the memory stack layer 302. In some embodiments, the channel structure 305 includes channel holes filled with one or more semiconductor materials and one or more dielectric materials. In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure 305 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0043] Return to reference Figure 2Peripheral circuitry 202 can be coupled to memory array 201 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213. Peripheral circuitry 202 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 201 by applying voltage and / or current signals to each target memory cell 206 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213, and by sensing voltage and / or current signals from each target memory cell 206. Peripheral circuitry 202 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 4 Some exemplary peripheral circuitry is shown. Peripheral circuitry 202 includes a page buffer / sensor amplifier 404, a column decoder / bit line driver 406, a row decoder / word line driver 408, a voltage generator 410, a control logic unit 412, a register 414, an interface 416, and a data bus 418. It should be understood that in some examples, additional components may be included. Figure 4 Additional peripheral circuitry not shown.

[0044] Page buffer / sensor amplifier 404 can be configured to read data from memory array 201 and program (write) data to memory array 201 according to control signals from control logic unit 412. In one example, page buffer / sensor amplifier 404 can store a page of programming data (write data) to be programmed into a page 220 of memory array 201. In another example, page buffer / sensor amplifier 404 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 206 coupled to selected word line 218. In yet another example, page buffer / sensor amplifier 404 can also sense a low-power signal from bit line 216 representing a data bit stored in memory cell 206 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 406 can be configured to be controlled by control logic unit 412 and select one or more NAND memory cell strings 208 by applying a bit line voltage generated from voltage generator 410.

[0045] The row decoder / word line driver 408 can be configured to be controlled by the control logic unit 412 and to select / deselect block 204 of the memory array 201 and select / deselect word line 218 of block 204. The row decoder / word line driver 408 can also be configured to drive word line 218 using word line voltages generated from the voltage generator 410. In some embodiments, the row decoder / word line driver 408 can also select / deselect and drive SSG line 215 and DSG line 213. As described in detail below, the row decoder / word line driver 408 is configured to perform an erase operation on memory cell 206 coupled to one or more selected word lines 218. The voltage generator 410 can be configured to be controlled by the control logic unit 412 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 201.

[0046] Control logic unit 412 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 414 can be coupled to control logic unit 412 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 416 can be coupled to control logic unit 412 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 412, and to buffer status information received from control logic unit 412 and relay it to the host. Interface 416 can also be coupled to column decoder / bit line driver 406 via data bus 418 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 201. The charge pump and high-voltage regulator involved in this embodiment of the invention can be included in voltage generator 410.

[0047] It should be noted that the memory structure described above is merely an exemplary structure, and other types of memory, or memory structures of other kinds, are also applicable to the operation method of this application.

[0048] Based on the aforementioned memory structure, in S101, the first scenario can be any scenario different from the default scenario. For example, the first scenario can be a high-temperature scenario, meaning the memory operates in this high-temperature scenario; or, for example, the first scenario can be a low-temperature scenario, meaning the memory operates in this low-temperature scenario; or, for example, the first scenario can also be a scenario with unstable power supply voltage, meaning the memory operates in this scenario with unstable power supply voltage. The so-called first operating data customized for the peripheral circuits means that, in this specific environment of the first scenario, the voltage required for the memory to correctly perform read and write operations may differ from that in the default scenario. The so-called initialization configuration can refer to the Power On Read / Reset (POR) configuration. This POR configuration automatically acquires basic configuration data (or default operating data) after the memory is powered on and automatically configures to form the default scenario. The default scenario can also be considered as the scenario tested before the memory leaves the factory, enabling normal read and write operations. The basic configuration data can refer to the minimum amount of configuration data that ensures the memory starts and operates normally, or, in other words, some default parameter values ​​set for the peripheral circuits before the memory leaves the factory. After POR configuration is completed, the memory can perform basic startup, writing, reading, and erasing operations. It should be noted that "basic startup, writing (programming), reading, and erasing operations" here refers to performing these operations according to the default data configured in the POR. For example, in Incremental Step Pulse Programming (ISPP), after POR configuration, parameters such as the maximum number of programming cycles, the initial offset of the programming voltage, and the increment step size of the programming voltage are all default values. For instance, the default maximum programming cycle count is 30, the default initial offset of the programming voltage is 0 volts (V), and the default increment step size of the programming voltage is 0.5V, etc. The technical solution described in this application means that after the memory starts up, a set of operating data is automatically configured for the peripheral circuits so that the memory can perform read, write, and other operations normally. Furthermore, when encountering a specific working environment, a set of operating data suitable for that specific working environment is configured for the peripheral circuits to meet the performance requirements under that specific working environment. The performance requirements mentioned can refer to the ability to read and write correctly, read and write quickly, and other performance characteristics that meet user expectations.

[0049] The customized configuration of the peripheral circuitry of the memory for a specific working environment can be called user configuration. User configuration aims to ensure that the memory operates according to the user's desired mode of operation, thereby meeting the user's specific needs and achieving better memory performance. For memory, user configuration is an optional function. That is, the memory can operate normally after POR configuration, performing basic write, read, and erase operations, or it can be configured with customized parameters based on user-defined scenarios to achieve better performance.

[0050] Based on this, an example of the memory configuration process can be as follows: Figure 5 As shown. In Figure 5 In this process, POR configuration is performed at or after memory startup; then user configuration is performed; and finally, the memory begins operation (performing startup, basic write, read, and erase operations). As described above, user configuration is an optional function; therefore, the order of user configuration and memory operation can be interchanged. The configuration flow is thus: POR configuration is performed at or after memory startup; then the memory begins operation; and finally, user configuration. In other words, after the memory completes its initialization configuration or during memory operation, user configuration data is received, and the memory is configured.

[0051] In some embodiments, S101 may include: reading the storage array to obtain first operating data customized for the peripheral circuit in a first scenario;

[0052] Alternatively, receive configuration data sent from the memory controller; and obtain first operating data customized for the peripheral circuit in the first scenario based on the current operating data of the peripheral circuit and the configuration data.

[0053] There are two ways to obtain the first operating data: One is that if the first operating data is stored in a storage array, then only the storage array needs to be read to retrieve the first operating data. The other is that if the first operating data is being configured for the peripheral circuit for the first time, then configuration data sent from the memory controller (i.e., the controller) is received, and then, based on the current operating data of the peripheral circuit and the configuration data, the first operating data customized for the peripheral circuit in the first scenario is obtained. That is, the operating values ​​of the corresponding parameters in the current operating data are replaced with the configuration values ​​customized for the same parameters in the configuration data, and together with the remaining current operating data, they form the first operating data. The current operating data can be the default operating data of the initial configuration or the operating data of the previous configuration. The default operating data can be a set of settings written into the memory at the factory in a storage area not accessible to the user, enabling each sub-circuit to function normally. For example, the default data for the maximum programming cycle is 30 times, the default data for the initial offset of the programming voltage is 0 volts (V), and the default data for the increment step of the programming voltage is 0.5V. The previously configured runtime data can be stored in the memory array, which is the runtime data configured during the last runtime scenario.

[0054] In some embodiments, the peripheral circuit includes a plurality of sub-circuits; configuring the peripheral circuit based on the first operating data may include:

[0055] After reading the first running data, the current running data configured in the plurality of sub-circuits is replaced with the first running data;

[0056] Alternatively, after parsing the configuration data, the first sub-running data configured in the corresponding sub-circuit of the plurality of sub-circuits is replaced with the configuration data; the second sub-running data of the other sub-circuits in the plurality of sub-circuits remains unchanged; the default running data includes the first sub-running data and the second sub-running data;

[0057] The initialization configuration includes the POR configuration that is performed automatically after the memory is powered on.

[0058] It should be noted that the aforementioned peripheral circuits include multiple sub-circuits, which can refer to... Figure 4 The page buffer / sensor amplifier 404, column decoder / bit line driver 406, row decoder / word line driver 408, voltage generator 410, control logic unit 412, register 414, interface 416 and data bus 418 shown, as well as other sub-circuits with functions not shown.

[0059] In the process described above, if the first running data is read, it directly replaces the current running data in the plurality of sub-circuits. The current running data can be default running data or previously configured running data. If the first running data is received from the memory controller for the first time, it resolves the command sent from the memory controller carrying the configuration data, obtains the configuration data, and replaces the first sub-running data configured in the corresponding sub-circuit in the plurality of sub-circuits with the configuration data; the second sub-running data of the other sub-circuits in the plurality of sub-circuits remains unchanged. The current running data includes the first sub-running data and the second sub-running data; that is, the running values ​​of the corresponding parameters in the plurality of sub-circuits are replaced with the configuration values ​​customized for the same parameter in the configuration data, while the running data of the remaining parameters remains unchanged.

[0060] Based on the above description, taking the ISPP programming operation of a memory as an example, assuming that after POR configuration, the default data for the maximum number of programming cycles is 30, the default data for the initial offset of the programming voltage is 0 volts (V), and the default data for the increment step of the programming voltage is 0.5V. Assuming the first scenario is a high-temperature scenario, since higher voltage and more programming cycles are required to program data into the memory cell at high temperatures, the maximum number of programming cycles for the ISPP programming operation is 60, the initial offset of the programming voltage is 1V, and the increment step of the programming voltage is 0.1V, provided that the user configuration allows it. Then, after completing the user configuration, when the memory performs ISPP programming, the maximum number of programming cycles is changed from the default data of 30 to 60, the initial offset of the programming voltage is changed from the default data of 0V to 1V, and the increment step of the programming voltage is changed from the default data of 0.5V to 0.1V.

[0061] In some embodiments, when the first operating parameter of the first scenario is obtained based on the configuration data and the current operating data of the peripheral circuit, the operation method further includes: writing the first operating data of the first scenario into the storage array when the power supply voltage of the memory is less than a preset threshold and / or when the memory is reset.

[0062] This illustrates that the timing for storing the first operating data corresponding to the first scenario is when the power supply to the memory is less than a preset threshold and / or when the memory undergoes a reset operation. The preset threshold can be determined based on the memory's operating status. The power supply to the memory being less than the preset threshold can include situations where the memory is powered off, i.e., when there is no power supply.

[0063] It should be noted that, as Figure 6As shown, currently, both POR configuration and user configuration data must be configured into registers within sub-circuits to enable them to perform their functions. These registers collectively form Static Random-Access Memory (SRAM), which typically loses data upon power failure or restart. Default data for POR configuration is stored in a non-user-accessible permanent storage area within the memory. This allows for automatic POR configuration by reading the default data from this non-user-accessible area after power-on. However, user configuration data for the first scenario is manually configured one by one into the corresponding sub-circuits. This data is lost when the memory's power supply voltage is below a preset threshold, when the memory's power supply is lost, or when the memory is reset. This means that upon power-on, the user-configured data still needs to be manually configured, which is cumbersome and time-consuming. Therefore, in the event of these abnormal situations, the memory triggers the storage of the user's configuration data for the current scenario in the storage array for future use. It should be noted that... Figure 6 The reserved physical pages mentioned above are one or more of the aforementioned physical pages 220. Figure 6 The operating parameters 1, 2, ..., n-1, and n in the configuration can be the operating parameters of one or more sub-circuits. In other words, the user configuration for a first scenario can include configuring one or more operating parameters for one or more sub-circuits.

[0064] In some embodiments, the operation method may further include: obtaining second operating data customized for the peripheral circuit in a second scenario;

[0065] The peripheral circuit replaces the first operating data of the first scenario with the second operating data of the second scenario so that the performance of the memory meets the requirements of the second scenario; the second scenario is different from the first scenario.

[0066] It should be noted that the above describes the implementation process of switching from the first scenario to the second scenario. That is, the second runtime data corresponding to the second scenario is obtained, and then the first runtime data of the first scenario is replaced with the second runtime data. The method for obtaining the second runtime data for the second scenario is similar to that for the first runtime data, and will not be repeated here.

[0067] In some embodiments, the peripheral circuit includes multiple sub-circuits; writing the first running data of the first scenario into the storage array includes:

[0068] Read the corresponding operating data of each circuit from the registers of each of the multiple sub-circuits;

[0069] The running data are sorted in a set order to obtain the first running data in the first scenario;

[0070] The first running data is written sequentially into the storage array.

[0071] This describes the process of storing the first set of running data. It involves reading the running data for the first scenario from the registers of each sub-circuit, then storing this running data in a pre-defined order in a storage array. This pre-defined order can refer to the order in which the running data is processed according to the register numbers of the sub-circuit. For example, if there are three registers numbered 1, 2, and 3, corresponding to running data 40, 50, and 60 respectively, then the data is written to the storage array in the order of 40, 50, and 60.

[0072] Based on the foregoing description, the memory operation method provided in this application generally achieves the following: Users can customize configuration data for a specific operating scenario of the memory. Then, based on this customized configuration data, the operating parameters of multiple sub-circuits within the memory's peripheral circuitry are configured to ensure the memory operates within the specified scenario. Furthermore, upon reaching a set condition (power failure or reset), the user's configuration data for the specified scenario is stored in a memory array in a predetermined order for future use. This allows users to re-operate the memory in a previously configured scenario without manual configuration; instead, they only need to read the already configured data from the memory array and operate the memory in the corresponding scenario based on this data to meet their needs. The specified scenario can refer to programming, reading, erasing, and other operations performed under different conditions to achieve optimal memory performance.

[0073] To understand this application, a memory configuration process can be described as follows: Figure 7 As shown, the configuration process for the memory can be as follows:

[0074] S1: When the memory is first used, power on the memory;

[0075] S2: The memory is initialized and configured, that is, POR configuration is performed.

[0076] Specifically, the memory configures the default data of the operating parameters of each sub-circuit of the peripheral circuit stored inside itself into the SRAM of each sub-circuit for storing operating parameters, so that each sub-circuit can operate normally when it is used; as long as the SRAM is kept powered on, the data stored in it can be maintained constantly, and the data stored will be lost when the power is off.

[0077] S3: Read the coded configuration data X customized by the user for the set scenario X from the memory array;

[0078] S4: Decode the encoded configuration data X to obtain the configuration data X;

[0079] S5: For the same operating parameter in multiple sub-circuits, replace the default data configured by POR with the corresponding configuration data X;

[0080] S6: After that, the memory can run in the set scenario X; on this basis, the user can also reconfigure the operating parameters of each sub-circuit of the memory to form the user's configuration data for other set scenarios, so that the memory can run in other set scenarios.

[0081] S7: When the power supply to the memory is turned off, suddenly loses power, or restarts, it triggers the saving of configuration data for other set scenarios and saves it in the storage array for later use;

[0082] S8: When you are finished using the memory, turn off the power supply to the memory and end the use.

[0083] It should be noted that the above process briefly describes some operations performed by the memory itself when the user uses the memory. It saves the user's configuration data for a set scenario for future use, saving time, simplifying user operations, and enabling quick switching between different set scenarios. It should be understood that the above process is only an example; other variations are also covered in the technical solution of this application, which will not be elaborated upon here. The set scenario is similar in meaning to the first and second scenarios, all describing scenarios where the memory customizes operating data for peripheral circuits under specific working conditions.

[0084] See Figure 8 This diagram illustrates the working relationship between the components contained in the memory when the memory configuration provided in this application is applied.

[0085] exist Figure 8In this context, Read Only Memory (ROM) is a memory unit within the control logic of a memory that stores firmware code and / or default data containing the operating parameters of various sub-circuits within the peripheral circuitry. The stored data is permanent and unchangeable; it is essentially a storage area within the memory that is not accessible to the user for permanently stored data. Accessing the default data in the ROM requires row and column addresses. These row and column addresses are written into the POR configuration program, which runs automatically after the memory powers on. That is, when the POR configuration program runs automatically after the memory powers on, it accesses the default data in the ROM based on the row and column addresses contained in the firmware code, retrieves the default data, and configures the various sub-circuits of the peripheral circuitry, enabling the memory to operate in its basic operating mode (the operating mode set at the factory, capable of basic boot, read, write, and erase). After the POR configuration is complete or while the memory is operating in basic operating mode, the user can customize configuration data for a specific scenario and load it into the various sub-circuits of the peripheral circuitry, causing the memory to operate in that scenario. The configuration scenarios can include multiple scenarios, such as scenario 1, ..., scenario n, each with different configuration data. When the specified conditions are met, the configuration data corresponding to the scenario is written to the storage array, and the address of the configuration data in the storage array is added to the POR configuration program. This is so that the configuration data of the user-selected scenario can be used to configure the various sub-circuits of the peripheral circuits during the next use, so that the memory operates in the selected scenario. It should be understood that the address in the POR configuration program is a logical address, which needs to be converted into a physical address by a row decoder and a column decoder to point to the corresponding physical storage space.

[0086] The memory operation method provided in this application stores the configuration data customized by the user for a set scenario in a storage array. In this way, when the memory is restarted to work in the set scenario, the configuration data can be read directly from the storage array for configuration without the need for manual reconfiguration by the user. This not only makes the operation more convenient for the user but also saves a lot of configuration time and improves the user's experience of using the memory.

[0087] This application embodiment also provides a memory, the memory comprising: a storage array for storing data;

[0088] and peripheral circuitry coupled to and configured to control the memory array; wherein,

[0089] The peripheral circuit is configured to implement the aforementioned operation method.

[0090] It should be noted that the memory described here only refers to the structure relevant to this application; other structures are as described above. Figures 2 to 4The structure shown.

[0091] This application also provides a storage system, such as... Figure 9 As shown, the storage system 900 includes: one or more of the aforementioned memory 200; and a memory controller 901 coupled to the one or more memory;

[0092] The memory controller is configured to send a configuration instruction to the memory containing configuration data customized by the user for a set scenario.

[0093] The memory is configured to implement any of the aforementioned operating methods in response to the configuration instructions.

[0094] In some embodiments, the storage system is a solid-state drive (SSD) or a memory card.

[0095] It should be noted that the storage system 900 can be coupled with the host to form a data system, for example... Figure 10 The data system shown. This data system 1000 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 10 As shown, the data system 1000 may include a host 1008 and a storage system 900, wherein the storage system 900 has one or more memories 200 and a memory controller 901; the host 1008 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), wherein the SoC may be, for example, an application processor (AP). The host 1008 may be configured to send data to or receive data from the memories 200. Specifically, the memories 200 may be any memory disclosed in this application, such as phase-change random access memory (PCRAM), three-dimensional NAND flash memory, etc.

[0096] According to some embodiments, a memory controller 901 is coupled to memory 200 and host 1008 and is configured to control memory 200. The memory controller 901 can manage data stored in memory 200 and communicate with host 1008. In some embodiments, the memory controller 901 is designed to operate in a low duty cycle environment, such as on a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller 901 is designed to operate in a high duty cycle environment, such as on a Solid State Drive (SSD) or an embedded Multimedia Card (eMMC), where the SSD or eMMC serves as data storage for mobile devices with high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise storage arrays. The memory controller 901 can be configured to control the operation of the memory 200, such as read, erase, and program operations. The memory controller 901 can also be configured to manage various functions related to data stored or to be stored in the memory 200, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 901 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory 200. The memory controller 901 can also perform any other suitable functions, such as formatting the memory 200. The memory controller 901 can communicate with external devices (e.g., host 1008) according to a specific communication protocol.For example, the memory controller 901 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc. The memory controller 901 and one or more memories 200 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 900 can be implemented and packaged into different types of end electronic products. Figure 11 In one example shown, the memory controller 901 and a single memory 200 can be integrated into a memory card 1102. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a connector for the memory card to a host computer (e.g., Figure 10 The memory card connector 1104 is coupled to the host 1008. In such a... Figure 12 In another example shown, the memory controller 901 and multiple memories 200 can be integrated into the SSD 1202. The SSD may also include components for connecting the SSD to a host (e.g., Figure 10 The SSD connection 1204 is coupled to the host 1008. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. Furthermore, the memory controller 901 can also be configured to control erase, read, and write operations of the memory 200.

[0097] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

Claims

1. A method for operating a memory, characterized in that, The memory includes a memory array and peripheral circuitry for controlling the memory array, and the operation method includes: Receive configuration data sent from the memory controller; obtain first operating data customized for the peripheral circuit in a first scenario based on the current operating data of the peripheral circuit and the configuration data; the first scenario is different from the default scenario configured for the peripheral circuit during initialization configuration; The peripheral circuit is configured based on the first operating data so that the performance of the memory meets the requirements in the first scenario; When the power supply voltage of the memory is less than a preset threshold and / or the memory is reset, the first running data of the first scenario is written into the storage array.

2. The operating method according to claim 1, characterized in that, The operation method further includes: Read the storage array to obtain the first operating data customized for the peripheral circuit in the first scenario.

3. The operating method according to claim 2, characterized in that, The peripheral circuit includes multiple sub-circuits; configuring the peripheral circuit based on the first operating data includes: After reading the first running data, the current running data configured in the plurality of sub-circuits is replaced with the first running data; Alternatively, after parsing the configuration data, the first sub-operation data configured in the corresponding sub-circuit of the plurality of sub-circuits is replaced with the configuration data; the second sub-operation data of the other sub-circuits in the plurality of sub-circuits remains unchanged; the current operation data includes the first sub-operation data and the second sub-operation data; The initialization configuration includes the POR configuration that is performed automatically after the memory is powered on.

4. The operating method according to claim 1, characterized in that, The storage array stores the operating data of the peripheral circuits under multiple different scenarios.

5. The operating method according to claim 1, characterized in that, The operation method further includes: Obtain second operating data customized for the peripheral circuit in the second scenario; The peripheral circuit replaces the first operating data of the first scenario with the second operating data of the second scenario so that the performance of the memory meets the requirements of the second scenario; the second scenario is different from the first scenario.

6. The operating method according to claim 1, characterized in that, The peripheral circuit includes multiple sub-circuits; writing the first running data of the first scenario into the storage array includes: Read the corresponding operating data of each circuit from the registers of each of the multiple sub-circuits; The running data are sorted in a set order to obtain the first running data in the first scenario; The first running data is written sequentially into the storage array.

7. A memory, characterized in that, include: Storage arrays used for storing data; and peripheral circuitry coupled to and configured to control the memory array; wherein, The peripheral circuit is configured to: receive configuration data sent from the memory controller; and obtain first operating data customized for the peripheral circuit in a first scenario based on the current operating data of the peripheral circuit and the configuration data; the first scenario is different from the default scenario configured for the peripheral circuit during initialization. The peripheral circuit is configured based on the first operating data so that the performance of the memory meets the requirements in the first scenario; When the power supply voltage of the memory is less than a preset threshold and / or the memory is reset, the first running data of the first scenario is written into the storage array.

8. A storage system, characterized in that, include: One or more of the memories described in claim 7; and a memory controller coupled to the one or more memories; wherein, The memory controller is configured to send a read command or a write command to the memory; The memory is configured to: in response to the read command or write command, obtain first operating data customized for the peripheral circuit in a first scenario; the first scenario is different from the default scenario configured for the peripheral circuit during initialization. The peripheral circuit is configured based on the first operating data so that the performance of the memory meets the requirements in the first scenario.

9. The storage system according to claim 8, characterized in that, The storage system includes solid-state drives (SSDs) or memory cards.

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