High-voltage gan mis-hemt device and method of manufacturing the same

Abstract

The application discloses a high-voltage GaN MIS-HEMT device and a preparation method thereof. The method comprises the following steps: preparing a GaN MIS-HEMT device without a gate field plate; preparing a first layer of gate field plates on the GaN MIS-HEMT device without the gate field plate; sequentially depositing a first passivation dielectric layer and a second passivation dielectric layer on the surface of the GaN MIS-HEMT device with the first layer of gate field plates; preparing a second layer of gate field plates at the position of the second layer of gate field plates reserved by etching, and preparing a third layer of gate field plates on the second layer of gate field plates; depositing a third passivation dielectric layer on the surface of the device; forming a fourth layer of gate field plate setting position on the third passivation dielectric layer corresponding to the fourth layer of gate field plates reserved by etching, preparing a fourth layer of gate field plates in the fourth layer of gate field plate setting position, and forming a fifth layer of gate field plates on the upside of the fourth layer of gate field plates. The method has a simple process flow, and can improve the breakdown voltage and the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of electronic device technology, and in particular to a high-voltage GaN MIS-HEMT device and its fabrication method. Background Technology

[0002] Due to its excellent material properties and the effects of spontaneous polarization and piezoelectric polarization, GaN-based MIS-HEMT devices are highly favored in high-voltage, high-power applications. However, high-quality GaN is difficult to obtain due to limitations in materials and epitaxy, and material defects and interface states can significantly impact the electrical performance of the devices. To enable devices to withstand higher voltages, field plates, a commonly used electric field modulation technique, are well-suited for GaN MIS-HEMT devices. The gate field plate can modulate and reduce the electric field between the gate and drain, effectively improving the device's breakdown voltage and mitigating the excitation of traps and interface states by the high electric field. This also improves the device's dynamic characteristics and current collapse between the gate and drain. Therefore, the gate field plate, with its relatively simple fabrication process and beneficial effects, has become a preferred choice for high-voltage GaN MIS-HEMT devices. With advancements in fabrication technology and increasing demands for high voltage and high power, 600V-class devices are gradually becoming commercially available. To better meet the requirements of high-voltage applications and achieve a withstand voltage of 1500V, the gate-drain spacing and gate field plate of GaN MIS-HEMT devices need to be further adjusted. However, due to the constraints of the material itself and application requirements, the adjustment space for the gate-drain spacing is limited, while the gate field plate can be further optimized to achieve effective modulation of the electric field and improve the breakdown voltage of the device. Summary of the Invention

[0003] The technical problem to be solved by the present invention is how to provide a high-voltage GaN MIS-HEMT device fabrication method with a simple process flow that can improve breakdown voltage and device reliability.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a method for fabricating a high-voltage GaN MIS-HEMT device, characterized by comprising the following steps:

[0005] 1) Fabrication of GaN MIS-HEMT devices without gate field plates;

[0006] 2) Fabricate the first gate field plate on a GaN MIS-HEMT device without a gate field plate;

[0007] 3) A first passivation dielectric layer and a second passivation dielectric layer are sequentially deposited on the surface of a GaN MIS-HEMT device having a first gate field plate;

[0008] 4) Etch or corrode the second passivation dielectric layer and terminate at the first passivation dielectric layer, and reserve the position for setting the second gate field plate and the alignment position for the fourth gate field plate at the corresponding position;

[0009] 5) Fabricate a second grid field plate at the reserved position of the second grid field plate, and fabricate a third grid field plate on the second grid field plate, wherein the third grid field plate is perpendicular to the first grid field plate in the vertical direction.

[0010] It has partial overlap;

[0011] 6) A third passivation dielectric layer is deposited on the device surface after step 5);

[0012] 7) A fourth gate field plate setting position is formed on the third passivation dielectric layer above the fourth gate field plate alignment position, a fourth gate field plate is prepared within the fourth gate field plate setting position, and a fifth gate field plate is formed on the upper side of the fourth gate field plate, wherein the fifth gate field plate partially overlaps with the third gate field plate in the vertical direction.

[0013] 8) The dielectric material above the source and drain electrodes is removed by etching or corrosion to complete the fabrication of a high-voltage GaN MIS-HEMT device with five gate field plates.

[0014] Accordingly, the present invention also discloses a high-voltage GaN MIS-HEMT device, comprising a device body, characterized in that: a first gate field plate is formed on the upper side of the gate electrode on the device body, the first gate field plate covers the gate electrode, a first passivation dielectric layer is located between the source electrode and the drain electrode of the device, and covers the first gate field plate, a second passivation dielectric layer is formed on the upper surface of the first passivation dielectric layer, a second gate field plate setting position and a fourth gate field plate alignment position are formed on the upper surface of the second passivation dielectric layer, a second gate field plate is disposed within the second gate field plate setting position, and a third gate field plate is connected to the second gate field plate. Furthermore, the third-layer gate plate partially overlaps with the first-layer gate plate in the vertical projection direction. The third passivation dielectric layer covers the exposed second passivation dielectric layer, the alignment position of the fourth-layer gate plate, and the third-layer gate plate. A fourth-layer gate plate setting position is formed on the third passivation dielectric layer corresponding to the alignment position of the fourth-layer gate plate. A fourth-layer gate plate is set in the fourth-layer gate plate setting position. The fifth-layer gate plate is connected to the fourth-layer gate plate and located on the upper surface of the third passivation dielectric layer. The fifth-layer gate plate partially overlaps with the third-layer gate plate in the vertical projection direction.

[0015] Furthermore, the device body includes a substrate layer, a GaN buffer layer is formed on the upper surface of the substrate layer, an AlGaN barrier layer is formed on the upper surface of the GaN buffer layer, a gate insulating layer is formed on the upper side of the AlGaN barrier layer, a gate electrode is embedded in the gate insulating layer, and a drain electrode and a source electrode are embedded in the AlGaN barrier layer.

[0016] The beneficial effects of adopting the above technical solution are as follows: the method achieves the purpose of preparing a five-layer gate field plate by etching or corroding the reserved gate field plate position. The process is simple and reduces the steps of photolithography and evaporation stripping. It can not only reduce the electric field strength and increase the breakdown voltage to 1500V by using a five-layer gate field plate, but also balance the electric field distribution of each field plate, thereby improving the reliability of the device. Attached Figure Description

[0017] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0018] Figure 1 This is a schematic diagram of the device after processing in step 1) of the method in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the device after processing in step 2) of the method in an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of the device after processing in step 3) of the method in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of the device after processing in step 4) of the method in an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram of the device after processing in step 5) of the method in an embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram of the device after processing in step 6) of the method in an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of the device after processing in step 7) of the method in an embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of the device after processing in step 8) of the method in an embodiment of the present invention;

[0026] Wherein: 1. First gate field plate; 2. First passivation dielectric layer; 3. Second passivation dielectric layer; 4. Position of second gate field plate; 5. Alignment position of fourth gate field plate; 6. Second gate field plate; 7. Third gate field plate; 8. Third passivation dielectric layer; 9. Position of fourth gate field plate; 10. Fourth gate field plate; 11. Fifth gate field plate; 12. Source electrode; 13. Drain electrode; 14. Substrate; 15. GaN buffer layer; 16. AlGaN barrier layer; 17. Gate insulating layer; 18. Gate electrode. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0028] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0029] This invention discloses a method for fabricating a high-voltage GaN MIS-HEMT device, comprising the following steps:

[0030] 1) The conventional process for fabricating GaN MIS-HEMT devices without a gate field plate includes the following steps:

[0031] A GaN buffer layer 15 is epitaxially grown on a conventional substrate 14, and an AlGaN barrier layer 16 is grown on the GaN buffer layer 15 to form a two-dimensional electron gas (2DEG). A gate insulating layer 17 is grown on the surface of the AlGaN barrier layer 16. The gate insulating layer 17 is etched or corroded to form a gate pattern, leaving a gate insulating layer 17 of a certain thickness under the gate electrode 18. The gate electrode 18 is prepared by evaporation and lift-off. The gate insulating layer 17 and part of the AlGaN barrier layer 16 are etched or corroded to form a source / drain pattern on the AlGaN barrier layer 16. The source electrode 12 and drain electrode 13 are prepared by evaporation and lift-off. Figure 1 As shown.

[0032] 2) Fabricating the first gate field plate 1 on a GaN MIS-HEMT device without a gate field plate, specifically including the following steps:

[0033] After step 1), the first gate field plate pattern is formed on the surface of the device by photolithography, followed by evaporation and lift-off to form the first gate field plate 1 on the first gate field plate pattern. The metal of the first gate field plate 1 can be a metal system such as Ti / Al, Ti / Ta / Al, or Ti / Al / Ni / Au, with a metal thickness of 300nm to 1000nm and a field plate width of 1μm to 3μm. The structure of the device after step 2) is as follows. Figure 2 As shown.

[0034] 3) A first passivation dielectric layer 2 and a second passivation dielectric layer 3 are sequentially deposited on the surface of the GaN MIS-HEMT device having a first gate field plate 1, such as... Figure 3 As shown. Figure 3 In this process, the first passivation dielectric layer 2 and the second passivation dielectric layer 3 can be Si3N4 or SiO2 or other dielectric materials; the thickness of the first passivation dielectric layer 2 is 300nm to 800nm, and the thickness of the second passivation dielectric layer 3 is 100nm to 500nm.

[0035] 4) Etch or corrode the second passivation dielectric layer 3 and terminate at the first passivation dielectric layer 2, reserving the second gate field plate setting position 4 and the fourth gate field plate alignment position 5 at the corresponding positions. The specific steps include the following:

[0036] The second passivation dielectric layer 3 is photolithographically formed to create a pattern corresponding to the area to be etched or corroded. Etching or corroding the second passivation dielectric layer 3 does not affect the first passivation dielectric layer 2, so that the pattern on the second passivation dielectric layer 3, from left to right, corresponds to the second gate field plate setting position 4 and the fourth gate field plate alignment position 5, respectively. Figure 4 As shown, the width of position 4 of the second-layer grid plate is 1μm to 3μm, and the width of position 5 of the fourth-layer grid plate is 2μm to 5μm.

[0037] 5) Prepare a second-layer grid plate 6 at the reserved location 4, and set a third-layer grid plate 7 on the second-layer grid plate 6, wherein the third-layer grid plate 7 partially overlaps with the first-layer grid plate 1 in the vertical projection direction. Specifically, this includes the following steps:

[0038] The third gate field pattern is formed on the device after step 4) by photolithography, followed by evaporation and lift-off. The second gate field pattern is self-aligned and formed within the second gate field pattern setting position 4 on the left side, as shown. Figure 5As shown; the third gate field plate 7 is located above and connected to the second gate field plate 6, and the two gate field plates are formed by photolithography and evaporation lift-off processes; the metal system of the second gate field plate and the metal system of the third gate field plate are the same as the metal system of the first gate field plate. The width of the second gate field plate is 1μm to 3μm and the thickness is 100nm to 500nm; the width of the third gate field plate is 3μm to 7μm and the thickness is 300nm to 1000nm.

[0039] 6) A third passivation dielectric layer 8 is deposited on the device surface after step 5), such as... Figure 6 As shown, the third passivation dielectric layer 8 can be Si3N4 or SiO2 or other dielectric materials, and its thickness is 500nm to 1500nm.

[0040] 7) A fourth-layer gate plate setting position 9 is formed on the third passivation dielectric layer 8 above the fourth-layer gate plate alignment position 5. A fourth-layer gate plate 10 is set in the fourth-layer gate plate setting position 9, and a fifth-layer gate plate 11 is formed on the upper side of the fourth-layer gate plate 10. The fifth-layer gate plate 11 partially overlaps with the third gate plate 7 in the vertical projection direction.

[0041] Furthermore, the fourth gate field plate setting position is formed by etching or corroding on the third passivation dielectric layer 8 above the fourth gate field plate alignment position 5. The fourth gate field plate 10 is then self-aligned and formed within the fourth gate field plate setting position using an evaporation and stripping process. Figure 7 As shown, the fifth gate field plate pattern is formed by photolithography. The fifth gate field plate 11 is located above and connected to the fourth gate field plate 10. The five gate field plates are fabricated and are all connected to the same potential. The metal system of the fourth gate field plate 10 and the fifth gate field plate 11 is the same as that of the first gate field plate. The width of the fourth gate field plate is 1μm to 3μm and the thickness is 100nm to 500nm. The width of the fifth gate field plate is 5μm to 10μm and the thickness is 500nm to 3000nm.

[0042] 8) By etching or corroding, the dielectric material above the source electrode 12 and drain electrode 13 is removed, thus completing the fabrication of a high-voltage GaN MIS-HEMT device with a five-layer gate field plate, such as... Figure 8 As shown.

[0043] Correspondingly, such as Figure 8As shown, this embodiment of the invention also discloses a high-voltage GaN MIS-HEMT device, including a device body. The device body includes a substrate layer 14, a GaN buffer layer 15 formed on the upper surface of the substrate layer 14, an AlGaN barrier layer 16 formed on the upper surface of the GaN buffer layer 15, a gate insulating layer 17 formed on the upper side of the AlGaN barrier layer 16, a gate electrode 18 embedded in the gate insulating layer 17, and a drain electrode 13 and a source electrode 12 embedded in the AlGaN barrier layer 16. A first gate field plate 1 is formed on the upper side of the gate electrode 18 on the device body, covering the gate electrode 18. A first passivation dielectric layer 2 is located between the source electrode 12 and the drain electrode 13 of the device, and covers the first gate field plate 1. A second passivation dielectric layer 3 is formed on the upper surface of the first passivation dielectric layer 2. A second gate field plate setting position 4 and a fourth gate field plate alignment position 5 are formed on the upper surface of the second passivation dielectric layer 3. A second gate field plate 6 is disposed within the second gate field plate setting position 4. A third gate field plate 7 is connected to the second gate field plate 6, and the third gate field plate... Plate 7 and the first layer gate plate 1 partially overlap in the vertical projection direction. The third passivation dielectric layer 8 covers the exposed second passivation dielectric layer 3, the fourth layer gate plate alignment position 5, and the third layer gate plate 7. A fourth layer gate plate setting position is formed on the third passivation dielectric layer 8 corresponding to the fourth layer gate plate alignment position 5. A fourth layer gate plate 10 is set in the fourth layer gate plate setting position. The fifth layer gate plate 11 is connected to the fourth layer gate plate 10 and is located on the upper surface of the third passivation dielectric layer 8. The fifth layer gate plate 11 and the third layer gate plate 7 partially overlap in the vertical projection direction.

[0044] The method described in this invention achieves the purpose of fabricating a five-layer gate field plate by etching or corroding the reserved gate field plate position. The process is simple and reduces the steps of photolithography and evaporation stripping. It can not only reduce the electric field strength and increase the breakdown voltage to 1500V by using a five-layer gate field plate, but also balance the electric field distribution of each field plate, thereby improving the reliability of the device.

Claims

1. A method for fabricating a high-voltage GaN MIS-HEMT device, the method comprising: Comprising the following steps: ​ 1) preparing a gateless field plate GaN MIS-HEMT device; 2) preparing a first layer of gate field plate (1) on the gateless field plate GaN MIS-HEMT device; 3) sequentially depositing a first passivation medium layer (2) and a second passivation medium layer (3) on the surface of the GaN MIS-HEMT device with the first layer of gate field plate (1); 4) etching or corroding the second passivation medium layer (3) and stopping at the first passivation medium layer (2), leaving a second layer of gate field plate setting position (4) and a fourth layer of gate field plate alignment position (5) at the corresponding position; 5) preparing a second layer of gate field plate (6) at the reserved second layer of gate field plate setting position (4), and setting a third layer of gate field plate (7) on the second layer of gate field plate (6), and the third layer of gate field plate (7) has a partial overlap with the first layer of gate field plate (1) in the up-down projection direction; 6) depositing a third passivation medium layer (8) on the surface of the device after step 5); 7) forming a fourth layer of gate field plate setting position (9) on the third passivation medium layer (8) on the upper side of the fourth layer of gate field plate alignment position (5), setting a fourth layer of gate field plate (10) in the fourth layer of gate field plate setting position (9), and forming a fifth layer of gate field plate (11) on the upper side of the fourth layer of gate field plate (10), the fifth layer of gate field plate (11) has a partial overlap with the third layer of gate field plate (7) in the up-down projection direction; 8) by etching or corroding, removing the medium above the source electrode (12) and the drain electrode (13), completing the preparation of the high-voltage GaN MIS-HEMT device with five layers of gate field plate.

2. The method of fabricating a high voltage GaN MIS-HEMT device as claimed in claim 1, wherein, The step 1) specifically comprises the following steps: Epitaxially growing a GaN buffer layer (15) on a substrate layer (14), growing an AlGaN barrier layer (16) on the GaN buffer layer (15), thereby forming a two-dimensional electron gas (2DEG); growing a gate insulating layer (17) on the surface of the AlGaN barrier layer (16), etching or corroding the gate insulating layer (17) to form a gate pattern, and leaving a certain thickness of the gate insulating layer (17) under the gate electrode (18), and evaporating and peeling to prepare the gate electrode (18); etching or corroding the gate insulating layer (17) and part of the AlGaN barrier layer (16) to form a source-drain pattern on the AlGaN barrier layer (16), and evaporating and peeling to prepare the source electrode (12) and the drain electrode (13).

3. The method of fabricating a high voltage GaN MIS-HEMT device as claimed in claim 1, wherein, The step 2) specifically comprises the following steps: After step 1), the surface of the device is photolithographed to form a first layer of gate field plate pattern, then evaporated and peeled to form a first layer of gate field plate (1) on the first layer of gate field plate pattern, the first layer of gate field plate (1) metal is Ti / Al, Ti / Ta / Al or Ti / Al / Ni / Au metal system, the metal thickness is 300 nm~1000 nm, and the field plate width is 1 μm ~3 μm.

4. The method of fabricating a high voltage GaN MIS-HEMT device as claimed in claim 1, wherein, In the step 3), the first passivation medium layer (2) and the second passivation medium layer (3) are Si3N4 or SiO2, the thickness of the first passivation medium layer (2) is 300 nm-800 nm, and the thickness of the second passivation medium layer (3) is 100 nm-500 nm.

5. The method of fabricating a high voltage GaN MIS-HEMT device as claimed in claim 1, wherein, The step 4) specifically comprises the following steps: The second passivation medium layer (3) is photoetched to form a pattern corresponding to the etching or corrosion required, the second passivation medium layer (3) is etched or corroded without affecting the first passivation medium layer (2), so that the pattern on the second passivation medium layer (3) from left to right is the second layer gate field plate setting position (4) and the fourth layer gate field plate alignment position (5), wherein the width of the second layer gate field plate setting position (4) is 1-3 μm, and the width of the fourth layer gate field plate alignment position (5) is 2-5 μm.

6. The method of fabricating a high voltage GaN MIS-HEMT device as claimed in claim 1, wherein, The step 5) specifically comprises the following steps: The third layer gate field plate pattern is photoetched on the device after step 4), and the second layer gate field plate is self-aligned to form in the left second layer gate field plate setting position (4) by evaporation and stripping; the third layer gate field plate (7) is located above the second layer gate field plate (6) and connected thereto, and two layer gate field plates are formed by the photoetching and evaporation and stripping process; the metal system of the second layer gate field plate and the third layer gate field plate is the same as that of the first layer gate field plate, the width of the second layer gate field plate is 1-3 μm, and the thickness is 100-500 nm; the width of the third layer gate field plate is 3-7 μm, and the thickness is 300-1000 nm.

7. The method of fabricating a high voltage GaN MIS-HEMT device as claimed in claim 1, wherein, In the step 6): The third passivation medium layer (8) is Si3N4 or SiO2, and the thickness is 500-1500 nm.

8. The method of fabricating a high voltage GaN MIS-HEMT device as claimed in claim 1, wherein, The step 7) specifically comprises the following steps: The fourth layer gate field plate setting position is etched or corroded on the upper side of the third passivation medium layer (8) of the fourth layer gate field plate alignment position (5), the fourth layer gate field plate (10) is self-aligned to form in the fourth layer gate field plate setting position by evaporation and stripping process, the fifth layer gate field plate pattern is photoetched, the fifth layer gate field plate (11) is located above the fourth layer gate field plate (10) and connected thereto, and the five layer gate field plates are prepared, and they are connected to the same potential; the metal system of the fourth layer gate field plate (10) and the fifth layer gate field plate (11) is the same as that of the first layer gate field plate, the width of the fourth layer gate field plate is 1-3 μm, and the thickness is 100-500 nm; the width of the fifth layer gate field plate is 5-10 μm, and the thickness is 500-3000 nm.

9. A high voltage GaN MIS-HEMT device comprising a device body, characterized by: The upper side of the gate electrode (18) on the device body is formed with a first layer of gate field plate (1), which covers the gate electrode (18), a first passivation dielectric layer (2) is located between the source electrode (12) and the drain electrode (13) of the device and covers the first layer of gate field plate (1), the upper surface of the first passivation dielectric layer (2) is formed with a second passivation dielectric layer (3), the upper surface of the second passivation dielectric layer (3) is formed with a second layer of gate field plate setting position (4) and a fourth layer of gate field plate alignment position (5), the second layer of gate field plate setting position (4) is provided with a second layer of gate field plate (6), a third layer of gate field plate (7) is connected with the second layer of gate field plate (6), and the third layer of gate field plate (7) has partial overlap with the first layer of gate field plate (1) in the up-down projection direction, a third passivation dielectric layer (8) covers the exposed second passivation dielectric layer (3), the fourth layer of gate field plate alignment position (5) and the third layer of gate field plate (7), and the third passivation dielectric layer (8) corresponding to the fourth layer of gate field plate alignment position (5) is formed with a fourth layer of gate field plate setting position, the fourth layer of gate field plate setting position is provided with a fourth layer of gate field plate (10), a fifth layer of gate field plate (11) is connected with the fourth layer of gate field plate (10) and located on the upper surface of the third passivation dielectric layer (8), and the fifth layer of gate field plate (11) has partial overlap with the third layer of gate field plate (7) in the up-down projection direction.

10. The high voltage GaN MIS-HEMT device of claim 9, wherein, The device body includes a substrate layer (14), the upper surface of the substrate layer (14) is formed with a GaN buffer layer (15), the upper surface of the GaN buffer layer (15) is formed with an AlGaN barrier layer (16), the upper side of the AlGaN barrier layer (16) is formed with a gate insulating layer (17), a gate electrode (18) is embedded in the gate insulating layer (17), and a drain electrode (13) and a source electrode (12) are embedded in the AlGaN barrier layer (16).

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