Slew rate control device and slew rate control method

Abstract

A slew rate control device and a slew rate control method are disclosed. The slew rate control device includes a signal generating circuit, a comparison circuit, and a control circuit. The signal generating circuit is configured to generate a first voltage signal and a second voltage signal, both having a slew rate, and the first voltage signal and the second voltage signal are a pair of differential signals. The comparison circuit is configured to output an enable signal according to a relative position relationship between an eye crossing point of the pair of differential signals and a signal edge of a reference clock. The control circuit is configured to generate at least one control signal according to the enable signal to control the signal generating circuit, so that the signal generating circuit can change the slew rate of the first voltage signal and the second voltage signal according to the at least one control signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a Slew Rate control device and a Slew Rate control method, in particular to a Slew Rate control device and a Slew Rate control method for changing Slew Rate according to the relative position relationship between the Eye Crossing Point of a pair of differential signals and the signal edge of a reference clock. BACKGROUND

[0002] Slew Rate refers to the voltage change per unit time, and can be intuitively divided into rising Slew Rate and falling Slew Rate. However, in the control of Slew Rate, it is usually necessary to match a complex circuit to detect Slew Rate, and to provide a voltage source or a current source with adjustable output capability to change Slew Rate. SUMMARY

[0003] In view of the deficiencies of the prior art, the embodiments of the present application provide a Slew Rate control device, comprising a signal generation circuit, a comparison circuit and a control circuit. The signal generation circuit is used to generate a first voltage signal and a second voltage signal both having a Slew Rate, and the first voltage signal and the second voltage signal are a pair of differential signals. The comparison circuit is used to output an enable signal according to the relative position relationship between the Eye Crossing Point of the pair of differential signals and the signal edge of a reference clock. The control circuit is coupled between the signal generation circuit and the comparison circuit, and is used to generate at least one control signal according to the enable signal to control the signal generation circuit, so that the signal generation circuit can change the Slew Rate of the first voltage signal and the second voltage signal according to the at least one control signal.

[0004] In addition, the embodiments of the present application provide a Slew Rate control method applicable to a Slew Rate control device, comprising the following steps. First, a signal generation circuit is configured to generate a first voltage signal and a second voltage signal both having a Slew Rate, and the first voltage signal and the second voltage signal are a pair of differential signals. Second, a comparison circuit is configured to output an enable signal according to the relative position relationship between the Eye Crossing Point of the pair of differential signals and the signal edge of a reference clock. Third, a control circuit is configured to generate at least one control signal according to the enable signal to control the signal generation circuit, so that the signal generation circuit can change the Slew Rate of the first voltage signal and the second voltage signal according to the at least one control signal.

[0005] In order to further understand the features and technical contents of the present application, please refer to the following detailed description of the present application and the accompanying drawings, however, the provided drawings are only used for reference and illustration, and are not used to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a function block schematic diagram of a slew rate control device according to an embodiment of the present application.

[0007] Figure 2 is a timing diagram of a first voltage signal, a second voltage signal, a reference clock and an enable signal according to an embodiment of the present application.

[0008] Figure 3 is a circuit schematic diagram of a comparison circuit according to an embodiment of the present application.

[0009] Figure 4 is a circuit schematic diagram of a signal generating circuit according to an embodiment of the present application.

[0010] Figure 5 is a step flow chart of a counting procedure of a control circuit according to an enable signal according to an embodiment of the present application.

[0011] Figure 6 is a step flow chart of a slew rate control method according to an embodiment of the present application. DETAILED DESCRIPTION

[0012] The present application will be described in detail by specific embodiments, and the advantages and effects of the present application can be understood by the content provided in the present specification. The present application can be implemented or applied by other different embodiments, and each detail in the present specification can be modified and changed in various ways based on different views and applications without departing from the concept of the present application. In addition, the drawings of the present application are only simple schematic illustrations, and are not drawn according to actual sizes, and it is declared in advance. The following embodiments will further illustrate the related technical content of the present application in detail, but the content provided is not used to limit the protection scope of the present application.

[0013] It should be understood that although the terms of "first", "second", "third" and the like can be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one element from another element, or one signal from another signal. In addition, the term "or" used herein can include any one or more combinations of the associated listed items as appropriate.

[0014] Please refer to Figure 1 , Figure 1 is a function block schematic diagram of a slew rate control device according to an embodiment of the present application. As shown in Figure 1As shown, the slew rate control device 1 includes a signal generation circuit 10, a comparison circuit 12, and a control circuit 14. The control circuit 14 is coupled between the comparison circuit 12 and the signal generation circuit 10. The signal generation circuit 10 generates a first voltage signal VCCP and a second voltage signal VCCN, each having a slew rate, and the first voltage signal VCCP and the second voltage signal VCCN are a pair of differential signals. That is, when the first voltage signal VCCP transitions from a logic high level to a logic low level, the second voltage signal VCCN transitions from a logic low level to a logic high level, and at this time, the falling edge slew rate of the first voltage signal VCCP is equal to the rising edge slew rate of the second voltage signal VCCN. Conversely, when the first voltage signal VCCP transitions from a logic low level to a logic high level, the second voltage signal VCCN transitions from a logic high level to a logic low level, and at this time, the rising edge slew rate of the first voltage signal VCCP is equal to the falling edge slew rate of the second voltage signal VCCN.

[0015] Please refer to this as well. Figure 2 , Figure 2 This is a timing diagram of the first voltage signal VCCP, the second voltage signal VCCN, the reference clock REF_CLK, and the enable signal EN according to an embodiment of the present invention. Figure 2 As shown, this invention can assume that the first voltage signal VCCP initially generated by the signal generation circuit 10 is at a logic high level, and the reference clock REF_CLK is at a logic low level at this time. Therefore, the eye intersection point C of the pair of differential signals (i.e., the first voltage signal VCCP and the second voltage signal VCCN) can be taken as the intersection of the falling edge of the first voltage signal VCCP and the rising edge of the second voltage signal VCCN, but this invention is not limited thereto. In this case, this invention can also assume that when the comparator circuit 12 determines that the eye intersection point C appears to the left of the rising edge of the reference clock REF_CLK, the comparator circuit 12 outputs a logic high level enable signal EN, and the control circuit 14 generates at least one control signal CS according to the logic high level enable signal EN to control the signal generation circuit 10, so that the signal generation circuit 10 can change the slew rate of the first voltage signal VCCP and the second voltage signal VCCN according to the at least one control signal CS.

[0016] from Figure 2It can be seen that at this time, the control circuit 14 needs to generate at least one control signal CS to control the signal generation circuit 10 to reduce the slew rate of the first voltage signal VCCP and the second voltage signal VCCN, so that the eye cross point C can appear to the right of the rising edge of the reference clock REF_CLK. Therefore, when the comparator circuit 12 determines that the eye cross point C appears to the right of the rising edge of the reference clock REF_CLK, the comparator circuit 12 outputs a logic low-level enable signal EN. It should be noted that the above is an explanation of the implementation of the comparator circuit 12 through a specific embodiment, but the present invention is not limited thereto. In summary, the comparator circuit 12 can be used to output the enable signal EN according to the relative positional relationship between the eye cross point of the pair of differential signals (i.e., the first voltage signal VCCP and the second voltage signal VCCN) and the signal edge of the reference clock REF_CLK. In addition, the control circuit 14 is used to generate at least one control signal CS according to the enable signal EN to control the signal generation circuit 10, so that the signal generation circuit 10 can change the slew rate of the first voltage signal VCCP and the second voltage signal VCCN according to the at least one control signal CS.

[0017] However, in order to gain a deeper understanding of the comparator circuit 12, the following explanation uses a specific circuit to illustrate its use. Figure 2 The present invention describes the implementation of the comparator circuit 12, but is not limited thereto. Please refer to the following embodiments: Figure 3 , Figure 3 This is a circuit diagram of the comparison circuit 12 according to an embodiment of the present invention. Figure 3 As shown, the comparator circuit 12 may include an operational amplifier 120, a flip-flop 122, and an inverter 124. The operational amplifier 120 receives a first voltage signal VCCP and a second voltage signal VCCN, and outputs a comparison signal CP. If... Figure 2 Taking the embodiment as an example, the non-inverting input and the inverting input of the operational amplifier 120 receive a first voltage signal VCCP and a second voltage signal VCCN, respectively. When the first voltage signal VCCP is less than the second voltage signal VCCN, the output of the operational amplifier 120 outputs a logic low comparison signal CP. That is, in... Figure 2 After the eye crossover point C, the operational amplifier 120 outputs a logic low-level comparison signal CP until the first voltage signal VCCP is greater than the second voltage signal VCCN.

[0018] The data input D and clock input CK of flip-flop 122 receive the comparison signal CP and the reference clock REF_CLK, respectively. When the reference clock REF_CLK transitions from logic low to logic high, flip-flop 122 outputs an output signal OP equal to the comparison signal CP. That is, when... Figure 2When the eye-crossing point C of the output signal OP appears on the left side of the rising edge of the reference clock REF CLK, the output signal OP is equal to the comparison signal CP of the logic low level. In addition, the inverter 124 is coupled to the flip-flop 122 for receiving the output signal OP and outputs the reversed output signal OP as the enable signal EN. Therefore, when the output signal OP is equal to the comparison signal CP of the logic low level, the comparison circuit 12 outputs the enable signal EN of the logic high level, and the control circuit 14 is able to generate at least one control signal CS according to the enable signal EN of the logic high level to control the signal generating circuit 10, so that the signal generating circuit 10 is able to change the slew rate of the first voltage signal VCCP and the second voltage signal VCCN according to the at least one control signal CS. Since the operation principle of the operational amplifier 120, the flip-flop 122 and the inverter 124 is well known to those skilled in the art, the details thereof will not be described herein.

[0019] In another aspect, referring to Figure 4 , Figure 4 is a circuit schematic diagram of the signal generating circuit 10 of the embodiment of the present application. As shown in Figure 4 , the signal generating circuit 10 can include the phase interpolator 100 and the phase interpolator 102 for outputting the first voltage signal VCCP and the second voltage signal VCCN through the node P1 and the node P2 respectively, and the phase interpolator 100 and the phase interpolator 102 each include a plurality of circuit branches. In the embodiment, the phase interpolator 100 includes the circuit branches 40_0~40_N-1, the phase interpolator 102 includes the circuit branches 42_0~42_N-1, and N is an integer greater than 1, but the present application does not limit the specific value thereof. In addition, each of the circuit branches in the phase interpolator 100 or the phase interpolator 102 includes the first switch, the first current source, the second current source and the second switch connected in series between the supply voltage VCC and the ground voltage GND, and the node P1 or the node P2 is coupled between the first current source and the second current source.

[0020] For example, the circuit branch 40_0 of the phase interpolator 100 includes a first switch 401_0, a first current source 402_0, a second current source 403_0, and a second switch 404_0 connected in series between the supply voltage VCC and the ground voltage GND, and the node Pl is coupled between the first current source 402_0 and the second current source 403_0, and so on, the circuit branch 40_N-1 of the phase interpolator 100 includes a first switch 401_N-1, a first current source 402_N-1, a second current source 403_N-1, and a second switch 404_N-1 connected in series between the supply voltage VCC and the ground voltage GND, and the node Pl is coupled between the first current source 402_N-1 and the second current source 403_N-1. In contrast, the circuit branch 42_0 of the phase interpolator 102 includes a first switch 421_0, a first current source 422_0, a second current source 423_0, and a second switch 424_0 connected in series between the supply voltage VCC and the ground voltage GND, and the node P2 is coupled between the first current source 422_0 and the second current source 423_0, and so on, the circuit branch 42_N-1 of the phase interpolator 102 includes a first switch 421_N-1, a first current source 422_N-1, a second current source 423_N-1, and a second switch 424_N-1 connected in series between the supply voltage VCC and the ground voltage GND, and the node P2 is coupled between the first current source 422_N-1 and the second current source 423_N-1.

[0021] In this embodiment, phase interpolator 100 can also include a capacitor CI coupled between node PI and ground voltage GND, and phase interpolator 102 can also include a capacitor C2 coupled between node P2 and ground voltage GND. In this case, phase interpolator 100 can transition first voltage signal VCCP from a logic high level to a logic low level by turning on second switches 404_0-404_N-1 to discharge capacitor CI using second current sources 403_0-403_N-1. At the same time, phase interpolator 102 can transition second voltage signal VCCN from a logic low level to a logic high level by turning on first switches 421_0-421_N-1 to charge capacitor C2 using first current sources 422_0-422_N-1. Assuming that each capacitor has an equal amount of charge and each current source provides the same amount of current, since the falling edge slew rate of first voltage signal VCCP is equal to the rising edge slew rate of second voltage signal VCCN at this time, at least one control signal CS generated by control circuit 14 can include N-bit first control signal SW1 [N-1 :0] for controlling second switches 404_0-404_N-1 and first switches 421_0-421_N-1. For example, first bit SW1 [0] of first control signal is used to control second switch 404_0 and first switch 421_0, and so on, N-bit SW1 [N-0] of first control signal is used to control second switch 404_N-1 and first switch 421_N-1.

[0022] Phase interpolator 100 can also transition first voltage signal VCCP from a logic low level to a logic high level by turning on first switches 401_0-401_N-1 to charge capacitor CI using first current sources 402_0-402_N-1. At the same time, phase interpolator 102 can transition second voltage signal VCCN from a logic high level to a logic low level by turning on second switches 424_0-424_N-1 to discharge capacitor C2 using second current sources 423_0-423_N-1. Assuming that each capacitor has an equal amount of charge and each current source provides the same amount of current, since the rising edge slew rate of first voltage signal VCCP is equal to the falling edge slew rate of second voltage signal VCCN at this time, at least one control signal CS generated by control circuit 14 can also include N-bit second control signal SW2 [N-1 :0] for controlling first switches 401_0-401_N-1 and second switches 424_0-424_N-1. For example, first bit SW2 [0] of second control signal is used to control first switch 401_0 and second switch 424_0, and so on, N-bit SW2 [N-0] of second control signal is used to control first switch 401_N-1 and second switch 424_N-1.

[0023] Therefore, if the falling edge slew rate of the first voltage signal VCCP is to be adjusted, the control circuit 14 can control the number of the second switches 404_0~404_N-1 in the phase interpolator 100 to be turned on to be reduced, so that the efficiency of discharging the capacitor C1 is deteriorated. At the same time, the control circuit 14 can also control the number of the first switches 421_0~421_N-1 in the phase interpolator 102 to be turned on to be reduced, so that the efficiency of charging the capacitor C2 is deteriorated, thereby adjusting the rising edge slew rate of the second voltage signal VCCN. In addition, if the rising edge slew rate of the first voltage signal VCCP is to be adjusted, the control circuit 14 can control the number of the first switches 401_0~401_N-1 in the phase interpolator 100 to be turned on to be reduced, so that the efficiency of charging the capacitor C1 is deteriorated. At the same time, the control circuit 14 can also control the number of the second switches 424_0~424_N-1 in the phase interpolator 102 to be turned on to be reduced, so that the efficiency of discharging the capacitor C2 is deteriorated, thereby adjusting the falling edge slew rate of the second voltage signal VCCN. Therefore, compared with the prior art of providing a voltage source or a current source with adjustable output capability to change the slew rate, the slew rate control device 1 of the present application can directly change the slew rate by controlling the number of the switches in each phase interpolator to be turned on.

[0024] In this case, the control circuit 14 can also be used to count according to the enable signal EN to generate a count value CV Figures 1 to 4 (not shown), and the count value CV is used to represent the number of the switches in each phase interpolator to be turned on which is to be controlled by the control circuit 14, but the present application is not limited to this specific embodiment, and therefore the control circuit 14 can also generate the first control signal SW1[N-1:0] and the second control signal SW2[N-1:0] according to the count value CV. For the convenience of the following description, the present application can represent the count value CV by N bits, and the number of the bits with the value of 1 represents the number of the switches in each phase interpolator to be turned on which is to be controlled, and therefore from the above embodiment, the N bits of the count value CV are initially all 1. In addition, the following will describe the specific embodiment of the control circuit 14 for generating the count value CV, but the present application is not limited to this specific embodiment. Figure 2 Please refer to the above embodiment of the phase interpolator 100 and the phase interpolator 102 for the details of the phase interpolator. Figure 5 Figure 5 is a flow chart of the steps of counting according to the enable signal EN by the control circuit 14 of the embodiment of the present application. As shown in Figure 5 , in step S510, the control circuit 14 receives the enable signal EN, and in step S520, it is judged whether the enable signal EN is at the logic high level.

[0025] If yes, it represents Figure 2 ​The eye cross point C appears to the left of the rising edge of the reference clock REF_CLK. Therefore, the control circuit 14 can execute step S530 to decrement the count value CV by 1, that is, control the reduction of the number of on switches to lower the slew rate of the first voltage signal VCCP and the second voltage signal VCCN, so that the eye cross point C appears to the right of the rising edge of the reference clock REF_CLK. If not, it means Figure 2 The eye cross point C has appeared to the right of the rising edge of the reference clock REF_CLK, therefore control circuit 14 can execute step S540 to stop counting. Since the relevant details have been described above, they will not be repeated here. Finally, please refer to... Figure 6 , Figure 6 This is a flowchart of the steps of the slewing rate control method according to an embodiment of the present invention. Figure 6 The slew rate control method can be applied to Figure 1 The slew rate control device 1, therefore please refer to it as well. Figure 1 To facilitate understanding.

[0026] like Figure 6 As shown, in step S610, a signal generation circuit 10 is configured to generate a first voltage signal VCCP and a second voltage signal VCCN, both having a slew rate, and the first voltage signal VCCP and the second voltage signal VCCN are a pair of differential signals. Next, in step S620, a comparator circuit 12 is configured to output an enable signal EN based on the relative position of the eye crossover point of the pair of differential signals and the signal edge of the reference clock REF_CLK. Then, in step S630, a control circuit 14 is configured to generate at least one control signal CS based on the enable signal EN to control the signal generation circuit 10, such that the signal generation circuit 10 can change the slew rate of the first voltage signal VCCP and the second voltage signal VCCN according to the at least one control signal CS. Since the relevant details have already been described above, they will not be repeated here.

[0027] In summary, the slew rate control device and method provided by this invention can change the slew rate based on the relative positional relationship between the eye intersection of a pair of differential signals and the signal edge of a reference clock. Furthermore, the slew rate control device of this invention can generate one voltage signal from the pair of differential signals using two phase interpolators, and each phase interpolator can charge or discharge a capacitor using a current source by turning on a switch, causing the corresponding voltage signal to transition from logic low to logic high or from logic high to logic low. Therefore, compared to the prior art that provides an adjustable voltage or current source to change the slew rate, the slew rate control device of this invention can directly change the slew rate by controlling the number of switches turned on in each phase interpolator.

[0028] The above provided content is only preferred feasible embodiments of the present application, and is not limited to the scope of claims of the present application, so that any equivalent technical changes made by applying the content of the present application specification and drawings are included in the scope of claims of the present application.

[0029] BRIEF DESCRIPTION OF DRAWINGS

[0030] 1: Slew rate control device

[0031] 10: Signal generation circuit

[0032] 12: Comparison circuit

[0033] 14: Control circuit

[0034] VCCP: First voltage signal

[0035] VCCN: Second voltage signal

[0036] REF CLK: Reference clock

[0037] EN: Enable signal

[0038] CS: Control signal

[0039] C: Eye crossing point

[0040] 120: Operational amplifier

[0041] 122: Flip-flop

[0042] 124: Inverter

[0043] CP: Comparison signal

[0044] D: Data input terminal

[0045] CK: Clock input terminal

[0046] OP: Output signal

[0047] 100, 102: Phase interpolator

[0048] P1, P2: Node

[0049] 40_0 ~ 40_N-1, 42_0 ~ 42_N-1: Circuit branch

[0050] VCC: Supply voltage

[0051] GND: Ground voltage

[0052] 401_0 ~ 401_N-1, 421_0 ~ 421_N-1: First switch

[0053] 402_0 ~ 402_N-1, 422_0 ~ 422_N-1: first current source

[0054] 403_0 ~ 403_N-1, 423_0 ~ 423_N-1: second current source

[0055] 404_0 ~ 404_N-1, 424_0 ~ 424_N-1: second switch

[0056] C1, C2: capacitor

[0057] SW1[0] ~ SW1[N-1]: first control signal

[0058] SW2[0] ~ SW2[N-1]: second control signal

[0059] S510 ~ S540, S610 ~ S630: flow step

Claims

1. A slew rate control apparatus, comprising: a signal generating circuit configured to generate a first voltage signal and a second voltage signal each having a slew rate, and the first voltage signal and the second voltage signal being a pair of differential signals; a comparison circuit configured to output an enable signal according to a relative position relationship between an eye crossing point of the pair of differential signals and a signal edge of a reference clock; and a control circuit coupled between the signal generating circuit and the comparison circuit, and configured to generate at least one control signal according to the enable signal to control the signal generating circuit, such that the signal generating circuit is capable of changing the slew rate of the first voltage signal and the second voltage signal according to the at least one control signal; wherein the signal generating circuit comprises a first phase interpolator and a second phase interpolator configured to output the first voltage signal and the second voltage signal through a first node and a second node respectively, and each of the first phase interpolator and the second phase interpolator comprises a plurality of circuit branches. 2.The slew rate control apparatus of claim 1, wherein the comparison circuit comprises: an operational amplifier configured to receive the first voltage signal and the second voltage signal, and output a comparison signal; and a flip-flop having a data input and a clock input configured to receive the comparison signal and the reference clock respectively, and output an output signal equal to the comparison signal when the reference clock is converted from a logic low level to a logic high level. 3.The slew rate control apparatus of claim 2, wherein the comparison circuit further comprises: an inverter coupled to the flip-flop and configured to receive the output signal, and output a reversed output signal as the enable signal. 4.The slew rate control apparatus of claim 1, wherein in the first phase interpolator or the second phase interpolator, each of the circuit branches comprises a first switch, a first current source, a second current source and a second switch connected in series between a supply voltage and a ground voltage, and the first node or the second node is coupled between the first current source and the second current source. 5.The slew rate control apparatus of claim 4, wherein the at least one control signal generated by the control circuit comprises a first control signal and a second control signal, the first control signal is configured to control the second switch of each of the circuit branches of the first phase interpolator and the first switch of each of the circuit branches of the second phase interpolator, and the second control signal is configured to control the first switch of each of the circuit branches of the first phase interpolator and the second switch of each of the circuit branches of the second phase interpolator. 6.The slew rate control apparatus of claim 5, wherein the control circuit is further configured to count according to the enable signal to generate a count value, and the control circuit generates the first control signal and the second control signal according to the count value. ​ ​ 7. The slew rate control device of claim 6, wherein in the step of counting by the control circuit according to the enable signal, when the control circuit judges that the enable signal is at a logic high level, the control circuit decreases the count value by 1, and when the control circuit judges that the enable signal is at a logic low level, the control circuit stops counting.

8. A slew rate control method, applicable to a slew rate control device, comprising: configuring a signal generation circuit to generate a first voltage signal and a second voltage signal, both having a slew rate, and the first voltage signal and the second voltage signal being a pair of differential signals; configuring a comparison circuit to output an enable signal according to the relative position relationship between the eye crossing point of the pair of differential signals and the signal edge of a reference clock; and configuring a control circuit to generate at least one control signal according to the enable signal to control the signal generation circuit, so that the signal generation circuit can change the slew rate of the first voltage signal and the second voltage signal according to the at least one control signal; wherein the signal generation circuit comprises a first phase interpolator and a second phase interpolator for outputting the first voltage signal and the second voltage signal through a first node and a second node respectively, and the first phase interpolator and the second phase interpolator each comprise a plurality of circuit branches.

9. The slew rate control method of claim 8, wherein the comparison circuit comprises: an operational amplifier for receiving the first voltage signal and the second voltage signal and outputting a comparison signal; and a flip-flop, the data input end and the clock input end of the flip-flop receiving the comparison signal and the reference clock respectively, and when the reference clock changes from a logic low level to a logic high level, the flip-flop outputs an output signal equal to the comparison signal. ​

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