Calibration method, calibration device and multi-phase clock circuit

Abstract

This application provides a calibration method, a calibration device, and a multi-phase clock circuit. The method includes: selecting each phase clock signal from a multi-phase clock signal as a respective master clock signal and selecting a corresponding clock signal as a corresponding auxiliary clock signal according to a first preset rule; selecting each phase clock signal from the multi-phase clock signal as a respective master clock signal and selecting a corresponding clock signal as a corresponding auxiliary clock signal according to a second preset rule; obtaining the time difference between each master clock signal and the corresponding auxiliary clock signal under the first and second preset rules; determining the delay adjustment amount of each master clock signal based on the time difference, and obtaining the phase error between the multi-phase clock signals based on the delay adjustment amount; obtaining the calibration amount of the multi-phase clock signals based on the phase error. The phase calibration amount obtained based on the calibration method can be used to calibrate the multi-phase clock signals.

Description

Technical Field

[0001] This application belongs to the field of electronic circuits, and in particular relates to a calibration method, calibration device and multiphase clock circuit. Background Technology

[0002] In typical multiphase clock circuits, multiphase clock signals are usually output from a PLL (Phase Locked Loop) and driven by a multiplexer to meet the clock requirements of subsequent circuits. However, in practical applications, the inventors discovered that due to differences in clock trees and physical implementations, there is an error between the phase difference of the final clock output and the reference phase difference. Therefore, how to calibrate the phase difference of multiphase clock circuits has become one of the technical problems that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a calibration method, calibration device and multiphase clock circuit to solve the above-mentioned problems in the prior art.

[0004] To achieve the above and other related objectives, a first aspect of this application provides a calibration method, the calibration method comprising: selecting each phase clock signal in a multi-phase clock signal as a respective master clock signal and selecting a corresponding clock signal as a corresponding auxiliary clock signal according to a first preset rule, wherein the reference phase difference between each master clock signal and the corresponding auxiliary clock signal under the first preset rule is a first preset value; selecting each phase clock signal in the multi-phase clock signal as a respective master clock signal and selecting a corresponding clock signal as a corresponding auxiliary clock signal according to a second preset rule, wherein the reference phase difference between each master clock signal and the corresponding auxiliary clock signal under the second preset rule is a second preset value, wherein the first preset value is not equal to the second preset value; obtaining the time difference between each master clock signal and the corresponding auxiliary clock signal under the first preset rule and the second preset rule; determining the delay adjustment amount of each master clock signal according to the time difference, and obtaining the phase error between the multi-phase clock signals according to the delay adjustment amount; and obtaining the calibration amount of the multi-phase clock signals according to the phase error.

[0005] In one embodiment of the first aspect, determining the delay adjustment amount of each master clock signal based on the time difference includes: obtaining the frequency signal corresponding to the time difference based on the time difference; and obtaining the delay adjustment amount of each master clock signal based on the frequency signal.

[0006] In one embodiment of the first aspect, the method for obtaining the phase error between the multi-phase clock signals based on the delay adjustment amount is as follows: Where Δt(k+1,k) is the phase error between the k-th phase clock signal and the (k+1)-th phase clock signal, m+1 is the number of phases of the multi-phase clock signal, and c A (n) represents the delay adjustment amount of the nth phase clock signal under the first preset rule, c B (n) represents the delay adjustment amount of the nth phase clock signal under the second preset rule.

[0007] In one embodiment of the first aspect, the method for obtaining the calibration amount of the multi-phase clock signal based on the phase error is as follows: Where c(k) is the calibration value of the k-th phase clock signal.

[0008] In one embodiment of the first aspect, the first preset value is 2×π / (m+1), and the second preset value is 4×π / (m+1), where m+1 is the number of phases of the multi-phase clock signal.

[0009] A second aspect of this application provides a calibration apparatus, comprising: a main selector for receiving a multi-phase clock signal and, under the control of a controller, selecting a phase clock signal from the multi-phase clock signal and outputting it as a main clock signal; an auxiliary selector for receiving the multi-phase clock signal and, under the control of the controller, selecting a corresponding phase clock signal from the multi-phase clock signal and outputting it as an auxiliary clock signal, wherein the reference phase difference between the main clock signal and the auxiliary clock signal is a preset value, and the preset value is not equal to 0; a time difference acquisition module for receiving the main clock signal and the auxiliary clock signal and acquiring the time difference between the main clock signal and the auxiliary clock signal; a controller connected to the main selector, the auxiliary selector, and the time difference acquisition module, for determining a delay adjustment amount for the main clock signal based on the time difference between the main clock signal and the auxiliary clock signal; and a delay adjustment module connected to the main selector and the controller, for adjusting the delay of the main clock signal according to the delay adjustment amount, such that the phase difference between the main clock signal and the auxiliary clock signal is equal to or close to the preset value.

[0010] In one embodiment of the second aspect, the controller is further configured to control the main selector to select each phase clock signal in the multi-phase clock signals as a respective main clock signal according to a first preset rule, and to control the auxiliary selector to select a corresponding clock signal as a corresponding auxiliary clock signal, and to control the main selector to select each phase clock signal in the multi-phase clock signals as a respective main clock signal according to a second preset rule, and to control the auxiliary selector to select a corresponding clock signal as a corresponding auxiliary clock signal; wherein, under the first preset rule, the reference phase difference between each main clock signal and the corresponding auxiliary clock signal is a first preset value, and under the second preset rule, the reference phase difference between each main clock signal and the corresponding auxiliary clock signal is a second preset value, and the first preset value is different from the second preset value; the time difference acquisition module acquires the time difference between each main clock signal and the corresponding auxiliary clock signal under the first preset rule and the second preset rule, the controller determines the delay adjustment amount of each main clock signal based on the time difference, obtains the phase error between the multi-phase clock signals according to the delay adjustment amount, and obtains the calibration amount of the multi-phase clock signals according to the phase error.

[0011] In one embodiment of the second aspect, the calibration device further includes a frequency conversion module; the frequency conversion module is connected between the time difference acquisition module and the controller, and is used to receive the time difference between the master clock signal and the corresponding auxiliary clock signal, and to acquire the frequency signal corresponding to the time difference according to the time difference; the controller acquires the delay adjustment amount of each master clock signal according to the frequency signal.

[0012] In one embodiment of the second aspect, the controller is specifically configured to obtain the phase error between the multi-phase clock signals according to the following formula: Where Δt(k+1,k) is the phase error between the k-th phase clock signal and the (k+1)-th phase clock signal, m+1 is the number of phases of the multi-phase clock signal, and c A (n) represents the delay adjustment amount of the nth phase clock signal under the first preset rule, c B (n) represents the delay adjustment amount of the nth phase clock signal under the second preset rule.

[0013] In one embodiment of the second aspect, the controller is specifically configured to obtain the calibration amount of the multi-phase clock signal according to the following formula: Where c(k) is the calibration value of the k-th phase clock signal.

[0014] In one embodiment of the second aspect, the delay adjustment module is connected between the output of the main selector and the input of the time difference acquisition module.

[0015] In one embodiment of the second aspect, each phase clock signal in the multi-phase clock signal is connected to a delay adjustment module between itself and the corresponding input of the master selector.

[0016] In one embodiment of the second aspect, the first preset value is 2×π / (m+1), and the second preset value is 4×π / (m+1), where m+1 is the number of phases of the multi-phase clock signal.

[0017] A third aspect of this application provides a multiphase clock circuit, comprising: a clock signal generation circuit for generating multiphase clock signals; a main selector for receiving the multiphase clock signals and, under the control of a controller, selecting one phase clock signal from the multiphase clock signals and outputting it as a main clock signal; and an auxiliary selector for receiving the multiphase clock signals and, under the control of the controller, selecting a corresponding phase clock signal from the multiphase clock signals and outputting it as an auxiliary clock signal, wherein the reference phase difference between the main clock signal and the auxiliary clock signal is a preset value, and the preset value is not equal to 0. The system comprises: a time difference acquisition module for receiving the master clock signal and the auxiliary clock signal and acquiring the time difference between them; a controller connected to the master selector, the auxiliary selector, and the time difference acquisition module for determining a delay adjustment amount for the master clock signal based on the time difference between them; and a delay adjustment module connected to the master selector and the controller for adjusting the delay of the master clock signal based on the delay adjustment amount, such that the phase difference between the master clock signal and the auxiliary clock signal is equal to or close to the preset value.

[0018] As described above, the calibration method in one or more embodiments of this application has the following beneficial effects:

[0019] The calibration method determines the delay adjustment amount of each master clock signal by obtaining the time difference between each master clock signal and the corresponding auxiliary clock signal under the first preset rule and the second preset rule, and obtains the phase error between the multi-phase clock signals based on the delay adjustment amount, and then obtains the calibration amount of the multi-phase clock signals based on the phase error, and can realize the phase calibration of the multi-phase clock signals based on the calibration amount. Attached Figure Description

[0020] Figure 1 The flowchart shown is a specific embodiment of the calibration method described in this application.

[0021] Figure 2 The diagram shown is an example of a structural diagram of the calibration device described in this application in a specific embodiment.

[0022] Figure 3A The flowchart shown is a key step of the calibration method described in this application in a specific embodiment.

[0023] Figure 3B The diagram shown is an example of a structural diagram of the calibration device described in this application in a specific embodiment.

[0024] Figure 4 The diagram shown is an example of a structural diagram of the calibration device described in this application in a specific embodiment.

[0025] Component designation explanation

[0026] Steps S11 to S15

[0027] Steps S31 to S32 Detailed Implementation

[0028] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0029] It should be noted that the illustrations provided in the following embodiments are merely schematic representations of the basic concept of this application. The illustrations only show components relevant to this application and are not drawn according to the actual number, shape, and size of components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may also be more complex. Furthermore, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0030] Current multiphase clock calibration techniques are mostly based on frequency and phase detectors and low-frequency filters, combined with digital control, adjusting the voltage-controlled oscillator (VCO) control voltage or the multiphase output delay of the phase-locked loop (PLL) to achieve calibration. However, adjusting the VCO control voltage is difficult to apply directly to multi-output circuits, and adjusting the PLL multiphase output delay has problems of excessive hardware overhead and power consumption. To address these issues, one embodiment of this application provides a calibration method, please refer to the reference. Figure 1 and 2 The calibration method includes:

[0031] S11, each phase clock signal in the multi-phase clock signal is selected as the master clock signal and a corresponding clock signal is selected as the auxiliary clock signal according to the first preset rule. The reference phase difference between each master clock signal and the corresponding auxiliary clock signal under the first preset rule is the first preset value.

[0032] The multi-phase clock signal can be clk_p0, clk_p1, ..., clk_pm, where m is an integer greater than 1. For an example of a four-phase clock signal (i.e., m = 3), please refer to [link to example]. Figure 2 The four-phase clock signal generation circuit outputs four-phase clock signals, clk_p0, clk_p1, clk_p2, and clk_p3, with a reference phase difference of π / 2 between adjacent phases of clk_p0, clk_p1, clk_p2, and clk_p3. A main selector and an auxiliary selector receive these four-phase clock signals and, under the control of the controller, select the corresponding phase clock signal. Under a first preset rule, the controller controls the main selector to select each phase clock signal as the main clock signal for output, i.e., clk_p0, clk_p1, clk_p2, and clk_p3 are output as the main clock signals in turn. Simultaneously, the controller controls the auxiliary selector to select each corresponding clock signal as the auxiliary clock signal for output. The reference phase difference between each main clock signal and its corresponding auxiliary clock signal is a first preset value. The first preset value can be set according to actual needs, for example, it can be 2×π / (m+1). Therefore, for a four-phase clock signal, the first preset value is π / 2. That is to say, when the controller controls the main selector to select clk_p0 as the main clock signal, the controller will correspondingly control the auxiliary selector to select the clock signal clk_p1 with a reference phase difference of π / 2 from clk_p0 as the auxiliary clock signal. That is, when clk_p0 is the main clock signal, the corresponding auxiliary clock signal is clk_p1. Similarly, when clk_p1 is the main clock signal, the corresponding auxiliary clock signal is clk_p2; when clk_p2 is the main clock signal, the corresponding auxiliary clock signal is clk_p3; and when clk_p3 is the main clock signal, the corresponding auxiliary clock signal is clk_p0.

[0033] S12, according to the second preset rule, each phase clock signal in the multi-phase clock signal is selected as the respective master clock signal and a corresponding clock signal is selected as the corresponding auxiliary clock signal. The reference phase difference between each master clock signal and the corresponding auxiliary clock signal under the second preset rule is the second preset value.

[0034] like Figure 2As shown, similarly, under the second preset rule, the controller still controls the main selector, causing it to select each phase of the four-phase clock signal as the main clock signal for output. That is, clk_p0, clk_p1, clk_p2, and clk_p3 are output as the main clock signals in turn. Simultaneously, the controller controls the auxiliary selector, causing it to select each corresponding clock signal as the auxiliary clock signal for output. The reference phase difference between each main clock signal and its corresponding auxiliary clock signal is a second preset value, which is not equal to the first preset value. The second preset value can be set according to actual needs; for example, it can be 4×π / (m+1). For a four-phase clock signal, the second preset value is π. In other words, when the controller controls the main selector to select clk_p0 as the main clock signal, the controller will correspondingly control the auxiliary selector to select clk_p2, a clock signal with a reference phase difference of π from clk_p0, as the auxiliary clock signal. That is, when clk_p0 is the main clock signal, the corresponding auxiliary clock signal is clk_p2. Similarly, when clk_p1 is the main clock signal, the corresponding auxiliary clock signal is clk_p3; when clk_p2 is the main clock signal, the corresponding auxiliary clock signal is clk_p0; and when clk_p3 is the main clock signal, the corresponding auxiliary clock signal is clk_p1.

[0035] S13, obtain the time difference between each master clock signal and the corresponding auxiliary clock signal under the first preset rule and the second preset rule.

[0036] like Figure 2 As shown, the time difference acquisition module connects the main selector and the auxiliary selector. It is used to receive the main clock signal output by the main selector and the auxiliary clock signal output by the auxiliary selector, and to acquire the time difference t(pi,pj_dmy) between each main clock signal and the corresponding auxiliary clock signal, where pi represents the main clock signal and pj_dmy represents the auxiliary clock signal.

[0037] S14, determine the delay adjustment amount of each master clock signal according to the time difference, and obtain the phase error between the multi-phase clock signals according to the delay adjustment amount.

[0038] In one embodiment, such as Figure 2 As shown, the controller can calculate the delay adjustment amount of the master clock signal based on the time difference output by the time difference acquisition module.

[0039] In another embodiment, such as Figure 3A As shown, the method for determining the delay adjustment amount of each master clock signal based on the time difference includes:

[0040] S31, Obtain the frequency signal corresponding to the time difference based on the time difference.

[0041] Optionally, such as Figure 3B As shown, a frequency conversion module (such as a current-controlled oscillator ICO) can be connected between the time difference acquisition module and the controller. The frequency conversion module receives the time difference output by the time difference acquisition module, converts the time difference into a frequency signal, and sends the converted frequency signal to the controller.

[0042] S32, obtain the delay adjustment amount of the master clock signal based on the frequency signal.

[0043] Specifically, the controller can obtain the delay adjustment amount of each master clock signal based on the frequency signal sent by the frequency conversion module.

[0044] As mentioned above, under the first preset rule and the second preset rule, the main controller controls the main selector to make each phase clock signal in the multi-phase clock signal take turns as the main clock signal. Therefore, the controller can obtain the delay adjustment amount of each phase clock signal under the first preset rule and the delay adjustment amount of each phase clock signal under the second preset rule.

[0045] After obtaining the delay adjustment amount of the master clock signal, the main controller can control the delay adjustment module to adjust the delay of the master clock signal so that the phase difference between the master clock signal and the corresponding auxiliary clock signal is equal to or close to a preset value. Here, "phase difference close to preset value" means that the difference between the phase difference and the preset value is less than a preset threshold, which can be set according to actual needs. Under the first preset rule, this preset value is the first preset value; under the second preset rule, this preset value is the second preset value.

[0046] In one embodiment, the main controller obtains the phase error between multi-phase clock signals based on the delay adjustment amount as follows:

[0047] Where Δt(k+1,k) is the phase error between the k-th phase clock signal and the (k+1)-th phase clock signal, m+1 is the number of phases in the multi-phase clock signal, and c A (n) represents the delay adjustment amount of the nth phase clock signal under the first preset rule, c B (n) represents the delay adjustment amount of the nth phase clock signal under the second preset rule.

[0048] The formula for calculating the phase error mentioned above can be obtained as follows:

[0049] Under the first preset rule, after adjusting the delay of the master clock signal according to the delay adjustment amount of the acquired master clock signal, the phase difference between each master clock signal and the corresponding auxiliary clock signal is equal to or close to the first preset value d. ATherefore, we can know that t(p1,p2_dmy)-c A (0)=t(p2,p3_dmy)-c A (1) = ... = t(pk, p0_dmy) - c A (m-1)=t(p0,p1_dmy)-c A (m)=d A Where t(pi,pj_dmy) is the time difference between the i-th phase main clock signal and the corresponding j-th phase auxiliary clock signal, and c A (i) represents the delay adjustment amount corresponding to the i-th phase master clock signal.

[0050] Under the second preset rule, after adjusting the delay of the master clock signal according to the delay adjustment amount of the acquired master clock signal, the phase difference between each master clock signal and the corresponding auxiliary clock signal is equal to or close to the second preset value d. B Therefore, t(p0,p2_dmy)-c B (0)=t(p1,p3_dmy)-c B (1) = ... = t(pk-1, p0_dmy) - c B (m-1)=t(pm,p1_dmy)-c B (m)=d B , where c B (i) represents the delay adjustment amount corresponding to the i-th phase clock signal.

[0051] The above d A With d B The equation includes the phase difference introduced by both clock paths (the main clock signal path and the auxiliary clock signal path). Subtracting the two will cancel out the phase difference introduced by the auxiliary clock signal path. A -d B We can obtain:

[0052] t(p1,p0)=d A -d B +c A (0)-c B (0) (1)

[0053] t(p2,p1)=d A -d B +c A (1)-c B (1) (2)

[0054] ...

[0055] t(pm, pm-1) = d A -d B +c A(m-1)-c B (m-1) (m)

[0056] t(p0,pm)=d A -d B +c A (m)-c B (m) (m+1),

[0057] The sum of (1), (2), ..., (m), (m+1) above equals -T (where T is the period), thus yielding:

[0058]

[0059] Will Substituting into (1), (2), ..., (m-1), (m) above, we get:

[0060]

[0061] From this, we can further conclude that... Right now:

[0062]

[0063] S15, obtain the calibration amount of the multi-phase clock signal based on the phase error.

[0064] In one embodiment, after obtaining the phase error, the method for obtaining the calibration value of the multi-phase clock signal based on the phase error of the multi-phase clock signal can be as follows:

[0065] Where c(k) is the calibration value of the k-th phase clock signal.

[0066] Preferably, if min(c(0),c(1),...,c(m))<0, then a bias of -cmin is applied to all c(k), where cmin is min(c(0),c(1),...,c(m)).

[0067] As can be seen from the above description, the calibration method provided in this embodiment is based on an error cancellation algorithm to obtain the phase error and calibration amount of the multi-phase clock signal. This process only requires simple algebraic operations to obtain the calibration amount, which is simple to implement and helps to reduce hardware overhead and power consumption.

[0068] After acquiring the calibration value of each phase clock signal, when the multi-phase clock signal generation circuit outputs the multi-phase clock signal, the main controller can control the delay adjustment module to calibrate each phase clock signal according to the corresponding calibration value and output the calibrated multi-phase clock signal.

[0069] In one embodiment of this application, as Figure 2 As shown in 3B, the delay adjustment module is connected between the output of the main selector and the input of the time difference acquisition module. The multi-phase clock signal is selected by the main selector and output, with only one phase clock signal output at any given moment to drive the subsequent circuit. This single-phase clock signal is calibrated by the delay adjustment module and then output to the corresponding subsequent circuit.

[0070] In another embodiment of this application, as Figure 4 As shown, each phase of the multi-phase clock signal is connected to a delay adjustment module at its corresponding input to the main selector. At any given moment, all phase clock signals can be output to drive subsequent circuits. Each phase clock signal is calibrated by its corresponding delay adjustment module before being output. In practical applications, one or more phase clock signals can be selected according to actual needs.

[0071] Based on the above description of the calibration method, embodiments of this application also provide a calibration apparatus. Please refer to... Figure 2 , Figure 3B and Figure 4 In one embodiment of this application, the calibration transpose includes:

[0072] The master selector is used to receive multi-phase clock signals and, under the control of the controller, select one phase clock signal from the multi-phase clock signals to output as the master clock signal.

[0073] An auxiliary selector is used to receive the multi-phase clock signal and, under the control of the controller, select a corresponding phase clock signal from the multi-phase clock signal and output it as an auxiliary clock signal, wherein the reference phase difference between the main clock signal and the auxiliary clock signal is a preset value, and the preset value is a value that is not equal to 0.

[0074] The time difference acquisition module is used to receive the master clock signal and the auxiliary clock signal and acquire the time difference between the master clock signal and the auxiliary clock signal.

[0075] The controller, connected to the main selector, the auxiliary selector, and the time difference acquisition module, is used to determine the delay adjustment amount of the main clock signal based on the time difference between the main clock signal and the auxiliary clock signal.

[0076] The delay adjustment module, connected to the main selector and the controller, is used to adjust the delay of the main clock signal according to the delay adjustment amount, so that the phase difference between the main clock signal and the auxiliary clock signal is equal to or close to the preset value.

[0077] In one embodiment, the controller is further configured to control the main selector to select each phase clock signal in the multi-phase clock signals as a respective main clock signal according to a first preset rule, and to control the auxiliary selector to select a corresponding clock signal as a corresponding auxiliary clock signal, and to control the main selector to select each phase clock signal in the multi-phase clock signals as a respective main clock signal according to a second preset rule, and to control the auxiliary selector to select a corresponding clock signal as a corresponding auxiliary clock signal; wherein, under the first preset rule, the reference phase difference between each main clock signal and the corresponding auxiliary clock signal is a first preset value, and under the second preset rule, the reference phase difference between each main clock signal and the corresponding auxiliary clock signal is a second preset value, and the first preset value is different from the second preset value; the time difference acquisition module acquires the time difference between each main clock signal and the corresponding auxiliary clock signal under the first preset rule and the second preset rule, the controller determines the delay adjustment amount of each main clock signal based on the time difference, obtains the phase error between the multi-phase clock signals according to the delay adjustment amount, and obtains the calibration amount of the multi-phase clock signals according to the phase error.

[0078] In one embodiment, the first preset value is 2×π / (m+1), and the second preset value is 4×π / (m+1), where m+1 is the number of phases of the multi-phase clock signal.

[0079] In one embodiment, such as Figure 3B , Figure 4 As shown, the calibration device further includes a frequency conversion module; the frequency conversion module is connected between the time difference acquisition module and the controller, and is used to receive the time difference between the master clock signal and the corresponding auxiliary clock signal, and to acquire the frequency signal corresponding to the time difference and output it to the controller. The controller acquires the delay adjustment amount of each master clock signal based on the frequency signal.

[0080] In one embodiment, the controller is specifically configured to obtain the phase error between the multi-phase clock signals according to the following formula:

[0081] Where Δt(k+1,k) is the phase error between the k-th phase clock signal and the (k+1)-th phase clock signal, m+1 is the number of phases of the multi-phase clock signal, and c A (n) represents the delay adjustment amount of the nth phase clock signal under the first preset rule, c B (n) represents the delay adjustment amount of the nth phase clock signal under the second preset rule.

[0082] In one embodiment, the controller is specifically configured to obtain the calibration amount of the multi-phase clock signal according to the following formula:

[0083] Where c(k) is the calibration value of the k-th phase clock signal.

[0084] In one embodiment, such as Figure 3B As shown, the delay adjustment module is connected between the output of the main selector and the input of the time difference acquisition module.

[0085] In another embodiment, such as Figure 4 As shown, each phase clock signal in the multi-phase clock signal is connected to a delay adjustment module between the corresponding input terminal of the master selector.

[0086] This application also provides a multiphase clock circuit. The multiphase clock circuit includes a clock signal generation circuit and the calibration device described in the above embodiments. The calibration device includes at least a main selector, an auxiliary selector, a time difference acquisition module, a controller, and a delay adjustment module.

[0087] Specifically, the clock signal generation circuit is used to generate multi-phase clock signals.

[0088] The master selector is used to receive multi-phase clock signals and, under the control of the controller, select one phase clock signal from the multi-phase clock signals to output as the master clock signal.

[0089] The auxiliary selector is used to receive the multi-phase clock signal and, under the control of the controller, select a corresponding phase clock signal from the multi-phase clock signal and output it as an auxiliary clock signal. The reference phase difference between the main clock signal and the auxiliary clock signal is a preset value, and the preset value is not equal to 0.

[0090] The time difference acquisition module is used to receive the master clock signal and the auxiliary clock signal and acquire the time difference between the master clock signal and the auxiliary clock signal.

[0091] The controller is connected to the main selector, the auxiliary selector, and the time difference acquisition module, and is used to determine the delay adjustment amount of the main clock signal based on the time difference between the main clock signal and the auxiliary clock signal.

[0092] The delay adjustment module is connected to the main selector and the controller, and is used to adjust the delay of the main clock signal according to the delay adjustment amount, so that the phase difference between the main clock signal and the auxiliary clock signal is equal to or close to the preset value.

[0093] Furthermore, related technologies also employ frequency and phase detectors and low-frequency filters combined with digital control to adjust the multi-phase output delay of the VCO (Voltage Controlled Oscillator) or PLL to achieve phase calibration. However, adjusting the VCO control voltage is difficult to apply directly to multi-output circuits, while adjusting the multi-phase output delay of the PLL suffers from excessive hardware overhead and power consumption. Unlike the solutions used in related technologies, the calibration method and apparatus described in one or more embodiments of this application use an auxiliary clock signal as a reference for calibration, requiring only the addition of a selector to the multi-phase clock circuit without an additional reference source. The calibration method and apparatus achieve calibration by fine-tuning the clock tree delay of the multi-phase clock, rather than directly adjusting the multi-phase output of the PLL. This approach has lower hardware overhead and meets the requirements of low-power design. Moreover, the calibration method and apparatus offer considerable flexibility in circuit configuration and algorithm flow. Furthermore, the calibration method and calibration device described in one or more embodiments of this application can adjust the delay of the master clock signal through a delay adjustment module. By configuring the number and position of the delay adjustment modules, simultaneous output of one or more phase clock signals can be achieved, which is suitable for both single-output circuits and multi-output circuits.

[0094] Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0095] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A phase calibration method for a multi-phase clock signal, characterized in that, The phase calibration method for the multi-phase clock signal includes: According to the first preset rule, each phase clock signal in the multi-phase clock signal is selected as the respective master clock signal and a corresponding clock signal is selected as the corresponding auxiliary clock signal. The reference phase difference between each master clock signal and the corresponding auxiliary clock signal under the first preset rule is the first preset value. According to the second preset rule, each phase clock signal in the multi-phase clock signal is selected as the main clock signal and a corresponding clock signal is selected as the corresponding auxiliary clock signal. The reference phase difference between each main clock signal and the corresponding auxiliary clock signal under the second preset rule is the second preset value, wherein the first preset value is not equal to the second preset value. Obtain the time difference between each master clock signal and the corresponding auxiliary clock signal under the first preset rule and the second preset rule; The delay adjustment amount of each master clock signal is determined based on the time difference, and the phase error between the multi-phase clock signals is obtained based on the delay adjustment amount. The calibration value of the multi-phase clock signal is obtained based on the phase error.

2. The phase calibration method for a multi-phase clock signal according to claim 1, characterized in that, Determining the delay adjustment amount of each master clock signal based on the time difference includes: The frequency signal corresponding to the time difference is obtained based on the time difference. The delay adjustment amount of each master clock signal is obtained based on the frequency signal.

3. The phase calibration method for a multi-phase clock signal according to claim 1, characterized in that, The method for obtaining the phase error between the multi-phase clock signals based on the delay adjustment amount is as follows: ,in, For the first Phase clock signal and the ( Phase error between phase clock signals The number of phases in a multi-phase clock signal. For the first The delay adjustment amount of the phase clock signal under the first preset rule. For the first The amount of delay adjustment of the phase clock signal under the second preset rule.

4. The phase calibration method for a multi-phase clock signal according to claim 3, characterized in that, The method for obtaining the calibration value of the multi-phase clock signal based on the phase error is as follows: ,in, For the first The calibration value of the phase clock signal.

5. The phase calibration method for a multi-phase clock signal according to claim 1, characterized in that: The first preset value is The second preset value is ,in, The number of phases of the multi-phase clock signal.

6. A phase calibration device for a multi-phase clock signal, characterized in that, include: The master selector is used to receive multi-phase clock signals and, under the control of the controller, select one phase clock signal from the multi-phase clock signals and output it as the master clock signal. An auxiliary selector is used to receive the multi-phase clock signal and, under the control of the controller, select a corresponding phase clock signal from the multi-phase clock signal and output it as an auxiliary clock signal, wherein the reference phase difference between the main clock signal and the auxiliary clock signal is a preset value, and the preset value is a value that is not equal to 0. A time difference acquisition module is used to receive the master clock signal and the auxiliary clock signal and acquire the time difference between the master clock signal and the auxiliary clock signal; The controller, connected to the main selector, the auxiliary selector, and the time difference acquisition module, is used to determine the delay adjustment amount of the main clock signal based on the time difference between the main clock signal and the auxiliary clock signal. The delay adjustment module, connected to the main selector and the controller, is used to adjust the delay of the main clock signal according to the delay adjustment amount, so that the phase difference between the main clock signal and the auxiliary clock signal is equal to or close to the preset value.

7. The phase calibration device for multi-phase clock signals according to claim 6, characterized in that, The controller is further configured to control the main selector to select each phase clock signal in the multi-phase clock signals as a respective main clock signal according to a first preset rule, and to control the auxiliary selector to select a corresponding clock signal as a corresponding auxiliary clock signal, and to control the main selector to select each phase clock signal in the multi-phase clock signals as a respective main clock signal according to a second preset rule, and to control the auxiliary selector to select a corresponding clock signal as a corresponding auxiliary clock signal; wherein, under the first preset rule, the reference phase difference between each main clock signal and the corresponding auxiliary clock signal is a first preset value, and under the second preset rule, the reference phase difference between each main clock signal and the corresponding auxiliary clock signal is a second preset value, and the first preset value is different from the second preset value; The time difference acquisition module acquires the time difference between each master clock signal and the corresponding auxiliary clock signal under the first preset rule and the second preset rule. The controller determines the delay adjustment amount of each master clock signal based on the time difference, obtains the phase error between the multi-phase clock signals according to the delay adjustment amount, and obtains the calibration amount of the multi-phase clock signals according to the phase error.

8. The phase calibration device for multi-phase clock signals according to claim 7, characterized in that, The phase calibration device also includes a frequency conversion module; The frequency conversion module is connected between the time difference acquisition module and the controller, and is used to receive the time difference between the main clock signal and the corresponding auxiliary clock signal, and to acquire the frequency signal corresponding to the time difference based on the time difference. The controller obtains the delay adjustment amount of each master clock signal based on the frequency signal.

9. The phase calibration device for a multi-phase clock signal according to claim 7, characterized in that, The controller is specifically used to obtain the phase error between the multi-phase clock signals according to the following formula: ,in, For the first Phase clock signal and the ( Phase error between phase clock signals The number of phases of the multi-phase clock signal. For the first The delay adjustment amount of the phase clock signal under the first preset rule. For the first The delay adjustment amount of the phase clock signal under the second preset rule.

10. The phase calibration device for a multi-phase clock signal according to claim 9, characterized in that, The controller is specifically used to obtain the calibration value of the multi-phase clock signal according to the following formula: ,in, For the first The calibration value of the phase clock signal.

11. The phase calibration device for a multi-phase clock signal according to claim 6, characterized in that, The delay adjustment module is connected between the output of the main selector and the input of the time difference acquisition module.

12. The phase calibration device for a multi-phase clock signal according to claim 6, characterized in that, Each phase clock signal in the multi-phase clock signal is connected to a delay adjustment module between its corresponding input terminal of the master selector.

13. The phase calibration device for a multi-phase clock signal according to claim 7, characterized in that, The first preset value is The second preset value is ,in, This represents the number of phases in a multi-phase clock signal.

14. A multiphase clock circuit, characterized in that, The multiphase clock circuit includes: Clock signal generation circuit, used to generate multi-phase clock signals; The master selector is used to receive the multi-phase clock signal and, under the control of the controller, select one phase clock signal from the multi-phase clock signal and output it as the master clock signal. An auxiliary selector is used to receive the multi-phase clock signal and, under the control of the controller, select a corresponding phase clock signal from the multi-phase clock signal and output it as an auxiliary clock signal, wherein the reference phase difference between the main clock signal and the auxiliary clock signal is a preset value, and the preset value is a value that is not equal to 0. A time difference acquisition module is used to receive the master clock signal and the auxiliary clock signal and acquire the time difference between the master clock signal and the auxiliary clock signal; The controller, connected to the main selector, the auxiliary selector, and the time difference acquisition module, is used to determine the delay adjustment amount of the main clock signal based on the time difference between the main clock signal and the auxiliary clock signal. The delay adjustment module, connected to the main selector and the controller, is used to adjust the delay of the main clock signal according to the delay adjustment amount, so that the phase difference between the main clock signal and the auxiliary clock signal is equal to or close to the preset value.

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