Successive approximation analog-to-digital converter and method thereof

Abstract

The present disclosure provides a successive approximation analog-to-digital converter, comprising: a capacitor array; a comparator, wherein a first input terminal of the comparator is connected to the differential positive capacitor in each group of differential capacitors to respectively receive the voltage of the differential positive capacitor, a second input terminal of the comparator is connected to the differential negative capacitor in each group of differential capacitors to respectively receive the voltage of the differential negative capacitor, and outputs the voltage measurement value of each group of differential capacitors; a logic module, which is used to obtain calibration weight values of m groups of high-order differential capacitors based on the voltage measurement values of n groups of low-order differential capacitors, and calibrate the voltage measurement value of each group of high-order differential capacitors according to the obtained calibration weight value of each group of high-order differential capacitors, so as to generate a conversion output value according to the voltage measurement values of the n groups of low-order differential capacitors and the voltage measurement values and calibration weight values of the m groups of high-order differential capacitors.

Description

Technical Field

[0001] The present disclosure relates to a successive approximation analog-to-digital converter. Background Art

[0002] Successive approximation (SAR) ADCs (ADCs) are widely used due to their low power consumption and small footprint. However, the accuracy of high-precision SAR ADCs is often limited by capacitor mismatch. In recent years, various approaches have been proposed to enhance the dynamic performance of SAR ADCs.

[0003] Because capacitor mismatch exists, the weights between capacitors are not exactly binary. In existing technology, the conversion signal obtained by directly using binary weighted calculations in the digital domain will deviate from the actual analog voltage, resulting in a decrease in the accuracy of the successive approximation analog-to-digital converter (SAR ADC). Therefore, it is necessary to calibrate the capacitor mismatch of the SAR ADC. Summary of the Invention

[0004] In order to solve one of the above technical problems, the present disclosure provides a successive approximation analog-to-digital converter and a method thereof.

[0005] According to one aspect of the present disclosure, there is provided a successive approximation analog-to-digital converter, comprising:

[0006] A capacitor array, the capacitor array comprising N groups of differential capacitors and a switch array, each group of differential capacitors comprising a differential positive capacitor and a differential negative capacitor, the switch array being configured to connect the differential positive capacitors and the differential negative capacitors of the N groups of differential capacitors to a positive reference voltage and a negative reference voltage, respectively, where N>1, the N groups of differential capacitors comprising n groups of low-order differential capacitors and m groups of high-order differential capacitors, where n+m=N;

[0007] a comparator, wherein a first input terminal of the comparator is connected to the differential positive capacitors in each group of differential capacitors to respectively receive the voltage of the differential positive capacitors, a second input terminal of the comparator is connected to the differential negative capacitors in each group of differential capacitors to respectively receive the voltage of the differential negative capacitors, and outputs a voltage measurement value of each group of differential capacitors;

[0008] A logic module is used to obtain calibration weight values of m groups of high-order differential capacitors based on the voltage measurement values of n groups of low-order differential capacitors, and to calibrate the voltage measurement value of each group of high-order differential capacitors according to the obtained calibration weight value of each group of high-order differential capacitors, so as to generate a conversion output value according to the voltage measurement values of the n groups of low-order differential capacitors and the voltage measurement values and calibration weight values of the m groups of high-order differential capacitors.

[0009] According to at least one embodiment of the successive approximation analog-to-digital converter of the present disclosure, the memory is further configured to store the obtained calibration weight values so that the calibration weight values can be called when the analog-to-digital converter is actually operating to calibrate the voltage measurement values of each group of high-bit differential capacitors.

[0010] According to at least one embodiment of the successive approximation analog-to-digital converter of the present disclosure, calibration weight values corresponding to each group of high-order differential capacitors are obtained for m groups of high-order differential capacitors according to voltage measurement values of n groups of low-order differential capacitors.

[0011] According to at least one embodiment of the successive approximation analog-to-digital converter of the present disclosure, during the process of calibrating each set of high-bit differential capacitors,

[0012] Connect all low-order differential capacitors to an inverting reference voltage, connect the bottom plates of the differential positive capacitors of the group of high-order differential capacitors to the positive reference voltage and connect the bottom plates of the differential negative capacitors to the inverting reference voltage, and connect all other groups of high-order differential capacitors to the inverting reference voltage. Perform conversion using an analog-to-digital converter composed of a capacitor array, a comparator, and a logic module of the low-order differential capacitors to obtain first conversion results of each low-order differential capacitor, and perform weighted summation of each first conversion result to obtain a first calibration value.

[0013] The bottom plates of the differential positive capacitors of the group of differential capacitors are connected to an inverting reference voltage and the bottom plates of the differential negative capacitors are connected to a positive reference voltage, and all other groups of differential capacitors are connected to an inverting reference voltage. A second conversion result of each low-order differential capacitor is obtained by performing conversion using an analog-to-digital converter composed of a capacitor array, a comparator, and a logic module. The second conversion results are weighted and summed to obtain a second calibration value.

[0014] The calibration weight value of the group of high-order differential capacitors is obtained by subtracting the second calibration value from the first calibration value.

[0015] According to a successive approximation analog-to-digital converter of at least one embodiment of the present disclosure, the first calibration value is Dn_p*Cn+Dn-1_p*Cn-1+…+D1_p*C1, where Dn_p is the first conversion result of the n-th low-order differential capacitor, and Cn is the capacitance-related value of the n-th low-order differential capacitor; Dn-1_p is the first conversion result of the n-1-th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1-th low-order differential capacitor; D1_p is the first conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor;

[0016] The second calibration value is Dn_n*Cn+Dn-1_n*Cn-1+…+D1_n*C1, where Dn_n is the second conversion result of the nth low-order differential capacitor, and Cn is the capacitance-related value of the nth low-order differential capacitor; Dn-1_n is the second conversion result of the n-1th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1th low-order differential capacitor; D1_n is the second conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor.

[0017] According to the successive approximation analog-to-digital converter of at least one embodiment of the present disclosure, after the analog-to-digital converter enters the normal conversion mode, the calibrated output value is: DN*BN_cal+DN-1*BN-1_cal+…+Dn*2^Cn+…+D1*2^C1, wherein DN is the conversion result of the Nth differential capacitor, BN_cal is the calibration weight value of the Nth differential capacitor, DN-1 is the conversion result of the N-1th differential capacitor, BN-1_cal is the calibration weight value of the N-1th differential capacitor, Dn is the conversion result of the nth low-order differential capacitor, and D1 is the conversion result of the 1st low-order differential capacitor.

[0018] According to another aspect of the present disclosure, a successive approximation analog-to-digital conversion method is provided, comprising:

[0019] Connect all low-order differential capacitors to an inverting reference voltage, connect the bottom plates of the differential positive capacitors of a group of high-order differential capacitors to the positive reference voltage and the bottom plates of the differential negative capacitors to the inverting reference voltage, and connect all other groups of high-order differential capacitors to the inverting reference voltage. Perform conversion using an analog-to-digital converter composed of a capacitor array, a comparator, and a logic module of the low-order differential capacitors to obtain first conversion results of each low-order differential capacitor, and perform weighted summation of each first conversion result to obtain a first calibration value.

[0020] The bottom plates of the differential positive capacitors of the group of differential capacitors are connected to an inverting reference voltage and the bottom plates of the differential negative capacitors are connected to a positive reference voltage, and all other groups of differential capacitors are connected to an inverting reference voltage. A second conversion result of each low-order differential capacitor is obtained by performing conversion using an analog-to-digital converter composed of a capacitor array, a comparator, and a logic module. The second conversion results are weighted and summed to obtain a second calibration value.

[0021] Obtaining the calibration weight value of the group of high-order differential capacitors by subtracting the second calibration value from the first calibration value;

[0022] Repeat at least the steps to obtain the calibration weight value of each group of high-order differential capacitors;

[0023] The conversion output value is generated by multiplying the calibration weight value of each group of high-order differential capacitors by the conversion result and according to the conversion result of each group of low-order differential capacitors.

[0024] According to at least one embodiment of the present disclosure, a successive approximation analog-to-digital conversion method includes N groups of differential capacitors, N>1, the N groups of differential capacitors include n groups of low-order differential capacitors and m groups of high-order differential capacitors, where n+m=N, and each group of high-order differential capacitors obtains its own calibration weight value based on the n groups of low-order differential capacitors.

[0025] According to the successive approximation analog-to-digital conversion method of at least one embodiment of the present disclosure, the first calibration value is Dn_p*Cn+Dn-1_p*Cn-1+…+D1_p*C1, where Dn_p is the first conversion result of the nth low-order differential capacitor, and Cn is the capacitance-related value of the nth low-order differential capacitor; Dn-1_p is the first conversion result of the n-1th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1th low-order differential capacitor; D1_p is the first conversion result of the first low-order differential capacitor, and C1 is the capacitance-related value of the first low-order differential capacitor;

[0026] The second calibration value is Dn_n*Cn+Dn-1_n*Cn-1+…+D1_n*C1, where Dn_n is the second conversion result of the nth low-order differential capacitor, and Cn is the capacitance-related value of the nth low-order differential capacitor; Dn-1_n is the second conversion result of the n-1th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1th low-order differential capacitor; D1_n is the second conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor.

[0027] According to the successive approximation analog-to-digital conversion method of at least one embodiment of the present disclosure, after entering the normal conversion mode, the calibrated output value is: DN*BN_cal+DN-1*BN-1_cal+…+Dn*2^Cn+…+D1*2^C1, wherein DN is the conversion result of the Nth differential capacitor, BN_cal is the calibration weight value of the Nth differential capacitor, DN-1 is the conversion result of the N-1th differential capacitor, BN-1_cal is the calibration weight value of the N-1th differential capacitor, Dn is the conversion result of the nth low-order differential capacitor, and D1 is the conversion result of the 1st low-order differential capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0029] Figure 1 A schematic diagram of a successive approximation analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0030] Figure 2 A schematic diagram of a capacitor array of a successive approximation analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0031] Figure 3 A schematic diagram of a successive approximation analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0032] Figure 4 A schematic diagram of a successive approximation analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0033] Figure 5 A schematic diagram of a successive approximation analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0034] Figure 6 A schematic diagram of a successive approximation analog-to-digital conversion method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0035] The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to explain the relevant content and are not intended to limit the present disclosure. It should also be noted that, for ease of description, only the portions relevant to the present disclosure are shown in the accompanying drawings.

[0036] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] Unless otherwise stated, the exemplary embodiments / examples shown are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of the various embodiments / examples may be further combined, separated, interchanged, and / or rearranged without departing from the technical concepts of the present disclosure.

[0038] The use of cross hatching and / or shading in the accompanying drawings is generally used to make the boundaries between adjacent components clear. As such, unless otherwise indicated, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. In addition, in the accompanying drawings, the sizes and relative sizes of the components may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed in a different order than described. For example, two successively described processes can be performed substantially simultaneously or in an order opposite to the order described. In addition, the same figure numbers represent the same components.

[0039] When a component is referred to as being “on,” “over,” “connected to,” or “coupled to” another component, the component may be directly on, directly connected to, or directly coupled to the other component, or intervening components may be present. However, when a component is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another component, there are no intervening components present. For this purpose, the term “connected” may refer to a physical connection, an electrical connection, etc., with or without intervening components.

[0040] For descriptive purposes, the present disclosure may use spatially relative terms such as "below," "beneath," "under," "down," "above," "upper," "above," "higher," and "side (e.g., as in "sidewall")," to describe the relationship of one component to another (other) component as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is turned over, a component described as "below" or "beneath" another component or feature would then be positioned "above" the other component or feature. Thus, the exemplary term "below" can encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0041] The terms used herein are for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "one (kind, person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, the features, integral bodies, steps, operations, parts, assemblies and / or their groups stated are explained, but the presence or addition of one or more other features, integral bodies, steps, operations, parts, assemblies and / or their groups is not excluded. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, so that they are used to explain the inherent deviations of the measured values, calculated values and / or the values provided that will be recognized by those of ordinary skill in the art.

[0042] According to one embodiment of the present disclosure, a successive approximation analog-to-digital converter (SAR ADC) is provided.

[0043] like Figure 1 As shown, the successive approximation analog-to-digital converter may include a first capacitor array 100 , a second capacitor array 200 , a comparator 300 , and a logic module 400 .

[0044] The first capacitor array 100 is a differential positive capacitor array, and the first input terminal of the comparator 300 is connected to the first capacitor array 100, the second capacitor array 200 is a differential negative capacitor array, and the second input terminal of the comparator 300 is connected to the second capacitor array 200. The comparator 300 is used to compare the voltage between the first capacitor array 100 and the second capacitor array 200, and provide the comparison result to the logic module 400. That is, the capacitor array includes N groups of differential capacitors and switch arrays, each group of differential capacitors includes differential positive capacitors and differential negative capacitors, and the switch array is configured to connect the differential positive capacitors and differential negative capacitors of the N groups of differential capacitors to the positive reference voltage and the negative reference voltage, respectively, where N>1. The first capacitor array 100 and the second capacitor array 200 include capacitors and switches connected to the capacitors, and each switch switches between the voltage VRN (negative reference voltage) and VRP (positive reference voltage). As Figure 2 The first input terminal of the comparator is connected to the differential positive capacitor in each group of differential capacitors to receive the voltage of the differential positive capacitor, the second input terminal of the comparator is connected to the differential negative capacitor in each group of differential capacitors to receive the voltage of the differential negative capacitor, and outputs the voltage measurement value of each group of differential capacitors.

[0045] The logic module 400 controls switches in the first capacitor array 100 or the second capacitor array 200 based on the comparison result. In addition, the logic module 400 is configured to receive the voltage measurement value of each group of differential capacitors output by the comparator and calibrate the voltage measurement value of each group of differential capacitors based on the calibration weight value of each group of differential capacitors to generate a conversion output value.

[0046] The first capacitor array 100 includes a first low-order capacitor array 110 and a first high-order capacitor array 120, wherein the first low-order capacitor array 110 and the first high-order capacitor array 120 are connected via a first capacitor 1C. The second capacitor array 200 includes a second low-order capacitor array 210 and a second high-order capacitor array 220, wherein the second low-order capacitor array 210 and the second high-order capacitor array 220 are connected via a second capacitor 1C.

[0047] SAR ADCs are widely used due to their advantages, such as their small footprint. However, the accuracy of high-precision SAR ADCs is often limited by capacitor mismatch. This paper proposes a calibration technique for SAR ADC capacitor arrays. This technique measures the capacitance weight error after power-up, avoiding accuracy loss caused by capacitor mismatch.

[0048] In this disclosure, as an embodiment, a 9+7 segmented structure can be adopted. That is, there can be 9 high-order capacitors and 7 low-order capacitors. In this way, each time the SAR ADC completes the conversion, 16 digital codes will be obtained: D16, D15, D14, ..., D2, D1. When not calibrated, the digital domain will be weighted according to the following formula:

[0049] Dout=D16*2^16+D15*2^15+D14*2^14+……+D2*2^2+D1*2^1.

[0050] However, due to capacitor mismatch, the weights between capacitors are not accurate binary. The output Dout obtained by directly using binary for weighted calculation in the digital domain will deviate from the actual analog voltage, resulting in a decrease in the accuracy of the SAR ADC. Therefore, the capacitor mismatch of the SAR ADC needs to be calibrated.

[0051] To address the random mismatch of calibration capacitors, a SAR ADC consisting of a low-order capacitor array, comparator, and logic circuit is used to measure the weight value of each high-order capacitor. The result is stored in efuse, and the weight value is added in the digital domain during actual operation.

[0052] The specific calibration process is described in detail below. It is assumed that the first capacitor array includes N capacitors and the second capacitor array includes N capacitors, where N is an integer greater than 1, preferably ≥ 16. In this application, the capacitors of the first capacitor array are referred to as differential positive capacitors, and the capacitors of the second capacitor array are referred to as differential negative capacitors.

[0053] The N differential positive capacitors included in the first capacitor array are B1, B2, ..., BN-1, and BN from low to high. The N differential positive capacitors included in the second capacitor array are B1, B2, ..., BN-1, and BN from low to high. The low-order capacitors of the N differential positive capacitors may include n capacitors, namely B1, B2, ..., Bn, and the high-order capacitors of the N differential positive capacitors may include m capacitors, namely Bn+1, Bn+2, ..., BN, where n+m=N. The low-order capacitors of the N differential negative capacitors may include n capacitors, namely B1, B2, ..., Bn, and the high-order capacitors of the N differential negative capacitors may include m capacitors, namely Bn+1, Bn+2, ..., BN, where n+m=N.

[0054] Taking the calibration capacitor Bn+1 as an example, the first step is to connect the bottom plates of all differential positive and negative capacitors B1 to Bn to VRN. The bottom plate of the differential positive capacitor Bn+1 is connected to VRP, the bottom plate of the differential negative capacitor Bn+1 is connected to VRN, and the bottom plates of all other high-order capacitors are connected to VRN. The second step is to perform a SAR ADC conversion on the capacitor array B1 to Bn, the comparator, and the logic module. This will produce n conversion results, Dn_p, Dn-1_p, ..., D2_p, and D1_p, with Dn_p being the conversion result for the nth capacitor. After weighted summation, Bn+1_p = Dn_p * Cn + ... + D1_p * C1, where Cn is the capacitance value or relative ratio of the nth capacitor, and Bn+1_p is the first calibration value for capacitor Bn+1. The third step is to connect the bottom plate of the differential positive capacitor Bn+1 to VRN and the bottom plate of the differential negative capacitor Bn+1 to VRP. The connection method of other capacitors remains unchanged. The fourth step is the same as the second step, obtaining Dn_n, Dn-1_n, ..., D2_n, D1_n, a total of n conversion results, Dn_n is the conversion result of the nth capacitor. After weighted summation, Bn+1_n = Dn_n*Cn+...+D1_n*C1. Bn+1_n is the second calibration value of capacitor Bn+1. The fifth step is to calculate the calibration weight value of capacitor Bn+1 as Bn+1_cal = Bn+1_p-Bn+1_n, and store this value in the memory efuse. Bn+1_cal will be called every time digital domain weighting is performed.

[0055] Similar operations can be performed to obtain the calibration weight Bn+2_cal of Bn+2, and so on to the calibration weight BN_cal of BN.

[0056] After calibration, the SAR ADC enters normal conversion mode. Each time the SAR ADC completes a conversion, it generates N digital codes: DN, DN-1, ..., D2, D1. The digital domain is weighted according to the following formula:

[0057] Dout=DN*BN_cal+……+D4*2^4+D3*2^3+D2*2^2+D1*2^1.

[0058] Because BN_cal, ..., Bn_cal are calculated based on actual capacitance values, the output Dout can better approximate the analog input voltage, realizing a high-precision SAR ADC.

[0059] With reference to the structure shown in the figure, including four low-level capacitors B1, B2, B3, and B4, the calibration of the high-level capacitor is described in detail.

[0060] Taking the calibration capacitor B5 as an example, the first step is to connect the bottom plates of all capacitors B1 to B4 to VRN, the bottom plate of the differential positive capacitor B5 to VRP, the bottom plate of the differential negative capacitor B5 to VRN, and the bottom plates of all capacitors B6 to B16 to VRN. The second step is to convert the SAR ADC composed of the B1 to B4 capacitor array, comparator, and logic module. This will produce four conversion results: D4_p, D3_p, D2_p, and D1_p. After weighted summation, B5_p = D4_p*8 + D3_p*4 + D2_p*2 + D1_p*1 (where the exponents 8, 4, 2, and 1 are the capacitance values or relative proportions of capacitors B1 to B4). The third step is to connect the bottom plate of the differential positive capacitor B5 to VRN and the bottom plate of the differential negative capacitor B5 to VRP. The other capacitor connections remain unchanged. The fourth step is the same as the second step, obtaining four conversion results: D4_n, D3_n, D2_n, and D1_n. After weighted summation, B5_n = D4_n*8 + D3_n*4 + D2_n*2 + D1_n*1. The fifth step is to calculate the calibration weight of capacitor B5: B5_cal = B5_p - B5_n. This value is stored in efuse. B5_cal will be called every subsequent time digital domain weighting is performed.

[0061] Taking the calibration capacitor B6 as an example, the first step is to connect the bottom plates of all capacitors B1 to B4 to VRN, the bottom plate of the differential positive capacitor B6 to VRP, the bottom plate of the differential negative capacitor B6 to VRN, and the bottom plates of all capacitors B6 to B16 to VRN. The second step is to convert the SAR ADC composed of the capacitor array B1 to B4, the comparator, and the logic module. This will produce four conversion results: D4_p, D3_p, D2_p, and D1_p. After weighted summation, B6_p = D4_p*8 + D3_p*4 + D2_p*2 + D1_p*1 (where the exponents 8, 4, 2, and 1 are the capacitance values or relative ratios of capacitors B1 to B4). The third step is to connect the bottom plate of the differential positive capacitor B6 to VRN and the bottom plate of the differential negative capacitor B6 to VRP. The other capacitor connections remain unchanged. The fourth step is the same as the second step, obtaining four conversion results: D4_n, D3_n, D2_n, and D1_n. After weighted summation, B6_n = D4_n*8 + D3_n*4 + D2_n*2 + D1_n*1. The fifth step is to calculate the calibration weight of capacitor B6: B6_cal = B6_p - B6_n. This value is stored in efuse. B6_cal will be called every subsequent time digital domain weighting is performed.

[0062] Taking the calibration capacitor B7 as an example, the first step is to connect the bottom plates of all capacitors B1 to B4 to VRN, the bottom plate of the differential positive capacitor B7 to VRP, the bottom plate of the differential negative capacitor B7 to VRN, and the bottom plates of all capacitors B7 to B17 to VRN. The second step is to convert the SAR ADC composed of the capacitor array B1 to B4, the comparator, and the logic module. This will produce four conversion results: D4_p, D3_p, D2_p, and D1_p. After weighted summation, B7_p = D4_p*8 + D3_p*4 + D2_p*2 + D1_p*1 (where the exponents 8, 4, 2, and 1 are the capacitance values or relative ratios of capacitors B1 to B4). The third step is to connect the bottom plate of the differential positive capacitor B7 to VRN and the bottom plate of the differential negative capacitor B7 to VRP. The other capacitor connections remain unchanged. The fourth step is the same as the second step, obtaining four conversion results: D4_n, D3_n, D2_n, and D1_n. After weighted summation, B7_n = D4_n*8 + D3_n*4 + D2_n*2 + D1_n*1. The fifth step is to calculate the calibration weight of capacitor B7: B7_cal = B7_p - B7_n. This value is stored in efuse and will be used for each subsequent digital domain weighting.

[0063] Similar operations can be performed to obtain the calibration weight value B16_cal for capacitor B16. After calibration, the SAR ADC enters normal conversion mode. Each time the SAR ADC completes a conversion, it generates 16 digital codes: D16, D15, D14, ..., D2, D1. The digital domain is weighted according to the following formula:

[0064] Dout=D16*B16_cal+D15*B15_cal+D14*B14_cal+……+D5*B5_cal+D4*2^8+D3*2^4+D2*2^2+D1*2^1.

[0065] Because B16_cal, B15_cal…B5_cal are calculated based on actual capacitance values, the output Dout can better approximate the analog input voltage, realizing a high-precision SAR ADC.

[0066] In simple terms, during the calibration process, 1) the DAC formed by B1, B2, B3, and B4 is used to measure the actual weights of B5 to B16; (2) the calibration order is B5-->B16, and B5_cal to B16_cal are obtained and stored in the memory; (3) B5_cal to B16_cal are called during the actual conversion to complete the weight addition in the digital domain.

[0067] In summary, a successive approximation analog-to-digital converter includes: a capacitor array, the capacitor array includes N groups of differential capacitors and a switch array, each group of differential capacitors includes a differential positive capacitor and a differential negative capacitor, the switch array is configured to connect the differential positive capacitors and the differential negative capacitors of the N groups of differential capacitors to a positive reference voltage and an inverting reference voltage, respectively, where N>1, and the N groups of differential capacitors include n groups of low-order differential capacitors and m groups of high-order differential capacitors, where n+m=N; a comparator, the first input terminal of the comparator is connected to the differential positive capacitors in each group of differential capacitors to respectively receive the voltage of the differential positive capacitors, the second input terminal of the comparator is connected to the differential negative capacitors in each group of differential capacitors to respectively receive the voltage of the differential negative capacitors, and outputs the voltage measurement value of each group of differential capacitors. A logic module is used to obtain calibration weight values of m groups of high-order differential capacitors based on the voltage measurement values of n groups of low-order differential capacitors, and to calibrate the voltage measurement value of each group of high-order differential capacitors according to the obtained calibration weight value of each group of high-order differential capacitors, so as to generate a conversion output value according to the voltage measurement values of the n groups of low-order differential capacitors and the voltage measurement values and calibration weight values of the m groups of high-order differential capacitors.

[0068] In the process of calibrating each group of high-order differential capacitors, all low-order differential capacitors are connected to an inverting reference voltage, the bottom plates of the differential positive capacitors of the group of high-order differential capacitors are connected to the positive reference voltage and the bottom plates of the differential negative capacitors are connected to the inverting reference voltage, and all other groups of high-order differential capacitors are connected to the inverting reference voltage. The analog-to-digital converter composed of the capacitor array, comparator and logic module of the low-order differential capacitors is used for conversion to obtain first conversion results of each low-order differential capacitor, and the first conversion results are weighted and summed to obtain a first calibration value. The bottom plates of the differential positive capacitors of the group of differential capacitors are connected to the inverting reference voltage and the bottom plates of the differential negative capacitors are connected to the positive reference voltage, and all other groups of differential capacitors are connected to the inverting reference voltage. The analog-to-digital converter composed of the capacitor array, comparator and logic module of the low-order differential capacitors is used for conversion to obtain second conversion results of each low-order differential capacitor, and the second conversion results are weighted and summed to obtain a second calibration value. The calibration weight value of the group of high-order differential capacitors is obtained by subtracting the second calibration value from the first calibration value.

[0069] The first calibration value is Dn_p*Cn+Dn-1_p*Cn-1+…+D1_p*C1, where Dn_p is the first conversion result of the n-th low-order differential capacitor, and Cn is the capacitance-related value of the n-th low-order differential capacitor; Dn-1_p is the first conversion result of the n-1-th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1-th low-order differential capacitor; D1_p is the first conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor; The second calibration value is Dn_n*Cn+Dn-1_n*Cn-1+…+D1_n*C1, where Dn_n is the second conversion result of the nth low-order differential capacitor, and Cn is the capacitance-related value of the nth low-order differential capacitor; Dn-1_n is the second conversion result of the n-1th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1th low-order differential capacitor; D1_n is the second conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor. After the analog-to-digital converter enters the normal conversion mode, the calibrated output value is: DN*BN_cal+DN-1*BN-1_cal+…+Dn*2^Cn+…+D1*2^C1, where DN is the conversion result of the Nth differential capacitor, BN_cal is the calibration weight value of the Nth differential capacitor, DN-1 is the conversion result of the N-1th differential capacitor, BN-1_cal is the calibration weight value of the N-1th differential capacitor, Dn is the conversion result of the nth low-order differential capacitor, and D1 is the conversion result of the 1st low-order differential capacitor.

[0070] According to a further embodiment of the present disclosure, a successive approximation analog-to-digital conversion method is also provided. Figure 6 A flow chart according to the method is shown.

[0071] In step S102, all low-order differential capacitors are connected to an inverting reference voltage, the bottom plates of the differential positive capacitors of a group of high-order differential capacitors are connected to a positive reference voltage and the bottom plates of the differential negative capacitors are connected to an inverting reference voltage, and all other groups of high-order differential capacitors are connected to an inverting reference voltage. The analog-to-digital converter composed of the capacitor array, comparator and logic module of the low-order differential capacitors is used for conversion to obtain a first conversion result of each low-order differential capacitor, and the weighted sum of each first conversion result is used to obtain a first calibration value.

[0072] In step S104, the bottom plates of the differential positive capacitors of the group of differential capacitors are connected to the inverting reference voltage and the bottom plates of the differential negative capacitors are connected to the positive reference voltage, and all other groups of differential capacitors are connected to the inverting reference voltage. The analog-to-digital converter composed of the capacitor array, comparator and logic module of the low-order differential capacitors is used for conversion to obtain the second conversion results of each low-order differential capacitor, and the weighted sum of each second conversion result is used to obtain the second calibration value.

[0073] In step S106 , the calibration weight value of the group of high-order differential capacitors is obtained by subtracting the second calibration value from the first calibration value.

[0074] Repeat at least the steps to obtain the calibration weight value of each group of high-bit differential capacitors.

[0075] In step S108 , a conversion output value is generated by multiplying the calibration weight value of each group of high-order differential capacitors by the conversion result and according to the conversion result of each group of low-order differential capacitors.

[0076] It includes N groups of differential capacitors, N>1, the N groups of differential capacitors include n groups of low-order differential capacitors and m groups of high-order differential capacitors, where n+m=N, and each group of high-order differential capacitors obtains its own calibration weight value based on the n groups of low-order differential capacitors.

[0077] The first calibration value is Dn_p*Cn+Dn-1_p*Cn-1+…+D1_p*C1, where Dn_p is the first conversion result of the n-th low-order differential capacitor, and Cn is the capacitance-related value of the n-th low-order differential capacitor; Dn-1_p is the first conversion result of the n-1-th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1-th low-order differential capacitor; D1_p is the first conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor;

[0078] The second calibration value is Dn_n*Cn+Dn-1_n*Cn-1+…+D1_n*C1, where Dn_n is the second conversion result of the nth low-order differential capacitor, and Cn is the capacitance-related value of the nth low-order differential capacitor; Dn-1_n is the second conversion result of the n-1th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1th low-order differential capacitor; D1_n is the second conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor.

[0079] After entering the normal conversion mode, the calibrated output value is: DN*BN_cal+DN-1*BN-1_cal+…+Dn*2^Cn+…+D1*2^C1, where DN is the conversion result of the Nth differential capacitor, BN_cal is the calibration weight value of the Nth differential capacitor, DN-1 is the conversion result of the N-1th differential capacitor, BN-1_cal is the calibration weight value of the N-1th differential capacitor, Dn is the conversion result of the nth low-order differential capacitor, and D1 is the conversion result of the 1st low-order differential capacitor.

[0080] In the description of this specification, the description with reference to the terms "one embodiment / method", "some embodiments / methods", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment / method or example are included in at least one embodiment / method or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / method or example. Moreover, the specific features, structures, materials or characteristics described may be combined in an appropriate manner in any one or more embodiments / methods or examples. In addition, those skilled in the art may combine and combine different embodiments / methods or examples described in this specification and the features of different embodiments / methods or examples, unless they are contradictory.

[0081] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0082] Those skilled in the art will appreciate that the above embodiments are merely intended to clearly illustrate the present disclosure and are not intended to limit the scope of the present disclosure. Other changes or modifications may be made based on the above disclosure, and such changes or modifications are still within the scope of the present disclosure.

Claims

1. A successive approximation analog-to-digital converter, characterized in that include: A capacitor array, the capacitor array comprising N groups of differential capacitors and a switch array, each group of differential capacitors comprising a differential positive capacitor and a differential negative capacitor, the switch array being configured to connect the differential positive capacitors and the differential negative capacitors of the N groups of differential capacitors to a positive reference voltage and a negative reference voltage, respectively, where N>1, and the N groups of differential capacitors comprising n groups of low-order differential capacitors and m groups of high-order differential capacitors, where n+m=N; a comparator, wherein a first input terminal of the comparator is connected to the differential positive capacitors in each group of differential capacitors to respectively receive the voltage of the differential positive capacitors, a second input terminal of the comparator is connected to the differential negative capacitors in each group of differential capacitors to respectively receive the voltage of the differential negative capacitors, and outputs a voltage measurement value of each group of differential capacitors; as well as A logic module is configured to obtain calibration weight values of m groups of high-order differential capacitors based on the voltage measurement values of n groups of low-order differential capacitors, and calibrate the voltage measurement value of each group of high-order differential capacitors according to the obtained calibration weight value of each group of high-order differential capacitors, so as to generate a conversion output value according to the voltage measurement values of the n groups of low-order differential capacitors and the voltage measurement values and calibration weight values of the m groups of high-order differential capacitors. In the process of calibrating each group of high-order differential capacitors, all low-order differential capacitors are connected to an inverting reference voltage, the bottom plate of the differential positive capacitor of the group of high-order differential capacitors is connected to the positive reference voltage and the bottom plate of the differential negative capacitor is connected to the inverting reference voltage, and all other groups of high-order differential capacitors are connected to the inverting reference voltage. The analog-to-digital converter composed of the capacitor array, comparator and logic module of the low-order differential capacitor is used for conversion to obtain a first conversion result of each low-order differential capacitor, and the weighted sum of each first conversion result is obtained to obtain a first calibration value. The bottom plate of the differential positive capacitor of the group of differential capacitors is connected to the inverting reference voltage and the bottom plate of the differential negative capacitor is connected to the positive reference voltage, and all other groups of differential capacitors are connected to the inverting reference voltage. The analog-to-digital converter composed of the capacitor array, comparator and logic module of the low-order differential capacitor is used for conversion to obtain a second conversion result of each low-order differential capacitor, and the weighted sum of each second conversion result is obtained to obtain a second calibration value. The calibration weight value of the group of high-order differential capacitors is obtained by subtracting the second calibration value from the first calibration value.

2. The successive approximation analog-to-digital converter according to claim 1, wherein A memory is also included, and the memory is used to store the obtained calibration weight value, so that the calibration weight value can be called when the analog-to-digital converter is actually working to calibrate the voltage measurement value of each group of high-bit differential capacitors.

3. The successive approximation analog-to-digital converter according to claim 1, wherein For the m groups of high-order differential capacitors, calibration weight values corresponding to the respective groups of high-order differential capacitors are obtained in sequence according to the voltage measurement values of the n groups of low-order differential capacitors.

4. The successive approximation analog-to-digital converter according to claim 1, wherein: The first calibration value is Dn_p×Cn+Dn-1_p×Cn-1+…+D1_p×C1, where Dn_p is the first conversion result of the n-th low-order differential capacitor, and Cn is the capacitance-related value of the n-th low-order differential capacitor; Dn-1_p is the first conversion result of the n-1-th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1-th low-order differential capacitor; D1_p is the first conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor; The second calibration value is Dn_n×Cn+Dn-1_n×Cn-1+…+D1_n×C1, where Dn_n is the second conversion result of the nth low-order differential capacitor, and Cn is the capacitance-related value of the nth low-order differential capacitor; Dn-1_n is the second conversion result of the n-1th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1th low-order differential capacitor; D1_n is the second conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor.

5. The successive approximation analog-to-digital converter according to claim 4, wherein: After the analog-to-digital converter enters normal conversion mode, the calibrated output value is: DN×BN_cal+DN-1×BN-1_cal+…+Dn×2^Cn+…+ D1×2^C1, where DN is the conversion result of the Nth differential capacitor, BN_cal is the calibration weight value of the Nth differential capacitor, DN-1 is the conversion result of the N-1th differential capacitor, BN-1_cal is the calibration weight value of the N-1th differential capacitor, Dn is the conversion result of the nth low-order differential capacitor, and D1 is the conversion result of the 1st low-order differential capacitor.

6. A successive approximation analog-to-digital conversion method, characterized in that: include: Connect all low-order differential capacitors to an inverting reference voltage, connect the bottom plates of the differential positive capacitors of a group of high-order differential capacitors to the positive reference voltage and the bottom plates of the differential negative capacitors to the inverting reference voltage, and connect all other groups of high-order differential capacitors to the inverting reference voltage. Perform conversion using an analog-to-digital converter composed of a capacitor array, a comparator, and a logic module of the low-order differential capacitors to obtain first conversion results of each low-order differential capacitor, and perform weighted summation of each first conversion result to obtain a first calibration value. The bottom plates of the differential positive capacitors of the group of differential capacitors are connected to an inverting reference voltage and the bottom plates of the differential negative capacitors are connected to a positive reference voltage, and all other groups of differential capacitors are connected to an inverting reference voltage. A second conversion result of each low-order differential capacitor is obtained by performing conversion using an analog-to-digital converter composed of a capacitor array, a comparator, and a logic module. The second conversion results are weighted and summed to obtain a second calibration value. Obtaining the set of high-order differential capacitance calibration weight values by subtracting the second calibration value from the first calibration value; Repeat at least the steps to obtain the calibration weight value of each group of high-order differential capacitors; as well as The conversion output value is generated by multiplying the calibration weight value of each group of high-order differential capacitors by the conversion result and according to the conversion result of each group of low-order differential capacitors.

7. The method according to claim 6, wherein It includes N groups of differential capacitors, N>1, the N groups of differential capacitors include n groups of low-order differential capacitors and m groups of high-order differential capacitors, where n+m=N, and each group of high-order differential capacitors obtains its own calibration weight value based on the n groups of low-order differential capacitors.

8. The method according to claim 7, wherein The first calibration value is Dn_p×Cn+Dn-1_p×Cn-1+…+D1_p×C1, where Dn_p is the first conversion result of the n-th low-order differential capacitor, and Cn is the capacitance-related value of the n-th low-order differential capacitor; Dn-1_p is the first conversion result of the n-1-th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1-th low-order differential capacitor; D1_p is the first conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor; The second calibration value is Dn_n×Cn+Dn-1_n×Cn-1+…+D1_n×C1, where Dn_n is the second conversion result of the nth low-order differential capacitor, and Cn is the capacitance-related value of the nth low-order differential capacitor; Dn-1_n is the second conversion result of the n-1th low-order differential capacitor, and Cn-1 is the capacitance-related value of the n-1th low-order differential capacitor; D1_n is the second conversion result of the 1st low-order differential capacitor, and C1 is the capacitance-related value of the 1st low-order differential capacitor.

9. The method according to claim 8, wherein After entering normal conversion mode, the calibrated output value is: DN×BN_cal+DN-1×BN-1_cal+…+Dn×2^Cn+…+ D1×2^C1, where DN is the conversion result of the Nth differential capacitor, BN_cal is the calibration weight value of the Nth differential capacitor, DN-1 is the conversion result of the N-1th differential capacitor, BN-1_cal is the calibration weight value of the N-1th differential capacitor, Dn is the conversion result of the nth low-order differential capacitor, and D1 is the conversion result of the 1st low-order differential capacitor.

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