Multi-channel data training method based on joint phase adjustment

Abstract

The present invention relates to a multi-channel data training method based on joint phase adjustment. In this method, a receiver samples a fixed-code training word sent by a transmitter in real time. The FPAG control logic delays the input data by adjusting the IODLEAY data delay unit, completing multi-channel delay alignment. The FPAG control logic adjusts the sampling clock phase by controlling the DCM unit. The FPAG control logic controls the receiver latch position until the data position identical to the training word sent by the transmitter is latched, completing data training. The present invention utilizes the DCM clock management unit and the IODELAY data delay unit within the FPGA to achieve joint phase adjustment of the sampling clock and data input delay, effectively improving the training reliability of high-speed data communications, ensuring that high-speed data can be reliably acquired by the receiver, reducing the bit error rate, and extending its applicability.

Description

Technical Field

[0001] The present invention relates to the technical field of image transmission, and in particular to a multi-channel data training method based on joint phase adjustment. Background Art

[0002] As the resolution of digital image acquisition systems continues to increase, the amount of data output by image sensor chips is also increasing, and the number of data transmission channels is also increasing. For multi-channel high-speed signal transmission, differences in the drive circuits and physical connections such as PCB traces between each transmission channel lead to inconsistent data transmission link latency. This latency is also affected to a certain extent by factors such as operating voltage and temperature. Due to the differences in transmission delay between channels, the input data of each channel has a different phase relationship with the sampling clock, resulting in different setup and hold times for the input data of each channel relative to the sampling clock. The sample-and-hold time margin of each channel may be small, or even fail to meet the sampling requirements of the receiver, making it impossible to accurately and reliably acquire data, resulting in communication errors or increased bit error rates.

[0003] In order to overcome the problem that the high-speed data sent by each channel cannot be reliably sampled by the receiver, data training is required. In high-speed data communication, the data transmitter usually sends fixed and known code data, and the receiver completes data training by sampling the code data. Existing data training methods usually use a single IODELAY data delay unit in the FPGA to achieve delay control of the input data of each channel, search the IODELAY delay time span, find the optimal position of each channel relative to the sampling clock, and complete high-speed communication data training. However, due to the inherent limitations of FPGA hardware, the delay adjustment range of the IODELAY data delay unit is limited. When the transmission frequency is less than a certain value, it cannot cover the 1-bit data time width, resulting in unreliable training results or even training failure. It is also impossible to effectively take into account both asynchronous and synchronous transmission modes at the same time. Summary of the Invention

[0004] In order to solve the problems of unreliable training results or even training failure in existing multi-channel data training methods and the inability to effectively take into account both asynchronous and synchronous transmission modes, the present invention provides a multi-channel data training method based on joint phase adjustment.

[0005] In order to solve the above problems, the present invention adopts the following technical solutions:

[0006] A multi-channel data training method based on joint phase adjustment: multi-channel input data sent by a transmitter is input into an IODELAY data delay unit, and the delayed data output by the IODELAY data delay unit is input into a receiver; a clock input signal passes through a clock management unit (DCM) and is output to the receiver as the sampling clock of the receiver; FPGA control logic controls the data delay of the IODELAY data delay unit and is also used to control the clock management unit (DCM) to achieve phase adjustment of the sampling clock;

[0007] The multi-channel data training method is implemented by the following steps:

[0008] Step 1: The receiver samples the fixed pattern training word sent by the transmitter in real time. The FPAG control logic controls the delay of the input data by adjusting the IODLEAY data delay unit. For each delay adjustment step, the receiver performs multiple continuous acquisitions. If the continuous acquisition results are the same, it is determined to be a stable range. If the continuous acquisition results are different, it is determined to be an unstable range. When all channels are in the sampling unstable range, multi-channel delay alignment is completed.

[0009] Step 2: The FPAG control logic adjusts the sampling clock phase by controlling the clock management unit DCM unit. The specific adjustment process is as follows:

[0010] Search the entire range of the DCM control phase, and record the clock phase position and the clock phase span of each channel in the stable area.

[0011] After the search is completed, the maximum clock phase span Pspan of each channel in the stable area and the corresponding clock phase starting position Pstart are selected, and the sampling clock phase is adjusted to Pstart+Pspan / 2. The adjusted sampling clock phase is the final sampling clock phase, and the bit training is completed;

[0012] Step 3: The FPAG control logic controls the receiver latch position until it latches the same data position as the training word sent by the transmitter, thus completing the data training.

[0013] The beneficial effects of the present invention are:

[0014] The present invention utilizes a clock management unit (DCM) in conjunction with an IODELAY data delay unit within an FPGA to simultaneously perform joint phase adjustment on the sampling clock phase and data input delay of a receiver. When a high-speed data transmitter sends a training word with a fixed code pattern, the receiver detects the corresponding training word and adaptively implements inter-channel transmission delay alignment, bit training, and word training in sequence to complete data training. This effectively improves the training reliability of high-speed data communication, thereby ensuring that high-speed data can be reliably collected by the receiver and reducing the bit error rate. Furthermore, the multi-channel data training method of the present invention is applicable to data communication using either synchronous or asynchronous modes, and has a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the principle of the multi-channel data training method based on joint phase adjustment described in the present invention. DETAILED DESCRIPTION

[0016] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0017] The present invention provides a multi-channel data training method based on the joint phase adjustment of sampling clock phase and IO delay. The method utilizes the clock management unit DCM and the IODELAY data delay unit with clock dynamic phase adjustment function inside the FPGA to realize the joint phase adjustment of the sampling clock and data input delay.

[0018] like Figure 1 As shown, the multi-channel input data sent by the transmitter is input in series to the IODELAY data delay unit, and the delayed data output by the IODELAY data delay unit is input to the receiver. The clock input signal is output to the receiver as the sampling clock of the receiver after passing through the clock management unit DCM. The receiver can be an ISERDER module inside the FPGA to implement serial-to-parallel conversion or a general register. Since the receiver is a synchronous device regardless of the implementation method, the clock input signal samples the delayed data to complete the data transmission. The sampling clock can come from the local clock of the data transmitter or the receiver, that is, data communication is performed in a synchronous manner or an asynchronous manner. Therefore, the multi-channel data training method of the present invention can be applicable to synchronous data reception or asynchronous data reception, and has a wider range of applications. While the FPGA control logic controls the data delay of the IODELAY data delay unit, it is also used to effectively control the clock management unit DCM unit to achieve phase adjustment of the sampling clock.

[0019] Specifically, the high-speed data transmitter sends a training word with a fixed code pattern. When the receiver detects the corresponding training word, it adaptively implements inter-channel transmission delay alignment, bit training, and word training in sequence to complete data training. This method mainly completes training through the following three steps:

[0020] Step 1: Multi-channel delay alignment:

[0021] The receiver samples the fixed-pattern training words sent by the transmitter in real time. The FPAG control logic delays the input data by adjusting the IODLEAY data delay unit. With each delay adjustment, the receiver performs multiple consecutive acquisitions. If the consecutive acquisition results are the same, the signal is considered stable; if the consecutive acquisition results are different, the signal is considered unstable. When all channels are in the unstable sampling interval, multi-channel delay alignment is complete.

[0022] Step 2: Position training:

[0023] After completing multi-channel delay alignment, bit training is performed. The FPGA control logic adjusts the sampling clock phase by controlling the DCM. The specific adjustment process is as follows: the entire range of the DCM phase control is searched, and the clock phase position and the clock phase span of each channel in the stable zone are recorded. After the search is completed, the maximum clock phase span Pspan of each channel in the stable zone and the corresponding clock phase starting position Pstart are selected. The clock phase is adjusted to Pstart + Pspan / 2. This adjusted sampling clock phase is the final sampling clock phase, completing bit training.

[0024] Step 3: Word training:

[0025] After bit training is complete, each channel can achieve stable and reliable data acquisition. Each channel then performs word training. The FPGA control logic controls the receiver latch position until it latches the same data position as the training word sent by the transmitter. This completes word training.

[0026] Compared with traditional training methods, the present invention combines the clock management unit DCM and the FPGA's internal IODELAY data delay unit, and simultaneously performs joint phase adjustment on the receiver's sampling clock phase and data input delay, breaking away from the inherent hardware limitations of the FPGA and limiting the applicability of multi-channel data training methods or devices. This effectively improves the training reliability of high-speed data communications, ensures that high-speed data can be reliably collected by the receiver, and reduces the bit error rate.

[0027] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0028] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A multi-channel data training method based on joint phase adjustment, characterized in that: The multi-channel input data sent by the transmitter is input to the IODELAY data delay unit, and the delayed data output by the IODELAY data delay unit is input to the receiver. The clock input signal passes through the clock management unit DCM and is output to the receiver as the sampling clock of the receiver. The clock input signal comes from the transmitter or the local clock of the receiver, and is suitable for synchronous data reception or asynchronous data reception. The FPGA control logic controls the data delay of the IODELAY data delay unit and is also used to control the clock management unit DCM unit to achieve phase adjustment of the sampling clock. The multi-channel data training method is implemented by the following steps: Step 1: The receiver samples the fixed pattern training word sent by the transmitter in real time. The FPAG control logic controls the delay of the input data by adjusting the IODLEAY data delay unit. For each delay adjustment step, the receiver performs multiple continuous acquisitions. If the continuous acquisition results are the same, it is determined to be a stable range. If the continuous acquisition results are different, it is determined to be an unstable range. When all channels are in the sampling unstable range, multi-channel delay alignment is completed. Step 2: The FPAG control logic adjusts the sampling clock phase by controlling the clock management unit DCM unit. The specific adjustment process is as follows: Search the entire range of the DCM control phase, and record the clock phase position and the clock phase span of each channel in the stable area. After the search is completed, the maximum clock phase span Ps of each channel in the stable area is selected p an and the corresponding clock phase starting position Ps t ar t , adjust the sampling clock phase to Ps t ar t +Ps p an / 2, the adjusted sampling clock phase is the final sampling clock phase, completing bit training; Step 3: The FPAG control logic controls the receiver latch position until it latches the same data position as the training word sent by the transmitter, thus completing the data training.

2. The multi-channel data training method based on joint phase adjustment according to claim 1, characterized in that: The receiver is an ISERDER module inside the FPGA to implement serial-to-parallel conversion or a general register.

Images