Semiconductor memory base transistor circuit and method of fabrication

Abstract

The application relates to a semiconductor memory bottom transistor circuit and a preparation method, and relates to integrated circuit technology. The circuit comprises a column line layer arranged above a row line layer, an insulating isolation layer between the row line layer and the column line layer, and the directions of the row line and the column line being perpendicular to each other. A hole penetrating through the column line layer and the insulating isolation layer is arranged at the intersection of the row line and the column line. The hole is filled with two sections of semiconductor materials, the doping type of the semiconductor material in the upper section of the hole is the same as that of the row line, and the doping type of the semiconductor material in the lower section of the hole is opposite to that of the row line. A triode is formed at the position of each hole. The preparation process is simple, and the cost is low.

Description

TECHNICAL FIELD

[0001] The present application relates to integrated circuit technology, in particular to semiconductor memory technology. BACKGROUND

[0002] The existing 3D memory such as NAND memory, resistive random memory, phase change memory, etc. can usually use a MOS tube of a planar process as a selection tube of a vertical bit line of the 3D memory. Since the critical dimension and the occupied area of the MOS selection tube need to be adapted to the highly compact 3D memory array, the use of the MOS selection tube with the size limited by the planar process can cause the subsequent stacked 3D memory to occupy more chip area. Another selection tube is a vertical MOS selection tube (Wang et al., IEEE (2012)) or a vertical BJT selection tube (Wang et al., IEEE (2010)), which is prepared below the active area of the substrate. Other necessary peripheral circuits (such as I / O circuits, control circuits, etc.) can only be set in the periphery of the 3D memory array which occupies most of the chip area, further consuming a certain chip area. Another vertical MOS selection tube (US 9,065,044 B2) set on the substrate instead of below the substrate avoids the above problems, but needs a complex and difficult-to-control high-temperature annealing process to heavily dope the source to perform out-diffusion on the lightly doped MOS channel of different conductive types, which has a high process cost. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a semiconductor memory bottom transistor circuit and a preparation method, which have the characteristics of low cost and high reliability.

[0004] The technical solution adopted by the present application to solve the technical problem is that the semiconductor memory bottom transistor circuit comprises a column line layer arranged above a row line layer, and an insulating isolation layer between the row line layer and the column line layer,

[0005] The row line layer is provided with a predetermined number of row lines composed of doped semiconductor materials,

[0006] The column line layer comprises an insulating material and a predetermined number of column lines arranged in the insulating material, and the column lines are composed of conductive materials;

[0007] The directions of the row lines and the column lines are perpendicular to each other; and a hole penetrating the column line layer and the insulating isolation layer is arranged at the intersection of the row lines and the column lines;

[0008] The holes are filled with semiconductor materials in two sections, the semiconductor material in the upper section of the hole is of the same doping type as the row line, and the semiconductor material in the lower section of the hole is of the opposite doping type as the row line, and a transistor is formed at the position of each hole; the semiconductor material in the upper section of the hole and the material of the row line are one of the materials required for the collector region of the transistor and the other is the material required for the emitter region of the transistor, and the semiconductor material in the lower section of the hole is the material required for the base region of the transistor.

[0009] The semiconductor material in the lower section of the hole is in contact with the column line and the row line at the bottom of the hole.

[0010] Further, the holes are rectangular holes, and can also be oval or circular holes.

[0011] The material of the column line is a doped semiconductor material, a metal silicide or a metal conductive material.

[0012] The preparation method of the semiconductor memory bottom transistor circuit provided by the application comprises the following steps:

[0013] (1) a row line layer is arranged on the bottom base circuit layer, the row line layer has parallel and predetermined number of row lines, and the row lines are composed of low-resistance doped semiconductor materials;

[0014] (2) an insulating isolation layer is arranged on the row line layer, and then a column line layer is arranged on the insulating isolation layer, the column line layer comprises insulating materials and parallel and predetermined number of column lines arranged in the insulating materials, the column lines are perpendicular to the row lines, and the column lines are composed of conductive materials;

[0015] (3) holes are formed at the intersection of the row lines and the column lines, the holes penetrate the column line layer and the insulating isolation layer, the row lines are exposed at the bottom of the holes, and the opening of the holes is located on the upper surface of the column line layer;

[0016] (4) the lower section of the hole is filled with semiconductor materials of the opposite doping type as the row line, and then the upper section of the hole is filled with semiconductor materials of the same doping type as the row line, and the bottom surface of the semiconductor material in the upper section of the hole is higher than the top surface of the column line.

[0017] Further, the following steps are included: each row line and each column line are connected to the bottom base circuit layer, and the material in the upper end of the hole is connected to the vertical bit line of the upper end multi-layer stacked memory array.

[0018] The "opposite doping type" in the application is for the two doping types of P-type doping and N-type doping, and for the two materials, if both are N-type doping or both are P-type doping, they are of the same doping type, and if one is N-type doping and the other is P-type doping, they are of the opposite doping type.

[0019] The semiconductor memory bottom-layer transistor circuit of this invention can be used to select the vertical bit lines of a 3D memory array. The fabrication process is simple and low-cost. The circuit of this invention does not need to be fabricated in the active region of the bottom substrate, making it compatible with highly integrated 3D stacked devices. Other necessary peripheral circuits (such as I / O circuits, control circuits, etc.) can be located in the active region of the bottom substrate, saving chip area. This invention uses a vertical transistor as the selection device, which can provide higher driving capability, operate at a lower turn-on voltage, and the device operation does not rely on the optimization and precise control of the gate oxide layer thickness as with MOSFETs, thus offering higher tolerance for process requirements. Attached Figure Description

[0020] Figure 1 This is the schematic diagram of US 9065044 B2.

[0021] Figure 2 This is a top view of step (1) of Example 1.

[0022] Figure 3 This is a schematic diagram of the cross section (longitudinal section) along A-A' in step (1) of Example 1.

[0023] Figure 4 This is a top-view schematic diagram of step 2a of Example 1.

[0024] Figure 5 This is a schematic cross-sectional view along the A-A' direction of step 2a in Example 1.

[0025] Figure 6 This is a longitudinal cross-sectional view of step 2b in Example 1.

[0026] Figure 7 This is a top view of step (3) of Example 1.

[0027] Figure 8 This is a schematic diagram of the cross section along A-A' in step (3) of Example 1.

[0028] Figure 9 This is a longitudinal cross-sectional view of step (4) of Example 1.

[0029] Figure 10 This is a longitudinal cross-sectional view of step (5) of Example 1.

[0030] Figure 11 Schematic diagram of the structure of Example 3.

[0031] Figure 12 This is a top view schematic diagram of an embodiment with a rectangular hole.

[0032] Explanation of reference numerals in the attached figures:

[0033] 201: Line

[0034] 202: Insulation layer

[0035] 203: Column line

[0036] 204: Insulating material

[0037] 1101: Vertical Position Line

[0038] 1102: Polysilicon Row Line

[0039] 1103: Polycrystalline silicon array line

[0040] 1104: Vertical column base area

[0041] 1105: Top vertical collector Detailed Implementation

[0042] In the semiconductor memory bottom-layer transistor circuit of this invention, the transistor at the intersection of the row and column lines is a vertical transistor. The base region is vertically connected to the upper emitter region and the lower collector region. The column line serves as the base electrode, wrapping the base region and is isolated from the upper collector region and the lower emitter region (collector electrode) by an insulating material. Depending on the application requirements, the emitter region can also be set at the upper end and the collector region at the lower end. (Note: Since the emitter region usually has a higher doping concentration, the end with a higher doping concentration and better conductivity can naturally be used as the row line, but the reverse is also possible.) Since the base region thickness is generally around 0.1 μm, the thickness of the isolation layer should not be too large (usually less than 0.02 μm) to avoid the base region electrode being too thin, which would increase the base region conductivity resistance.

[0043] Example 1: Preparation method, see [link to example]. Figures 2-12 .

[0044] This embodiment includes the following steps:

[0045] (1) A row line layer is provided on the bottom basic circuit layer, the row line layer having a predetermined number of parallel row lines 201, the row lines being made of doped low-resistivity semiconductor material, see [reference]. Figure 2 and Figure 3 ;

[0046] (2) Cover the row layer with an insulating layer 202, and then construct the column layer above the insulating layer by the steps (2a) and (2b) below:

[0047] 2a. A predetermined number of parallel column lines 203 are provided on the upper surface of the insulating layer 202, the column lines being perpendicular to the row lines, and the column lines being made of conductive material; see also Figure 4 , Figure 5 ;

[0048] 2b. Cover the rows with insulating material 204, see [reference].Figure 6 ;

[0049] (3) A hole is made at the intersection of the row lines and column lines, penetrating the column line layer and the insulating layer. The row line material is exposed at the bottom of the hole, and the opening of the hole is located on the upper surface of the column line layer. See [reference needed] Figure 7 and Figure 8 ;

[0050] (4) In the lower section of the hole, fill with a semiconductor material with a doping type opposite to that of the row lines, see [reference]. Figure 9 ;

[0051] (5) Fill the upper section of the hole with a semiconductor material of the same doping type as the row line (implant impurities of the same conductivity type as the row line into the upper section of the hole) (Note: Figure 9 The entire channel is already filled, so it is necessary to inject impurities into the upper region to make the upper segment a semiconductor material with a different conductivity type; if this step uses the filling method described in the original text to form the upper structure, then... Figure 9 The upper part can be shown as empty (either step is acceptable), and the bottom surface of the semiconductor material in the upper section of the hole is higher than the top surface of the column line, see [reference]. Figure 10 .

[0052] Example 2: See Figure 10 .

[0053] The semiconductor memory bottom-layer transistor circuit of the present invention includes a column line layer disposed above the row line layer, and an insulating isolation layer is provided between the row line layer and the column line layer.

[0054] The row line layer contains a predetermined number of row lines made of doped low-resistivity semiconductor material.

[0055] The row line layer includes an insulating material and a predetermined number of row lines disposed in the insulating material, the row lines being made of a conductive material;

[0056] The directions of the row lines and column lines are perpendicular to each other; holes penetrating the column line layer and the insulating isolation layer are provided at the intersection of the row lines and column lines;

[0057] The hole is filled with two sections of semiconductor material. The doping type of the semiconductor material in the upper section of the hole is the same as that of the row line, while the doping type of the semiconductor material in the lower section of the hole is opposite to that of the row line. A transistor is formed at the position of each hole. One of the semiconductor materials in the upper section of the hole and the materials in the row line are materials that meet the requirements of the collector region of the transistor, and the other is a material that meets the requirements of the emitter region of the transistor. The semiconductor material in the lower section of the hole is a material that meets the requirements of the base region of the transistor.

[0058] The semiconductor material located in the lower section of the hole is in contact with the column lines and the row lines at the bottom of the hole.

[0059] Figure 12An embodiment of a rectangular hole is shown.

[0060] Example 3:

[0061] See Figure 11 Using Example 2 as the bottom-level selection circuit of the three-dimensional semiconductor memory, the emitter is connected to the vertical bit line 1101 of the stacked memory cell of the three-dimensional memory.

[0062] This embodiment consists of the three-dimensional memory above and the following parts:

[0063] (1) The bottom serves as the collector of the polysilicon row line 1102 (N+ or P+).

[0064] (2) The polysilicon row line 1103 (P+ or N+) above the polysilicon row line serves as the base.

[0065] (3) Vertical pillar base region 1104 (P- or N-lightly doped) surrounded by polysilicon array lines 1103

[0066] (4) Top vertical collector 1105 (N+ or P+) connected to the vertical bit line of the three-dimensional memory stack memory cell.

Claims

1. A semiconductor memory base transistor circuit, characterized by, The column line layer is arranged above the row line layer, and the row line layer and the column line layer are separated by an insulating separation layer, The row line layer is provided with a predetermined number of row lines composed of doped semiconductor material, The column line layer is composed of insulating material and a predetermined number of column lines arranged in the insulating material, and the column lines are composed of conductive material; The row lines and the column lines are perpendicular to each other, and a hole penetrating the column line layer and the insulating separation layer is arranged at the intersection of the row line and the column line; The hole is filled with two sections of semiconductor material, the semiconductor material in the upper section of the hole has the same doping type as the row line, and the semiconductor material in the lower section of the hole has the opposite doping type to the row line, and a transistor is formed at the position of each hole; one of the semiconductor material in the upper section of the hole and the material of the row line is the material required for the collector region of the transistor, and the other is the material required for the emitter region of the transistor, and the semiconductor material in the lower section of the hole is the material required for the base region of the transistor; The semiconductor material in the lower section of the hole is in contact with the column line and the row line at the bottom of the hole.

2. The semiconductor memory pass transistor circuit of claim 1, wherein, The hole is a rectangular hole.

3. The semiconductor memory pass transistor circuit of claim 1, wherein, The material of the column line is doped semiconductor material.

4. A method of fabricating a semiconductor memory base transistor circuit, characterized by, The method comprises the following steps: (1) arranging a row line layer on the bottom base circuit layer, and the row line layer is provided with a predetermined number of parallel row lines composed of doped semiconductor material; (2) covering the row line layer with an insulating separation layer, and then arranging a column line layer above the insulating separation layer, and the column line layer is composed of insulating material and a predetermined number of parallel column lines arranged in the insulating material, and the column lines are perpendicular to the row lines and composed of conductive material; (3) arranging a hole penetrating the column line layer and the insulating separation layer at the intersection of the row line and the column line, and the row line is exposed at the bottom of the hole, and the opening of the hole is located on the upper surface of the column line layer; (4) filling the lower section of the hole with semiconductor material having the opposite doping type to the row line, and then filling the upper section of the hole with semiconductor material having the same doping type as the row line, and the bottom surface of the semiconductor material in the upper section of the hole is higher than the top surface of the column line.

5. The method for fabricating the underlying transistor circuit of a semiconductor memory as described in claim 4, characterized in that, The method further comprises the following steps: connecting each row line and each column line to the bottom base circuit layer.

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