A neuromorphic device with ferroelectric polarization effect and charge trapping effect and a preparation method thereof

Abstract

This invention discloses a neuromorphic device possessing both ferroelectric polarization and charge trapping effects. The device comprises a gate electrode, a gate insulating layer, a ferroelectric polarization layer, a charge trapping layer, an organic semiconductor layer, a source electrode, and a drain electrode. The gate insulating layer is located directly above the gate electrode, the ferroelectric polarization layer is located directly above the gate insulating layer, the charge trapping layer is located directly above the ferroelectric polarization layer, the organic semiconductor layer is located directly above the charge trapping layer, and the source and drain electrodes are located directly above the organic semiconductor layer. By adding the ferroelectric polarization layer and the charge trapping layer, the neuromorphic device of this invention simultaneously possesses both ferroelectric polarization and charge trapping effects, exhibits stable electrical performance, and has low fabrication cost. Therefore, this neuromorphic device with both ferroelectric polarization and charge trapping effects is expected to be widely applied in the integration of multifunctional devices.

Description

Technical Field

[0001] This invention relates to the field of organic semiconductors, specifically to a neuromorphic device with ferroelectric polarization and charge trapping effects and its fabrication method. Background Technology

[0002] With the continuous development of artificial intelligence, obstacle avoidance technology based on neuromorphic computing systems has made rapid progress and is widely used in various fields of life, such as deep learning-based vehicle obstacle avoidance systems. However, these functions are all implemented based on software algorithms, requiring complex hardware circuit designs as support. Inspired by biological processes of avoiding dangerous environments, simulating the functions of neurons and synapses in biological systems to achieve obstacle avoidance can simplify hardware circuits and enable obstacle avoidance functions in more complex environments. Unlike software-based deep learning algorithms, the strategy of building neuromorphic circuits at the hardware level relies on the exploration and development of biomimetic electronic components, such as brain-like artificial neuromorphic devices.

[0003] There are many types of artificial neuromorphic devices. Among them, two-terminal devices include memristors and resistive random access memories, while three-terminal devices include field-effect synaptic transistors, ferroelectric transistor memories, and electrolyte synaptic transistors. Ferroelectric transistor memories, in particular, have become a hot research topic due to their simple fabrication process, wide range of applications, and ability to be integrated with flexible devices.

[0004] The learning process of neuromorphic chips is an iterative process of weight updates. Currently, most neuromorphic devices only contain one type of charge mechanism, so weight updates can only be achieved through bipolar voltage pulse modulation. Bipolar voltage pulse modulation uses alternating positive and negative voltages to achieve excitation and inhibition in neuromorphic devices. However, this modulation method requires complex peripheral circuitry in chip design, which increases chip integration and manufacturing costs. Therefore, this modulation method is not suitable for the development trend of multifunctional and low-integration electronic hardware devices. Furthermore, the process of bipolar modulation to achieve transistor excitation and inhibition through switching between positive and negative voltages is actually a passive regulation process. The weight update curve of this bipolar modulation does not conform to the unipolar modulation characteristic of biological synaptic response curves, which shows excitation followed by inhibition over time after the same pulse stimulus. Therefore, researching and developing devices that can achieve unipolar weight modulation is of great significance.

[0005] In view of this, the present invention provides a neuromorphic device that combines ferroelectric polarization effect and charge trapping effect, and a method for fabricating the same. Summary of the Invention

[0006] Purpose of the invention: To address the aforementioned problems of existing neuromorphic devices, this invention proposes a neuromorphic device and its fabrication method that combines ferroelectric polarization and charge trapping effects. The ferroelectric polarization effect of the ferroelectric layer induces hole accumulation in the semiconductor layer, increasing its hole density; while the hole trapping effect of the charge trapping layer generates a built-in electric field to reduce the hole density, providing technical support for achieving unipolar pulse voltage-controlled weighting.

[0007] Summary of the invention: The present invention simultaneously introduces a ferropolarization layer and a charge trapping layer into the device to adjust the charge density of the organic semiconductor layer, so that the device has both ferropolarization effect and charge trapping effect.

[0008] The technical solution provided by this invention is as follows:

[0009] A neuromorphic device combining ferroelectric polarization and charge trapping effects includes a gate electrode, a gate insulating layer, a ferroelectric polarization layer, a charge trapping layer, an organic semiconductor layer, a source electrode, and a drain electrode. The gate insulating layer is located directly above the gate electrode, the ferroelectric polarization layer is located directly above the gate insulating layer, the charge trapping layer is located directly above the ferroelectric polarization layer, the organic semiconductor layer is located directly above the charge trapping layer, and the source electrode and drain electrode are located directly above the organic semiconductor layer.

[0010] Furthermore, the ferroelectric polarization layer forming material is polyvinylidene fluoride (PVDF).

[0011] Furthermore, the charge trapping layer is formed of one of aluminum 8-hydroxyquinoline (alq3), octadecyltrichlorosilane (OTS), or polystyrene (PS).

[0012] Furthermore, the organic semiconductor layer forming material is pentacene.

[0013] Furthermore, the source electrode and drain electrode are both made of metallic copper, and the gate insulating layer is 50nm silicon oxide.

[0014] The above technical solution achieves the goal of updating the weight of a unipolar voltage-controlled device by utilizing the ferroelectric polarization effect and the charge trapping effect. Specifically, by applying a negative gate voltage to the gate, the ferroelectric layer generates a ferroelectric polarization effect, which induces the accumulation of holes in the semiconductor and increases the number of holes. The charge trapping layer generates a built-in electric field by using the hole trapping effect to reduce the number of holes in the organic semiconductor layer. The synergistic effect of these two effects, combined with a specific control method, provides technical support for realizing the weight of a unipolar control device.

[0015] This invention also provides a method for fabricating a neuromorphic device that combines ferroelectric polarization and charge trapping effects, characterized by comprising the following steps:

[0016] (1) Prepare a polyvinylidene fluoride solution;

[0017] (2) Clean the single-polished silicon oxide wafer and then dry it;

[0018] (3) Spin-coat polyvinylidene fluoride solution onto the single-sided polished silicon oxide wafer processed in step (2), and then anneal the spin-coated sample.

[0019] (4) A charge trapping layer, an organic semiconductor layer, a source electrode, and a drain electrode are sequentially deposited on the sample treated in step (3) to obtain a neuromorphic device that combines ferroelectric polarization effect and charge trapping effect.

[0020] Furthermore, the oxide layer thickness of the single-polished silicon oxide wafer in step (2) is 50 nm, and its size is 2 cm × 2 cm.

[0021] Furthermore, the spin-coating of polyvinylidene fluoride solution in step (3) is performed at a speed of 2000 r / min and a spin-coating time of 2 min. The polyvinylidene fluoride solution needs to be pretreated by ultrasound and heating before spin-coating.

[0022] Furthermore, after the sample was spin-coated, it was annealed at 150°C for 15 minutes.

[0023] Furthermore, the deposition rate of the charge trapping layer in step (4) is... The film thickness was controlled to be 10 nm; the deposition rate of the organic semiconductor layer was [missing information]. The film thickness is controlled at 30 nm; the evaporation rate of the evaporation source and drain electrodes is... The electrode thickness is controlled to be 50nm.

[0024] To better illustrate the role of ferropolarization effect, this invention also fabricates a neuromorphic device with only ferropolarization effect. The step of fabricating the above-mentioned fabrication process without a charge trapping layer is the fabrication process of the neuromorphic device with only ferropolarization effect.

[0025] The present invention has the following beneficial results:

[0026] (1) By utilizing the synergistic effect of ferropolar polarization and charge trapping, and in conjunction with specific control methods, technical support can be provided for the weight update of unipolar pulse voltage control devices. The unipolar control process is more suitable for simulating the process of self-switching of biological synaptic excitation and inhibition states.

[0027] (2) Current neuromorphic devices, due to their simple charge mechanism, mostly employ bipolar voltages (positive and negative) to regulate the increase or decrease of conductance. Using bipolar control necessitates more complex circuitry design around the device, increasing design and manufacturing costs, as well as circuit integration. This hinders the development of multifunctional and miniaturized electronic devices. This invention, by adding a ferropolarization layer and a charge trapping layer, provides technical support for unipolar control of conductance. This unipolar control method significantly reduces circuit design complexity, and with more flexible control methods, more complex functionalities can be integrated. This is highly beneficial for the development of multifunctional and miniaturized electronic devices.

[0028] (3) The method for preparing a neuromorphic device with both ferroelectric polarization effect and charge trapping effect provided by the present invention is simple, easy to operate, low in cost and easy to promote. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a neuromorphic device that combines ferroelectric polarization and charge trapping effects.

[0030] Figure 2 This is a schematic diagram of a neuromorphic device that only exhibits ferroelectric polarization effects.

[0031] Figure 3 This is a graph showing the relationship between hysteresis, forward current, and ratio of a neuromorphic device that combines ferroelectric polarization and charge trapping effects with gate voltage.

[0032] Figure 4 This is a graph showing the relationship between hysteresis, forward current, and ratio of a neuromorphic device with only ferroelectric polarization effect and gate voltage.

[0033] Figure 5 This is a transfer characteristic curve of a neuromorphic device that only exhibits ferroelectric polarization effect. Detailed Implementation

[0034] The invention will be further described below with reference to specific examples and accompanying drawings.

[0035] Reference Figure 1 As shown, this invention provides a schematic diagram of a neuromorphic device that combines ferroelectric polarization and charge trapping effects. The device structure, from bottom to top, includes: a gate electrode; a gate insulating layer located above the gate electrode; a ferroelectric polarization layer formed on the gate insulating layer; a charge trapping layer formed on the ferroelectric polarization layer; an organic semiconductor layer formed on the charge trapping layer; a source electrode; and a drain electrode formed on the organic semiconductor layer, with a channel in between.

[0036] In this invention, a single-layer polished silicon oxide wafer with an oxide layer thickness of 50 nm is used as the gate electrode and the gate insulating layer; polyvinylidene fluoride is used as the material for forming the ferroelectric polarization layer, which can form a ferroelectric polarization effect and induce a change in the charge density of the organic semiconductor layer; aluminum 8-hydroxyquinoline is used as the material for forming the charge trapping layer, which changes the charge density of the organic semiconductor layer by trapping holes in the organic semiconductor layer; pentacene is used as the material for forming the organic semiconductor layer; and metallic copper is used as the material for forming the source and drain electrodes.

[0037] Except for the ferroelectric polarization layer, which is prepared by spin coating, all other layers of the device are prepared by vacuum evaporation.

[0038] The specific fabrication steps of the neuromorphic device with both ferroelectric polarization and charge trapping effects described in this embodiment are as follows:

[0039] Step (1): Prepare polyvinylidene fluoride solution. Take 0.5g of polyvinylidene fluoride and add it to 9.5g of N-methylpyrrolidone solvent. Stir with a magnetic stirrer for 1h to prepare a solution with a mass fraction of 95%. Then let it stand overnight at room temperature.

[0040] Step (2): Cut the single-sided polished silicon wafer with an oxide layer thickness of 50nm into a size of 2cm×2cm. Then, use decon solution and deionized water to sonicate for 30min respectively. After sonication, use anhydrous ethanol to rinse repeatedly to ensure that the surface is clean and free of stains. After rinsing, use high-purity nitrogen to dry the surface. Then, place it in a drying oven and dry at 80℃ for 1h.

[0041] Step (3): Perform ultrasonic and heating pretreatment operations on the polyvinylidene fluoride solution prepared in step (1). After the pretreatment is completed, drop it onto the silicon wafer treated in step (2). Then spin coat it at a rate of 2000 r / min for 2 min. After each spin coating, observe the film quality. If the film quality is not good, spin coat it again until a bright and uniform thin film layer is formed on the surface. After spin coating, place the silicon wafer at 150℃ for annealing for 15 min.

[0042] Step (4): Perform vacuum coating on the sample completed in step (3). Use an organic evaporation source to deposit a charge trapping layer. The deposition material is 8-hydroxyquinoline aluminum. Control the film thickness to 10 nm and the deposition rate to be as follows: Control the vacuum level at 5×10 -4 Below Pa; an organic semiconductor layer is deposited using a metal evaporation source, with the film thickness controlled at 30 nm and the deposition rate controlled at [value missing]. Control the vacuum level at 5×10 -4Below Pa; using a metal evaporation source to deposit the source and drain electrodes, with copper as the deposition material, controlling the film thickness to 50 nm, and controlling the deposition rate to [value missing]. Control the vacuum level at 5×10 -4 Neuromorphic devices with both ferroelectric polarization and charge trapping effects were fabricated at Pa below 1.

[0043] To better illustrate the role of the ferroelectric polarization effect, this embodiment of the invention also fabricates a neuromorphic device exhibiting only the ferroelectric polarization effect. The step of removing the vacuum-deposited charge trapping layer described above constitutes the fabrication process of the neuromorphic device exhibiting only the ferroelectric polarization effect. The device structure is as follows: Figure 2 As shown.

[0044] The electrical properties of the neuromorphic device exhibiting both ferroelectric polarization and charge trapping effects, and the neuromorphic device exhibiting only ferroelectric polarization, fabricated in this embodiment, were characterized using a Keithley 2636B semiconductor analyzer. The characterization results are as follows: Figure 3-5 As shown.

[0045] Figure 3 This reflects the relationship between hysteresis, pre-current, and ratio with gate voltage in neuromorphic devices that exhibit both ferroelectric polarization and charge trapping effects. Figure 3 It can be seen that when the gate voltage is -10V, -15V, and -20V, the hysteresis current is smaller than the hysteresis current, and the ratio of the hysteresis current to the hysteresis current is less than 1, indicating that the hole trapping effect of the device plays a dominant role, causing the hole density of the device to decrease.

[0046] Figure 4 This reflects the relationship between the prehysteresis current and its ratio and the gate voltage in neuromorphic devices exhibiting only ferroelectric polarization. Figure 4 It can be seen that when the gate voltage is -10V, -15V, and -20V, the hysteresis current is larger than the prehysteresis current, and the ratio of the hysteresis current to the prehysteresis current is greater than 1, indicating that the hole density is continuously increasing and the ferroelectric polarization effect of the device is playing a role.

[0047] Figure 5 This reflects the transfer characteristic curves of neuromorphic devices exhibiting only ferroelectric polarization effects. Figure 5 It can be seen that when the gate voltage sweeps from 0V to -30V, the current increases from 10V to 10V. -11 A increased to approximately 10 -7 A indicates that the device has good P-type transistor field-effect characteristics.

[0048] All test results show that by adding a ferropolarized layer and a charge trapping layer, the present invention can regulate the increase and decrease of hole density in the semiconductor layer of the device by utilizing their ferropolarized effect and hole trapping effect. Combined with a specific regulation method, it can provide technical support for realizing unipolar pulse voltage regulation of device conductance. This regulation method is more convenient than bipolar pulse voltage regulation, which can improve the flexibility of conductance regulation and reduce circuit integration, which is conducive to the development of multifunctional devices.

[0049] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A neuromorphic device with ferroelectric polarization effect and charge trapping effect, characterized in that, The device comprises a gate electrode, a gate insulating layer, a ferroelectric polarization layer, a charge trapping layer, an organic semiconductor layer, a source electrode and a drain electrode, wherein the gate insulating layer is located directly above the gate electrode, the ferroelectric polarization layer is located directly above the gate insulating layer, the charge trapping layer is located directly above the ferroelectric polarization layer, the organic semiconductor layer is located directly above the charge trapping layer, and the source electrode and the drain electrode are located directly above the organic semiconductor layer. The preparation method of the neuromorphic device with ferroelectric polarization effect and charge trapping effect comprises the following steps: (1) preparing a polyvinylidene fluoride solution; (2) cleaning and drying a single-polish silicon wafer; (3) spin-coating the polyvinylidene fluoride solution on the single-polish silicon wafer treated in step (2) and annealing the spin-coated sample; (4) sequentially depositing a charge trapping layer, an organic semiconductor layer, a source electrode and a drain electrode on the sample treated in step (3) to obtain the neuromorphic device with ferroelectric polarization effect and charge trapping effect. In step (3), the polyvinylidene fluoride solution is spin-coated at a speed of 2000 r / min for 2 min, and the polyvinylidene fluoride solution needs to be pretreated by ultrasonic and heating before spin-coating. After the sample is spin-coated, annealing is performed at a temperature of 150 DEG C for 15 min. The evaporation rate of the charge trapping layer in step (4) is The film thickness is controlled to be 10 nm; the evaporation rate of the organic semiconductor layer is The film thickness is controlled to be 30 nm; the evaporation rate of the source-drain electrode is The electrode thickness is controlled to be 50 nm.

2. The neuromorphic device with ferroelectric polarization and charge trapping effects of claim 1, wherein, The ferroelectric polarization layer is formed by polyvinylidene fluoride.

3. The neuromorphic device with ferroelectric polarization and charge trapping effects of claim 1, wherein, The charge trapping layer is formed by one of 8-hydroxyquinoline aluminum, octadecyltrichlorosilane and polystyrene.

4. The neuromorphic device with ferroelectric polarization and charge trapping effects of claim 1, wherein, The organic semiconductor layer is formed by pentacene.

5. The neuromorphic device with ferroelectric polarization and charge trapping effects of claim 1, wherein, The source electrode and the drain electrode are both formed by copper.

6. A method for preparing a neuromorphic device with ferroelectric polarization effect and charge trapping effect according to any one of claims 1-5, characterized in that, The preparation method comprises the following steps: (1) preparing a polyvinylidene fluoride solution; (2) cleaning and drying a single-polish silicon wafer; (3) spin-coating the polyvinylidene fluoride solution on the single-polish silicon wafer treated in step (2) and annealing the spin-coated sample; (4) sequentially depositing a charge trapping layer, an organic semiconductor layer, a source electrode and a drain electrode on the sample treated in step (3) to obtain the neuromorphic device with ferroelectric polarization effect and charge trapping effect.

7. The method of claim 6, wherein the method further comprises: In step (2), the thickness of the oxide layer of the single-polish silicon wafer is 50 nm, and the size is 2 cm x 2 cm.

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