Level shift circuit and chip

Abstract

The application discloses a level transfer circuit and a chip, and relates to the technical field of circuits, and in particular relates to a level transfer circuit and a chip. The level transfer circuit comprises a level input circuit, a level output circuit and a voltage stabilizing circuit, and the level input circuit, the level output circuit and the voltage stabilizing circuit are connected through a signal transmission line. If the level input circuit is connected to a low-side power supply domain, the level output circuit is connected to a high-side power supply domain, and the voltage stabilizing circuit is used for stabilizing the high-side power supply domain. If the level input circuit is connected to the high-side power supply domain, the level output circuit is connected to the low-side power supply domain, and the voltage stabilizing circuit is used for stabilizing the low-side power supply domain. According to the level transfer circuit, the voltage stabilizing circuit is used for inhibiting the signal transmission line from being higher than the power supply of the low-side power supply domain or lower than the ground of the high-side power supply domain, so that the voltage between the power supply rails is not affected by the signal transmission line, and the power supply rails are stabilized, thereby obviously improving the stability of the power supply rails without affecting the normal interaction between the level input circuit and the level output circuit located in the high-side and low-side power supply domains.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a level shifting circuit and chip. Background Technology

[0002] In multi-power-domain systems, signal transmission between power domains is inevitable. During this transmission, mutual interference can occur between the two power domains, potentially causing power rail fluctuations. In CMOS integrated circuits, power rail fluctuations introduce power noise. Larger fluctuations can lead to overvoltage and burnout of internal MOSFETs, or conduction of parasitic body diodes within the MOSFETs, which may cause latch-up effects and severely impact chip reliability. In high-voltage floating power domains, the power rails are even more susceptible to interference and fluctuations.

[0003] For example, such as Figure 1 As shown, during the interaction between high and low voltage power domains, the voltage of the signal transmission line can be pulled down below the voltage of the high-side floating ground. If the signal transmission line has a direct connection to the drain of an NMOS transistor, the parasitic body diode of the NMOS transistor will conduct, further pulling down the voltage of the high-side floating ground (HVSS), thus increasing the voltage difference between HVSS and the high-side floating power supply (HVCC). Therefore, it is necessary to charge the signal transmission line promptly when the parasitic body diode is detected to increase its voltage, thereby preventing it from affecting the HVSS voltage and maintaining the stability of the power rail.

[0004] Similarly, such as Figure 3 As shown, the voltage on the signal transmission line will be pulled up to a level higher than the low-side floating power supply LVCC. If this signal transmission line has a directly connected drain to a PMOS transistor, the parasitic body diode of the PMOS transistor will conduct, further pulling up the voltage of the low-side floating power supply LVCC. This increases the voltage between the low-side power rails. Therefore, it is necessary to discharge the signal transmission line promptly upon detecting parasitic body diode conduction to reduce the voltage on the signal transmission line, preventing any impact on the low-side floating power supply LVCC and maintaining power rail stability.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a level shifting circuit and chip that can maintain the stability of the power rail.

[0007] To achieve the above object, embodiments of the present application provide a level shift circuit, comprising: a level input circuit and a level output circuit, and a voltage stabilizing circuit.

[0008] The level input circuit accesses a low-side power supply domain, and the level output circuit accesses a high-side power supply domain, or the level input circuit accesses a high-side power supply domain, and the level output circuit accesses a low-side power supply domain, and the level input circuit and the level output circuit are connected through a signal transmission line. The voltage stabilizing circuit is connected to the corresponding power supply domain and the signal transmission line following the level output circuit. If the level input circuit accesses the low-side power supply domain, and the level output circuit accesses the high-side power supply domain, the voltage stabilizing circuit is connected to the level input circuit and the level output circuit through the signal transmission line, and the voltage stabilizing circuit adjusts the voltage on the signal transmission line to stabilize the voltage of the level output circuit. If the level input circuit accesses the low-side power supply domain, and the level output circuit accesses the high-side power supply domain, the voltage stabilizing circuit is used to raise the voltage on the signal transmission line when the voltage of the high-side floating ground in the high-side power supply domain is pulled down by the voltage on the signal transmission line. If the level input circuit accesses the high-side power supply domain, and the level output circuit accesses the low-side power supply domain, the voltage stabilizing circuit is used to lower the voltage on the signal transmission line when the voltage of the low-side floating ground in the low-side power supply domain is pulled up by the voltage on the signal transmission line.

[0009] In one or more embodiments of the present application, the voltage stabilizing circuit comprises:

[0010] a current generating circuit for generating a current; and

[0011] a current mirror circuit for applying the current to the signal transmission line, specifically, if the level input circuit accesses the low-side power supply domain, and the level output circuit accesses the high-side power supply domain, the current mirror circuit is used to send the current to the signal transmission line to charge and raise the voltage on the signal transmission line; if the level input circuit accesses the high-side power supply domain, and the level output circuit accesses the low-side power supply domain, the current mirror circuit is used to draw the current from the signal transmission line to discharge and lower the voltage on the signal transmission line.

[0012] In one or more embodiments of the present application, the current generating circuit comprises a first resistor;

[0013] If the level input circuit accesses the low-side power supply domain, and the level output circuit accesses the high-side power supply domain, a first end of the first resistor is connected to the high-side floating ground in the high-side power supply domain, and a second end of the first resistor is connected to the current mirror circuit.

[0014] If the level input circuit accesses the high-side power supply domain, and the level output circuit accesses the low-side power supply domain, a first end of the first resistor is connected to the low-side floating ground in the low-side power supply domain, and a second end of the first resistor is connected to the current mirror circuit.

[0015] In one or more embodiments of the present application, the current mirror circuit comprises a first MOS transistor, a second MOS transistor and a third MOS transistor;

[0016] If the level input circuit is connected to the low-side power domain and the level output circuit is connected to the high-side power domain, the gate and the drain of the first MOS transistor are shorted and connected to the current generating circuit, the source of the first MOS transistor is connected to the high-side floating ground of the high-side power domain, the gates of the second MOS transistor and the third MOS transistor are connected to each other and to the gate of the first MOS transistor, the drains of the second MOS transistor and the third MOS transistor are connected to the high-side floating power of the high-side power domain, and the sources of the second MOS transistor and the third MOS transistor are connected to the level input circuit and the level output circuit through a signal transmission line.

[0017] If the level input circuit is connected to the high-side power domain and the level output circuit is connected to the low-side power domain, the gate and the drain of the first MOS transistor are shorted and connected to the current generating circuit, the source of the first MOS transistor is connected to the low-side floating power of the low-side power domain, the gates of the second MOS transistor and the third MOS transistor are connected to each other and to the gate of the first MOS transistor, the drains of the second MOS transistor and the third MOS transistor are connected to the low-side floating ground of the low-side power domain, and the sources of the second MOS transistor and the third MOS transistor are connected to the level input circuit and the level output circuit through a signal transmission line.

[0018] In one or more embodiments of the present application, the current mirror circuit further comprises a first capacitor.

[0019] If the level input circuit is connected to the low-side power domain and the level output circuit is connected to the high-side power domain, the first end of the first capacitor is connected to the gate of the first MOS transistor, and the second end of the first capacitor is connected to the high-side floating ground of the high-side power domain.

[0020] If the level input circuit is connected to the high-side power domain and the level output circuit is connected to the low-side power domain, the first end of the first capacitor is connected to the gate of the first MOS transistor, and the second end of the first capacitor is connected to the low-side floating power of the low-side power domain.

[0021] In one or more embodiments of the present application, the voltage stabilizing circuit further comprises a transmission gate circuit connected to the current mirror circuit, for reducing the transient power consumption of the voltage stabilizing circuit.

[0022] In one or more embodiments of the present application, the transmission gate circuit comprises a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor.

[0023] If the level input circuit is connected to the low-side power supply domain and the level output circuit is connected to the high-side power supply domain, the source of the seventh MOS transistor is connected to the drain of the eighth MOS transistor and the gate of the first MOS transistor, the drain of the seventh MOS transistor is connected to the source of the eighth MOS transistor, the gate of the second MOS transistor and the drain of the sixth MOS transistor, and the source of the sixth MOS transistor is connected to the high-side floating ground of the high-side power supply domain.

[0024] If the level input circuit is connected to the high-side power supply domain and the level output circuit is connected to the low-side power supply domain, the drain of the seventh MOS transistor is connected to the source of the eighth MOS transistor and the gate of the first MOS transistor, the source of the seventh MOS transistor is connected to the drain of the eighth MOS transistor, the gate of the second MOS transistor and the drain of the sixth MOS transistor, and the source of the sixth MOS transistor is connected to the low-side floating power supply of the low-side power supply domain.

[0025] In one or more embodiments of the present application, the current generation circuit further comprises a thirteenth MOS transistor.

[0026] If the level input circuit is connected to the low-side power supply domain and the level output circuit is connected to the high-side power supply domain, the source of the thirteenth MOS transistor is connected to the high-side floating power supply of the high-side power supply domain, and the drain of the thirteenth MOS transistor is connected to the first end of the first resistor.

[0027] If the level input circuit is connected to the high-side power supply domain and the level output circuit is connected to the low-side power supply domain, the source of the thirteenth MOS transistor is connected to the low-side floating ground of the low-side power supply domain, and the drain of the thirteenth MOS transistor is connected to the first end of the first resistor.

[0028] In one or more embodiments of the present application, the current mirror circuit further comprises a fourth MOS transistor and a fifth MOS transistor.

[0029] If the level input circuit is connected to the low-side power supply domain and the level output circuit is connected to the high-side power supply domain, the gate and the drain of the fourth MOS transistor are connected and connected to the drain of the second MOS transistor, the gate and the drain of the fifth MOS transistor are connected and connected to the drain of the third MOS transistor, and the sources of the fourth MOS transistor and the fifth MOS transistor are connected to the high-side floating power supply of the high-side power supply domain.

[0030] If the level input circuit is connected to the high-side power supply domain and the level output circuit is connected to the low-side power supply domain, the gate and the drain of the fourth MOS transistor are connected and connected to the drain of the second MOS transistor, the gate and the drain of the fifth MOS transistor are connected and connected to the drain of the third MOS transistor, and the sources of the fourth MOS transistor and the fifth MOS transistor are connected to the low-side floating ground of the low-side power supply domain.

[0031] The present application also discloses a chip comprising the level transfer circuit.

[0032] Compared with the prior art, the level transfer circuit and the chip according to the embodiment of the application can raise the voltage on the signal transmission line through the voltage stabilizing circuit when the level input circuit accesses the low-side power supply domain and the level output circuit accesses the high-side power supply domain, thereby stabilizing the power supply rail, can lower the voltage on the signal transmission line through the voltage stabilizing circuit when the level input circuit accesses the high-side power supply domain and the level output circuit accesses the low-side power supply domain, thereby stabilizing the power supply rail, thereby protecting the independence of the power supply rail without affecting the normal interaction between the level input circuit and the level output circuit located in the high-side and low-side power supply domains, obviously improving the stability of the power supply rail, reducing the noise caused by the power supply, and improving the long-term reliability and service life of the device; the voltage stabilizing circuit can work in two modes of strong voltage stabilization and weak voltage stabilization through the transmission gate and the logic control, thereby adapting to more scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a circuit schematic diagram of the level transfer circuit according to the embodiment one of the application.

[0034] Figure 2 is a pulse signal waveform diagram of the level transfer circuit according to the embodiment one of the application.

[0035] Figure 3 is a circuit schematic diagram of the level transfer circuit according to the embodiment two of the application.

[0036] Figure 4 is a pulse signal waveform diagram of the level transfer circuit according to the embodiment two of the application. DETAILED DESCRIPTION

[0037] The specific embodiments of the application are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the application is not limited by the specific embodiments.

[0038] Unless otherwise clearly indicated, in the entire specification and claims, the term “comprise” or its variants such as “contain” or “include” and the like are understood to include the stated element or component, but not to exclude the presence of other elements or components.

[0039] Embodiment 1

[0040] As shown in Figure 1 , a level transfer circuit comprises a level input circuit 10, a level output circuit 20, and a voltage stabilizing circuit 30.

[0041] As shown in Figure 1As shown, the level input circuit 10 is connected to the low-side power domain, the level output circuit 20 is connected to the high-side power domain, and the voltage stabilizing circuit 30 is connected to the high-side power domain. The level input circuit 10 and the level output circuit 20 are connected through a signal transmission line, and the voltage stabilizing circuit 30 is connected to the level input circuit 10 and the level output circuit 20 through a signal transmission line, so as to stabilize the voltage of the level output circuit 20 by adjusting the voltage on the signal transmission line. The level input circuit 10, the level output circuit 20, and the voltage stabilizing circuit 30 are connected through two signal transmission lines, which are a first signal transmission line On_pulldown and a second signal transmission line Off_pulldown. In the embodiment, the high-side power domain is a high-voltage floating power domain. In other embodiments, the high-side power domain is other high-voltage power domains.

[0042] The level input circuit 10 includes a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, and a seventeenth MOS transistor M17. The fourteenth MOS transistor M14 and the fifteenth MOS transistor M15 are high-voltage resistant thick gate MOS transistors, which are used to protect the sixteenth MOS transistor M16 and the seventeenth MOS transistor M17. The sixteenth MOS transistor M16 and the seventeenth MOS transistor M17 are MOS transistors controlled by signals of the low-side power domain.

[0043] Specifically, the source of the fourteenth MOS transistor M14 is connected to the drain of the sixteenth MOS transistor M16, the drain of the fourteenth MOS transistor M14 is connected to the level output circuit 20 and the voltage stabilizing circuit 30 through the first signal transmission line On_pulldown, and the gate of the fourteenth MOS transistor M14 is connected to a control voltage LVCC. The source of the sixteenth MOS transistor M16 is connected to a low-side ground LVSS of the low-side power domain, and the gate of the sixteenth MOS transistor M16 is connected to a first input signal on_pulse.

[0044] The source of the fifteenth MOS transistor M15 is connected to the drain of the seventeenth MOS transistor M17, the drain of the fifteenth MOS transistor M15 is connected to the level output circuit 20 and the voltage stabilizing circuit 30 through the second signal transmission line Off_pulldown, and the gate of the fifteenth MOS transistor M15 is connected to the control voltage LVCC. The source of the seventeenth MOS transistor M17 is connected to the low-side ground LVSS of the low-side power domain, and the gate of the seventeenth MOS transistor M17 is connected to a second input signal off_pulse.

[0045] In other embodiments, the sixteenth MOS transistor M16 and the seventeenth MOS transistor M17 can be removed, and the fourteenth MOS transistor M14 and the fifteenth MOS transistor M15 are directly controlled by the first input signal on_pulse and the second input signal off_pulse.

[0046] As Figure 1As shown, the level output circuit 20 comprises a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11 and a twelfth MOS transistor M12.

[0047] The gate of the ninth MOS transistor M9 and the gate of the tenth MOS transistor M10 are connected and connected to the second signal transmission line Off_pulldown, the gate of the eleventh MOS transistor M11 and the gate of the twelfth MOS transistor M12 are connected and connected to the first signal transmission line On_pulldown. The drain of the ninth MOS transistor M9 and the drain of the tenth MOS transistor M10 are connected and connected to the gate of the eleventh MOS transistor M11 and output the second output signal off_hv, the drain of the eleventh MOS transistor M11 and the drain of the twelfth MOS transistor M12 are connected and connected to the gate of the ninth MOS transistor M9 and output the first output signal on_hv. The source of the ninth MOS transistor M9 and the source of the eleventh MOS transistor M11 are connected and connected to the high-side floating power supply HVCC of the high-side power supply domain, and the source of the tenth MOS transistor M10 and the source of the twelfth MOS transistor M12 are connected to the high-side floating ground HVSS of the high-side power supply domain.

[0048] In other embodiments, the level input circuit 10 and the level output circuit 20 can also be other circuit structures.

[0049] As shown, Figure 1 The voltage stabilizing circuit 30 is used to raise the voltage on the signal transmission line when the voltage of the high-side floating ground HVSS of the high-side power supply domain is pulled down by the voltage on the signal transmission line. The voltage stabilizing circuit 30 comprises a current generating circuit 31 and a current mirror circuit 32.

[0050] The current generating circuit 31 is used to generate a current. The current generating circuit 31 comprises a first resistor R1 and a thirteenth MOS transistor M13.

[0051] The first end of the first resistor R1 is connected to the drain of the thirteenth MOS transistor M13, the source of the thirteenth MOS transistor M13 is connected to the high-side floating power supply HVCC of the high-side power supply domain, the gate of the thirteenth MOS transistor M13 is connected to the enable signal EN, when the voltage stabilizing circuit 30 is not used, the disconnection of the thirteenth MOS transistor M13 is controlled by the enable signal EN, thereby controlling the disconnection of the entire voltage stabilizing circuit 30 to reduce power consumption, and the second end of the first resistor R1 is connected to the current mirror circuit 32. In other embodiments, a constant current source can be used instead of the first resistor R1. In other embodiments, the thirteenth MOS transistor M13 can also be removed.

[0052] The current mirror circuit 32 is used to send the current into the signal transmission line to charge and raise the voltage on the signal transmission line. The current mirror circuit 32 comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a first capacitor C1.

[0053] Specifically, the gate and the drain of the first MOS transistor M1 are shorted and the second end of the first resistor R1 is connected, the source of the first MOS transistor M1 is connected to the high-side floating ground HVSS of the high-side power domain. The first end of the first capacitor C1 is connected to the gate of the first MOS transistor M1, and the second end of the first capacitor C1 is connected to the high-side floating ground HVSS of the high-side power domain. The gates of the second MOS transistor M2 and the third MOS transistor M3 are connected and connected to the gate of the first MOS transistor M1, the drains of the second MOS transistor M2 and the third MOS transistor M3 are connected to the high-side floating power HVCC of the high-side power domain, the source of the second MOS transistor M2 is connected to the drain of the fourteenth MOS transistor M14 and the gate of the eleventh MOS transistor M11 through the first signal transmission line On_pulldown, and the source of the third MOS transistor M3 is connected to the drain of the fifteenth MOS transistor M15 and the gate of the ninth MOS transistor M9 through the second signal transmission line Off_pulldown. The first capacitor C1 can be a MOS capacitor.

[0054] In the embodiment, the current mirror circuit 32 can further include a voltage division unit, the voltage division unit includes N pairs of MOS transistors, N is an integer greater than or equal to 1, and the voltage division unit is used to share the voltage difference between the source and the drain of the second MOS transistor M2 and the third MOS transistor M3, reduce the hot carrier effect of M2 and M3, and select a suitable N value according to the actual required voltage difference sharing size. Figure 1 It is disclosed that the voltage division unit includes a fourth MOS transistor M4 and a fifth MOS transistor M5. The gate and the drain of the fourth MOS transistor M4 are connected and connected to the drain of the second MOS transistor M2, the gate and the drain of the fifth MOS transistor M5 are connected and connected to the drain of the third MOS transistor M3, and the sources of the fourth MOS transistor M4 and the fifth MOS transistor M5 are connected to the high-side floating power HVCC of the high-side power domain.

[0055] In other embodiments, if the influence of hot carrier leakage can be ignored in actual application, the fourth MOS transistor M4 and the fifth MOS transistor M5 can be removed.

[0056] As Figure 1 As shown in the figure, the voltage stabilizing circuit 30 further includes a transmission gate circuit 33 connected with the current mirror circuit 32, and the transmission gate circuit 33 is used to reduce the transient power consumption of the voltage stabilizing circuit 30. The transmission gate circuit 33 includes a sixth MOS transistor M6, a seventh MOS transistor M7 and an eighth MOS transistor M8.

[0057] The source of the seventh MOS M7 is connected with the drain of the eighth MOS M8 and the gate of the first MOS M1, the drain of the seventh MOS M7 is connected with the source of the eighth MOS M8 and the gate of the second MOS M2 and the drain of the sixth MOS M6, and the source of the sixth MOS M6 is connected with the high side floating ground HVSS of the high side power domain. The gate of the seventh MOS M7 and the gate of the sixth MOS M6 are both connected with the first control signal Pulse_N, and the gate of the eighth MOS M8 is connected with the second control signal Pulse_P.

[0058] As shown in Figure 2 The first control signal Pulse_N, the second control signal Pulse_P, the first input signal on_pulse, the second input signal off_pulse, the first output signal on_hv and the second output signal off_hv are all corresponding pulse signals.

[0059] The embodiment also discloses a chip comprising the level shift circuit.

[0060] Next, the working principle of the embodiment will be described in detail in combination with Figure 1 and Figure 2

[0061] Taking the second signal transmission line Off_pulldown as an example. When the second input signal off_pulse is high, the voltage on the second signal transmission line Off_pulldown will be pulled down by the low side power domain without the voltage stabilizing circuit 30. If the voltage is pulled down for a certain period of time, the voltage on the second signal transmission line Off_pulldown will be lower than the voltage of the high side floating ground HVSS of the high side power domain. When the voltage on the second signal transmission line Off_pulldown is lower than the voltage of the high side floating ground HVSS by more than 0.7V, the parasitic diode D1 of the twelfth MOS M12 will be turned on. If the voltage on the second signal transmission line Off_pulldown is further reduced by continuing to pull down, the parasitic diode D1 can only be clamped, so the voltage of the high side floating ground HVSS will also be pulled down, and at this time, the gate-source voltage of the ninth MOS M9 will increase, which will affect the reliability of the MOS.

[0062] ​After the voltage stabilizing circuit 30 is added, the second control signal Pulse_P will be high during signal interaction, and the current mirror composed of the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 will make the voltage on the second signal transmission line Off_pulldown be pulled to be approximately equal to the voltage of the high-side floating ground HVSS, and the current generating circuit 31 will generate a current to flow to the second signal transmission line Off_pulldown through the third MOS transistor M3, so as to ensure that the voltage on the second signal transmission line Off_pulldown is not further lowered, thereby maintaining the voltage of the high-side floating ground HVSS stable.

[0063] Since the voltage stabilizing circuit 30 needs a large transient power consumption, a transmission gate circuit 33 is specially added to control the power consumption. In a scenario where the power consumption is not cared, the transmission gate circuit 33 can also be removed. The first capacitor C1 is used to protect the gate of the first MOS transistor M1 on one hand, and to provide part of the charging charge for the gates of the second MOS transistor M2 and the third MOS transistor M3 on the other hand.

[0064] During the period when the seventh MOS transistor M7 and the eighth MOS transistor M8 are closed, that is, the first control signal Pulse_N is high and the second control signal Pulse_P is low, the sixth MOS transistor M6 is turned on at this time, and the gates of the second MOS transistor M2 and the third MOS transistor M3 are connected to the high-side floating ground HVSS. If the voltage on the second signal transmission line Off_pulldown is pulled down to be lower than the voltage of the high-side floating ground HVSS, the second MOS transistor M2 and the third MOS transistor M3 will also be automatically turned on, but at this time, the parasitic diodes of the second MOS transistor M2 and the third MOS transistor M3 can also be turned on, thereby causing the voltage of the high-side floating ground HVSS to be possibly affected to a certain extent, and therefore this scenario can only cope with the case that the voltage on the second signal transmission line Off_pulldown is temporarily pulled down or the pull-down current is small.

[0065] Figure 1 The two parasitic diodes D1 in the figure are the equivalent parasitic diodes of the twelfth MOS transistor M12, and other similar equivalent parasitic diodes are not drawn in the figure. The voltage on the first signal transmission line On_pulldown will have the same change as the voltage on the second signal transmission line Off_pulldown in operation.

[0066] Embodiment 2

[0067] As shown in Figure 3 , a level shift circuit includes a level input circuit 40, a level output circuit 50, and a voltage stabilizing circuit 60.

[0068] like Figure 3 As shown, the level input circuit 40 is connected to the high-side power domain, the level output circuit 50 is connected to the low-side power domain, and the voltage regulator circuit 60 is connected to the low-side power domain. The level input circuit 40 and the level output circuit 50 are connected via signal transmission lines. The voltage regulator circuit 60 is connected to the level input circuit 40 and the level output circuit 50 via signal transmission lines, and voltage regulation of the level output circuit 50 is achieved by adjusting the voltage on the signal transmission lines. The level input circuit 40, the level output circuit 50, and the voltage regulator circuit 60 are connected via two signal transmission lines: the first signal transmission line On_pullup and the second signal transmission line Off_pullup. In this embodiment, the low-side power domain is a low-voltage floating power domain. In other embodiments, the low-side power domain is another low-voltage power domain.

[0069] The level input circuit 40 includes a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, and a seventeenth MOSFET M17. MOSFETs M14 and M15 are high-voltage, thick-gate MOSFETs used to protect MOSFETs M16 and M17. MOSFETs M16 and M17 are MOSFETs controlled by high-side power domain signals.

[0070] Specifically, the source of the fourteenth MOSFET M14 is connected to the drain of the sixteenth MOSFET M16. The drain of the fourteenth MOSFET M14 is connected to the level output circuit 50 and the voltage regulator circuit 60 through the first signal transmission line On_pullup. The gate of the fourteenth MOSFET M14 is connected to the control voltage HVSS. The source of the sixteenth MOSFET M16 is connected to the high-side power supply HVCC of the high-side power supply domain. The gate of the sixteenth MOSFET M16 is connected to the first input signal on_pulse.

[0071] The source of the fifteenth MOSFET M15 is connected to the drain of the seventeenth MOSFET M17. The drain of the fifteenth MOSFET M15 is connected to the level output circuit 50 and the voltage regulator circuit 60 through the second signal transmission line Off_pullup. The gate of the fifteenth MOSFET M15 is connected to the control voltage HVSS. The source of the seventeenth MOSFET M17 is connected to the high-side power supply HVCC of the high-side power supply domain. The gate of the seventeenth MOSFET M17 is connected to the second input signal off_pulse.

[0072] In other embodiments, the sixteenth MOSFET M16 and the seventeenth MOSFET M17 can be removed, and the fourteenth MOSFET M14 and the fifteenth MOSFET M15 can be controlled directly through the first input signal on_pulse and the second input signal off_pulse.

[0073] like Figure 3As shown, the level output circuit 50 includes a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11 and a twelfth MOS transistor M12.

[0074] The gate of the ninth MOS transistor M9 and the gate of the tenth MOS transistor M10 are connected and connected to the second signal transmission line Off_pullup, and the gate of the eleventh MOS transistor M11 and the gate of the twelfth MOS transistor M12 are connected and connected to the first signal transmission line On_pullup. The drain of the ninth MOS transistor M9 and the drain of the tenth MOS transistor M10 are connected and connected to the gate of the eleventh MOS transistor M11 and output a second output signal off_lv, and the drain of the eleventh MOS transistor M11 and the drain of the twelfth MOS transistor M12 are connected and connected to the gate of the ninth MOS transistor M9 and output a first output signal on_lv. The source of the ninth MOS transistor M9 and the source of the eleventh MOS transistor M11 are connected and connected to the low-side floating ground LVSS of the low-side power domain, and the source of the tenth MOS transistor M10 and the source of the twelfth MOS transistor M12 are connected to the low-side floating power LVCC of the low-side power domain.

[0075] In other embodiments, the level input circuit 40 and the level output circuit 50 can also be other circuit structures.

[0076] As shown, the voltage stabilizing circuit 60 is used to reduce the voltage on the signal transmission line when the voltage of the low-side power LVCC of the low-side power domain is pulled up by the voltage on the signal transmission line. The voltage stabilizing circuit 60 includes a current generating circuit 61 and a current mirror circuit 62. Figure 3

[0077] The current generating circuit 61 is used to generate a current. The current generating circuit 61 includes a first resistor R1 and a thirteenth MOS transistor M13.

[0078] The first end of the first resistor R1 is connected to the drain of the thirteenth MOS transistor M13, the source of the thirteenth MOS transistor M13 is connected to the low-side floating ground LVSS of the low-side power domain, the gate of the thirteenth MOS transistor M13 is connected to the enable signal EN, and when the voltage stabilizing circuit 30 is not used, the disconnection of the thirteenth MOS transistor M13 is controlled by the enable signal EN to control the disconnection of the entire voltage stabilizing circuit 30 to reduce power consumption, and the second end of the first resistor R1 is connected to the current mirror circuit 62. In other embodiments, a constant current source can be used instead of the first resistor R1. In other embodiments, the thirteenth MOS transistor M13 can also be removed.

[0079] The current mirror circuit 62 is used to draw the current from the signal transmission line, discharge, and reduce the voltage on the signal transmission line. The current mirror circuit 62 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a first capacitor C1.

[0080] ​Specifically, the gate and the drain of the first MOS transistor M1 are shorted and the second end of the first resistor R1 is connected, the source of the first MOS transistor M1 is connected to the low-side floating power supply LVCC of the low-side power supply domain. The first end of the first capacitor C1 is connected to the gate of the first MOS transistor M1, and the second end of the first capacitor C1 is connected to the low-side floating power supply LVCC of the low-side power supply domain. The gates of the second MOS transistor M2 and the third MOS transistor M3 are connected and connected to the gate of the first MOS transistor M1, the drains of the second MOS transistor M2 and the third MOS transistor M3 are connected to the low-side floating ground LVSS of the low-side power supply domain, the source of the second MOS transistor M2 is connected to the drain of the fourteenth MOS transistor M14 and the gate of the eleventh MOS transistor M11 through the first signal transmission line On_pullup, and the source of the third MOS transistor M3 is connected to the drain of the fifteenth MOS transistor M15 and the gate of the ninth MOS transistor M9 through the second signal transmission line Off_pullup. The first capacitor C1 can be a MOS capacitor.

[0081] In the embodiment, the current mirror circuit 62 can further include a voltage division unit, the voltage division unit includes N pairs of MOS transistors, N is an integer greater than or equal to 1, and the voltage division unit is used to share the voltage difference between the source and the drain of the second MOS transistor M2 and the third MOS transistor M3, reduce the hot carrier effect of the second MOS transistor M2 and the third MOS transistor M3, and select a suitable N value according to the actual required voltage difference sharing size. Figure 3 It is disclosed that the voltage division unit includes a fourth MOS transistor M4 and a fifth MOS transistor M5. The gate and the drain of the fourth MOS transistor M4 are connected and connected to the drain of the second MOS transistor M2, the gate and the drain of the fifth MOS transistor M5 are connected and connected to the drain of the third MOS transistor M3, and the sources of the fourth MOS transistor M4 and the fifth MOS transistor M5 are connected to the low-side ground LVSS of the low-side power supply domain.

[0082] In other embodiments, if the influence of hot carrier leakage can be ignored in actual application, the fourth MOS transistor M4 and the fifth MOS transistor M5 can be removed.

[0083] As Figure 3 As shown, the voltage stabilizing circuit 60 further includes a transmission gate circuit 63 connected with the current mirror circuit 62, and the transmission gate circuit 63 is used to reduce the transient power consumption of the voltage stabilizing circuit 60. The transmission gate circuit 33 includes a sixth MOS transistor M6, a seventh MOS transistor M7 and an eighth MOS transistor M8.

[0084] The drain of the seventh MOS M7 is connected with the source of the eighth MOS M8 and the gate of the first MOS M1, the source of the seventh MOS M7 is connected with the drain of the eighth MOS M8 and the gate of the second MOS M2 and the drain of the sixth MOS M6, the source of the sixth MOS M6 is connected with the low side floating power LVCC of the low side power domain. The gate of the seventh MOS M7 and the gate of the sixth MOS M6 are both connected with the second control signal Pulse_P, and the gate of the eighth MOS M8 is connected with the first control signal Pulse_N.

[0085] As shown in Figure 4 , the first control signal Pulse_N, the second control signal Pulse_P, the first input signal on_pulse, the second input signal off_pulse, the first output signal on_lv and the second output signal off_lv are all corresponding pulse signals.

[0086] In the embodiment, a chip is also disclosed, which comprises the level shift circuit.

[0087] Next, the working principle of the embodiment will be described in detail in combination with Figure 3 and Figure 4 .

[0088] Taking the second signal transmission line Off_pullup as an example. When the second input signal off_pulse is low and the voltage on the second signal transmission line Off_pullup is pulled up by the high side power domain, if the voltage on the second signal transmission line Off_pullup is higher than the voltage of the low side floating power LVCC of the low side power domain for a certain time, the parasitic diode D1 of the twelfth MOS M12 will be turned on, and if the voltage on the second signal transmission line Off_pullup is further increased, the parasitic diode D1 can only be clamped, so the voltage of the low side floating power LVCC of the low side power domain will also be pulled up, and at this time, the gate-source voltage of the ninth MOS M9 will increase, which will affect the reliability of the MOS.

[0089] After the voltage stabilizing circuit 60 is added, the second control signal Pulse_P will be high when the signals are interacting, and through the current mirror composed of the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3, when the voltage on the second signal transmission line Off_pullup is pulled to be approximately equal to the voltage of the low-side floating power supply LVCC, the third MOS transistor M3 will draw current from the second signal transmission line Off_pullup through the current generating circuit 31 that generates current, so as to ensure that the voltage on the second signal transmission line Off_pullup is no longer pulled up further, thereby maintaining the voltage of the low-side floating power supply LVCC stable.

[0090] Since the voltage stabilizing circuit 60 requires a large transient power consumption, a transmission gate circuit 63 is specially added to control the power consumption. In a scenario where the power consumption is not a concern, the transmission gate circuit 63 can also be removed. The first capacitor C1 is used to protect the gate of the first MOS transistor M1 on the one hand, and to provide part of the charging charge for the gates of the second MOS transistor M2 and the third MOS transistor M3 at the moment when the seventh MOS transistor M7 and the eighth MOS transistor M8 are turned on.

[0091] During the period when the seventh MOS transistor M7 and the eighth MOS transistor M8 are turned off, i.e., the first control signal Pulse_N is high and the second control signal Pulse_P is low, at this time the sixth MOS transistor M6 is turned on, and the gates of the second MOS transistor M2 and the third MOS transistor M3 are connected to the low-side floating power supply LVCC. If the voltage on the second signal transmission line Off_pullup is pulled up to be higher than the voltage of the low-side floating power supply LVCC, the second MOS transistor M2 and the third MOS transistor M3 will also be automatically turned on, but at this time the parasitic diodes of the second MOS transistor M2 and the third MOS transistor M3 may also be turned on, thereby causing the voltage of the low-side floating power supply LVCC to also be affected to a certain extent, so this scenario can only cope with the case where the voltage on the second signal transmission line Off_pullup is pulled up for a short time or the pull-up current is small.

[0092] Figure 3 The two parasitic diodes D1 in are the equivalent parasitic diodes of the twelfth MOS transistor M12, and other similar equivalent parasitic diodes are not drawn in the figure. The voltage on the first signal transmission line On_pullup will have the same change as the voltage on the second signal transmission line Off_pullup in operation.

[0093] The foregoing description of specific exemplary embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. It is intended that the scope of the application be limited not with this detailed description, but rather by the claims appended hereto.

Claims

1. A level shift circuit, comprising: a level input circuit and a level output circuit; the level input circuit is connected to a low-side power domain and the level output circuit is connected to a high-side power domain, or the level input circuit is connected to a high-side power domain and the level output circuit is connected to a low-side power domain, and the level input circuit and the level output circuit are connected through a signal transmission line; characterized in that the level shift circuit further comprises: a voltage stabilizing circuit connected to the level input circuit and the level output circuit through the signal transmission line, and configured to stabilize the voltage of the level output circuit by adjusting the voltage on the signal transmission line; if the level input circuit is connected to the low-side power domain and the level output circuit is connected to the high-side power domain, the voltage stabilizing circuit is configured to raise the voltage on the signal transmission line when the voltage of a high-side floating ground in the high-side power domain is pulled down by the voltage on the signal transmission line; if the level input circuit is connected to the high-side power domain and the level output circuit is connected to the low-side power domain, the voltage stabilizing circuit is configured to lower the voltage on the signal transmission line when the voltage of a low-side floating ground in the low-side power domain is pulled up by the voltage on the signal transmission line; the voltage stabilizing circuit comprises: a current generating circuit configured to generate a current; and a current mirror circuit configured to apply the current to the signal transmission line, specifically, if the level input circuit is connected to the low-side power domain and the level output circuit is connected to the high-side power domain, the current mirror circuit is configured to send the current to the signal transmission line to charge and raise the voltage on the signal transmission line; if the level input circuit is connected to the high-side power domain and the level output circuit is connected to the low-side power domain, the current mirror circuit is configured to draw the current from the signal transmission line to discharge and lower the voltage on the signal transmission line.

2. The level shifting circuit of claim 1, wherein, the current generating circuit comprises a first resistor; if the level input circuit is connected to the low-side power domain and the level output circuit is connected to the high-side power domain, a first end of the first resistor is connected to a high-side floating ground in the high-side power domain, and a second end of the first resistor is connected to the current mirror circuit; if the level input circuit is connected to the high-side power domain and the level output circuit is connected to the low-side power domain, a first end of the first resistor is connected to a low-side floating ground in the low-side power domain, and a second end of the first resistor is connected to the current mirror circuit.

3. The level shifting circuit of claim 1, wherein, the current mirror circuit comprises a first MOS transistor, a second MOS transistor and a third MOS transistor; if the level input circuit is connected to the low-side power domain and the level output circuit is connected to the high-side power domain, a gate and a drain of the first MOS transistor are shorted and connected to the current generating circuit, a source of the first MOS transistor is connected to the high-side floating ground in the high-side power domain, gates of the second MOS transistor and the third MOS transistor are connected to each other and connected to the gate of the first MOS transistor, drains of the second MOS transistor and the third MOS transistor are connected to a high-side floating power in the high-side power domain, and sources of the second MOS transistor and the third MOS transistor are connected to the level input circuit and the level output circuit through the signal transmission line. If the level input circuit is connected to the high-side power domain and the level output circuit is connected to the low-side power domain, the gate and the drain of the first MOS are connected and connected to the current generating circuit, the source of the first MOS is connected to the low-side floating power supply of the low-side power domain, the gates of the second MOS and the third MOS are connected and connected to the gate of the first MOS, the drains of the second MOS and the third MOS are connected to the low-side floating ground of the low-side power domain, and the sources of the second MOS and the third MOS are connected to the level input circuit and the level output circuit through the signal transmission line.

4. The level shifting circuit of claim 3, wherein, The current mirror circuit further comprises a first capacitor; If the level input circuit is connected to the low-side power domain and the level output circuit is connected to the high-side power domain, the first end of the first capacitor is connected to the gate of the first MOS, and the second end of the first capacitor is connected to the high-side floating ground of the high-side power domain. If the level input circuit is connected to the high-side power domain and the level output circuit is connected to the low-side power domain, the first end of the first capacitor is connected to the gate of the first MOS, and the second end of the first capacitor is connected to the low-side floating power supply of the low-side power domain.

5. The level shifting circuit of claim 3, wherein, The voltage stabilizing circuit further comprises a transmission gate circuit connected with the current mirror circuit, for reducing the transient power consumption of the voltage stabilizing circuit.

6. The level shifting circuit of claim 5, wherein, The transmission gate circuit comprises a sixth MOS, a seventh MOS and an eighth MOS; If the level input circuit is connected to the low-side power domain and the level output circuit is connected to the high-side power domain, the source of the seventh MOS is connected to the drain of the eighth MOS and the gate of the first MOS, the drain of the seventh MOS is connected to the source of the eighth MOS, the gate of the second MOS and the drain of the sixth MOS, and the source of the sixth MOS is connected to the high-side floating ground of the high-side power domain. If the level input circuit is connected to the high-side power domain and the level output circuit is connected to the low-side power domain, the drain of the seventh MOS is connected to the source of the eighth MOS and the gate of the first MOS, the source of the seventh MOS is connected to the drain of the eighth MOS, the gate of the second MOS and the drain of the sixth MOS, and the source of the sixth MOS is connected to the low-side floating power supply of the low-side power domain.

7. The level shifting circuit of claim 2, wherein, The current generating circuit further comprises a thirteenth MOS; If the level input circuit is connected to the low-side power domain and the level output circuit is connected to the high-side power domain, the source of the thirteenth MOS is connected to the high-side floating power supply of the high-side power domain, and the drain of the thirteenth MOS is connected to the first end of the first resistor. If the level input circuit is connected to the high-side power domain and the level output circuit is connected to the low-side power domain, the source of the thirteenth MOS is connected to the low-side floating ground of the low-side power domain, and the drain of the thirteenth MOS is connected to the first end of the first resistor.

8. The level shifting circuit of claim 3, wherein, The current mirror circuit further comprises a fourth MOS and a fifth MOS; If the level input circuit is connected to the low-side power domain and the level output circuit is connected to the high-side power domain, the gate and the drain of the fourth MOS are connected and connected to the drain of the second MOS, the gate and the drain of the fifth MOS are connected and connected to the drain of the third MOS, the source of the fourth MOS and the fifth MOS are connected to the high-side floating power of the high-side power domain; If the level input circuit is connected to the high-side power domain and the level output circuit is connected to the low-side power domain, the gate and the drain of the fourth MOS are connected and connected to the drain of the second MOS, the gate and the drain of the fifth MOS are connected and connected to the drain of the third MOS, the source of the fourth MOS and the fifth MOS are connected to the low-side floating ground of the low-side power domain.

9. A chip comprising the level shift circuit according to any one of claims 1-8.

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