Method for partitioning a netlist, method for simulating a circuit

Abstract

The application discloses a kind of network table partitioning method, circuit simulation method.Therein network table partitioning method includes: obtaining all the minimum logic unit (i.e.node) in network table and their connection relationship;Based on hardware information file, obtain all verification equipment, the capacity of verification equipment and the interconnection between each verification equipment;The relationship between each node and each verification equipment is used as a variable, and all variables are conditionally constrained;Based on the connection relationship of minimum logic unit and the relationship between each node and each verification equipment, the relationship between each connection and each verification equipment is obtained;According to the relationship between each connection and each verification equipment and the interconnection between verification equipment, build target partition function;Based on the condition constraint of all variables, the target partition function is solved by solver;When solver has solution, the output of obtained solver is the partitioning result of network table.The application is better in compatibility and higher in efficiency.

Description

Netlist partitioning methods and circuit simulation methods Technical Field

[0001] This invention relates to the technical field of circuit simulation, and in particular to a netlist partitioning method based on integer linear programming. Background Technology

[0002] System simulation verification of large-scale integrated circuits based on pure software is extremely inefficient, significantly increasing chip development cycles, which is unacceptable, especially for large-scale integrated circuit chips using advanced processes below 14 nanometers. Therefore, the industry advocates using hardware simulation acceleration technology based on multi-FPGA systems to speed up chip system simulation verification.

[0003] In a hardware simulation accelerator for a multi-FPGA system, the effect of dividing the chip design into multiple FPGAs directly affects the operating frequency of the chip design in the hardware simulation accelerator, thus affecting the efficiency of chip simulation.

[0004] Commonly used partitioning methods are mostly for partitioning gate-level netlists or RTL-level netlists after conversion to a supergraph. They cannot form a universal partitioning method for multi-level netlists. Therefore, how to quickly, efficiently and effectively partition the design netlist into multiple FPGAs has become an urgent problem to be solved. Summary of the Invention

[0005] To address the technical problem that existing netlist segmentation methods are incompatible with gate-level or RTL-level netlists, this invention proposes a netlist segmentation method and a circuit simulation method.

[0006] The netlist segmentation method proposed in this invention includes:

[0007] Obtain all the smallest logical units in the netlist and the connections between them, and treat each smallest logical unit as a node;

[0008] Based on the hardware information file, we obtain all verification devices, the capacity of each verification device, and the interconnection relationships between each verification device.

[0009] The relationship between each node and each verification device is used as a variable, and conditions are constrained on all variables according to the limitations of the verification device;

[0010] The relationship between each connection and each verification device is obtained based on the connection relationship of the smallest logical unit and the relationship between each node and each verification device.

[0011] Construct the target segmentation function based on the relationship between each connection and each verification device, as well as the interconnection relationship between the verification devices;

[0012] The objective segmentation function is solved by a solver based on the conditional constraints of all variables.

[0013] When the solver has a solution, the output of the solver is the netlist partitioning result.

[0014] Furthermore, the connection relationship of the smallest logical unit is represented by a connection node relationship matrix, where each row or column of the connection node relationship matrix represents a branchless connection formed by the sequential connection of nodes.

[0015] Furthermore, the interconnection relationship between the various verification devices is represented by a device interconnection matrix, where each element of the device interconnection matrix represents the number of interconnection signal lines between the verification device in the row and the verification device in the column.

[0016] Furthermore, the relationship between each node and each verification device is represented by a node-device relationship matrix, where each element of the node-device relationship matrix is ​​a variable, and the value of the variable is 0 or 1.

[0017] Furthermore, the condition constraints include: the sum of all variables in each row or column corresponding to each node is 1; the sum of all variables in each column or row corresponding to each verification device is less than or equal to the resource constraint of that verification device.

[0018] Furthermore, when the connection relationship of the smallest logical unit is represented by a connection node relationship matrix, and the relationship between each node and each verification device is represented by a node device relationship matrix, the connection device relationship matrix obtained by multiplying the connection node relationship matrix and the node device relationship matrix is ​​used to represent the relationship between each connection and each verification device.

[0019] Furthermore, the target segmentation function is:

[0020]

[0021] The Cut represents the equivalent number of connections across verification devices in the netlist (i.e., the ratio of the actual number of connections to the device's connection capacity), d represents the verification device number, n represents the connection number, and y represents the connection sequence number. d,n W represents an element in the connection device relationship matrix. d This indicates the connection capacity of each device.

[0022] The circuit simulation method proposed in this invention includes:

[0023] The netlist of the circuit is segmented using the netlist segmentation method described in the above technical solution;

[0024] The segmented netlists are then subjected to parallel simulation processing.

[0025] This invention is compatible with netlists designed at the gate level or RTL level. Furthermore, it considers netlist logic resources and interconnections for segmentation, and also takes into account the actual FPGA array structure for netlist segmentation layout. Therefore, this invention achieves a highly efficient and universal netlist segmentation method. This invention can directly segment gate-level or RTL-level netlists, reducing the compilation process. Moreover, this invention transforms the segmentation problem into an integer linear programming problem, which is compatible with various third-party solvers. Because this invention can consider the FPGA array structure in the constraints, it can obtain segmentation results that are more adapted to the physical hardware. Attached Figure Description

[0026] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, wherein:

[0027] Figure 1 is an overall flowchart of an embodiment of the present invention. Detailed Implementation

[0028] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0030] As shown in Figure 1, the netlist segmentation method proposed in this invention mainly includes the following steps.

[0031] The process involves acquiring all the smallest logic units (BLUs) and their interconnections in the netlist, treating each BLU as a node. By reading the netlist input file, nodes are constructed based on the BLUs, such as operators (gate-level) or primitives (register-level). Simultaneously, connections (nets) and a hardware information file (Boardfile) are built based on the interconnections of the BLUs. Each connection is a branchless connection formed by sequentially linking the BLUs based on signal transmission, and each connection has at least two nodes.

[0032] Based on the hardware information file, we obtain all verification devices, their capacities, and the interconnections between them. Verification devices refer to FPGAs. When the hardware simulation accelerator performs parallel simulation, it involves multiple FPGAs based on the netlist. FPGAs may or may not be interconnected. Here, "connected" refers to the physical signal lines that allow them to communicate with each other. For example, there are 600 interconnected physical signal lines between FPGA1 and FPGA2, while there are 0 non-connected physical signal lines between FPGA2 and FPGA3.

[0033] The relationship between each node and each verification device is treated as a variable, and conditions are imposed on all variables based on the limitations of the verification devices. When a node is placed in a verification device, the variable representing the relationship between that node and that verification device takes the value 1; when a node is not placed in a verification device, the variable representing the relationship between that node and that verification device takes the value 0. Specifically, determining which node to place in which FPGA is the objective of this invention; therefore, the relationship between each node and each verification device is a variable.

[0034] The relationship between each connection and each verification device is obtained based on the connection relationships of the smallest logical units and the relationship between each node and each verification device. By understanding which nodes are on each connection, and then combining the variables of the relationship between nodes and verification devices, the connection-device relationship with corresponding variables can be obtained.

[0035] The target segmentation function is constructed based on the relationship between each connection and each verification device, as well as the interconnection relationships between the verification devices. This step constructs a target segmentation function containing corresponding variables, which refer to the relationships between nodes and verification devices.

[0036] The objective segmentation function is solved by a solver based on the conditional constraints of all variables.

[0037] When the solver has a solution, the solver output is the netlist partitioning result. The solution can obtain the specific values ​​of the variables relating the nodes to the verification device, that is, the location information of each node on the verification device.

[0038] If the solver has no solution, it means that the corresponding partitioning requirements cannot be met, and it will exit with an error message.

[0039] The present invention directly segments the gate-level or register-level (RTL-level) netlist through the above technical solution, reducing the compilation process. At the same time, the FPGA array structure can be considered in the constraints to obtain a segmentation result that is more adapted to the physical hardware.

[0040] In one embodiment, the connection relationship of the smallest logical unit of the present invention is represented by a connection node relationship matrix. Each row or column of the connection node relationship matrix represents a branchless connection formed by the sequential connection of nodes. For example, whenever each row of the connection node relationship matrix represents a connection, then each column represents a node. The element of each column corresponding to a connection is the value of whether the node in the corresponding column is on the connection. For example, if the node corresponding to the current column is on the connection, then the value of the element in the row corresponding to the connection and the element in the column corresponding to the node is 1, otherwise it is 0.

[0041] In one embodiment, the interconnection relationship between the verification devices is represented by a device interconnection matrix. Each element of the device interconnection matrix represents the number of interconnection signal lines between the verification device in the row and the verification device in the column. For example, if the number of connections between FPGA1 and FPGA2 is 600, then the value of the element in the row represented by FPGA1 and the column represented by FPGA2 is 600, and similarly, the value of the element in the column represented by FPGA1 and the row represented by FPGA2 is also 600.

[0042] In one embodiment, the relationship between each node and each verification device is represented by a node-device relationship matrix, where each element of the node-device relationship matrix is ​​a variable, and the variable takes the value of 0 or 1.

[0043] Since the placement of nodes in the verification device must meet the actual conditions of the verification device, in one embodiment, the constraints may include: the sum of all variables in each row or column corresponding to each node in the node-device relationship matrix is ​​1, meaning that a node can only be placed in one FPGA. The sum of all variables in each column or row corresponding to each verification device in the node-device relationship matrix is ​​less than or equal to the resource constraints of that verification device.

[0044] When the connection relationship of the smallest logical unit is represented by the connection node relationship matrix, and the relationship between each node and each verification device is represented by the node device relationship matrix, the connection device relationship matrix can be obtained by multiplying the connection node relationship matrix and the node device relationship matrix to represent the relationship between each connection and each verification device.

[0045] In the above technical solution, the target segmentation function can specifically add the elements corresponding to the verification devices in each row or column of the connection device relationship matrix to obtain the number of cross-device connections of the verification device, add the elements corresponding to the verification devices in each row or column of the device interconnection matrix to obtain the number of interconnection signal lines of the verification device, divide the number of cross-device connections of each verification device by the number of interconnection signal lines of the verification device to obtain the equivalent segmentation line number of each verification device, and solve for the minimum equivalent segmentation line number of all verification devices.

[0046] The target segmentation function can be expressed by the following formula:

[0047]

[0048] Cut represents the equivalent number of connections across verification devices in the netlist (i.e., the ratio of the actual number of connections to the device's connection capacity), d represents the verification device number, n represents the connection number, and y represents the connection sequence number. d,n W represents an element in the connection device relationship matrix. d This indicates the connection capacity of each device.

[0049] The following describes a specific embodiment of the present invention in detail, using a matrix implementation as an example.

[0050] When performing fully automatic partitioning of gate-level or netlist-level DUT designs, the synthesized gate-level netlist-level design is read first, and the smallest logical unit in the netlist is counted as the partitioning unit to count the netlist resources.

[0051] Construct a node-device relationship matrix, i.e., the Node*Device matrix in the table below, where x_0_0, etc., each represent a variable.

[0052] FPGA0FPGA1FPGA2FPGA3...FPGAnNode0x_0_0x_0_1x_0_2x_0_3...x_0_nNode1x_1_0x_1_1x_1_2x_1_3 ……x_1_nNode2x_2_0x_2_1x_2_2x_2_3……x_2_nNode3x_3_0x_3_1x_3_2x_3_3……x_3_n…………………………………… surface

[0053] Table 1 Node Device Relationship Matrix

[0054] Add placement constraints to indicate that each Node can only be placed in one Device.

[0055]

[0056] A resource constraint is added, meaning the sum of all resources of each node in each column must not exceed the resources that the verification device can accommodate. R_Nx represents the resource of node x. R_Dx represents the resource of verification device x.

[0057]

[0058] Based on the interconnection information of the Net, a node relationship matrix is ​​established, namely the Net*Node matrix, which represents the nodes contained in each Net.

[0059]

[0060]

[0061] Table 2. Matrix of Connection Nodes

[0062] Multiplying the Net*Node matrix by the Node*Device matrix yields the Net*Device matrix, which is the interconnection device relationship matrix. This interconnection device relationship matrix represents the mapping of each interconnection Net in the verification device, that is, the segmentation result of each Net in the device.

[0063]

[0064] Table 3. Connection Device Relationship Matrix

[0065] A Device*Device matrix, or device interconnection matrix, is constructed based on the boardfile (hardware information file) to represent the interconnection relationships between verification devices. As shown in the table below, each row represents the interconnection capacity from Device X to Device Y.

[0066] FPGA0FPGA1FPGA2FPGA3……FPGA006002000……FPGA16000600……FPGA22006000……FPGA30000…………………………………… surface

[0067] Table 4 Device Interconnection Relationship Matrix

[0068] Based on the Net*Device matrix and the Device*Device matrix, the interconnection between Devices can be considered as the objective function. With minimization as the objective, the objective function can be expressed as:

[0069]

[0070] First, the elements of each column in the Net*Device matrix are added together to obtain the current Device Cut. Then, the columns of the Device interconnection matrix are added together to obtain the current Device interconnection capacity. After dividing, the results are accumulated to obtain the target Cut.

[0071] Based on the above steps, the conditional constraints and objective function of the required ILP solver are obtained. The solution can then be obtained using the ILP (Integer Linear Programming) solver.

[0072] If the solver finds a solution, it outputs the segmentation result, where each x-value represents the location information of the device containing each Node. If no solution is found, it reports an error and exits.

[0073] The present invention also protects the simulation method of the circuit, which adopts the netlist segmentation method of the above-mentioned technical solution to segment the netlist of the circuit, and then performs parallel simulation processing on the segmented netlist.

[0074] The netlist segmentation method of the present invention can directly segment the netlist, and the segmentation method of the present invention can be constrained based on the FPGA array structure through condition constraints. At the same time, the segmentation method is also compatible with gate-level netlists and RTL-level designs.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for segmenting a netlist, characterized in that, include: Obtain all the smallest logical units in the netlist and the connections between them, and treat each smallest logical unit as a node; Based on the hardware information file, all verification devices, their capacities, and interconnection relationships are obtained. These interconnection relationships are represented by a device interconnection matrix, where each element represents the number of interconnection signal lines between the verification device in the row and column corresponding to that element. The relationship between each node and each verification device is used as a variable, and conditions are constrained for all variables based on the limitations of the verification devices. The relationship between each node and each verification device is represented by a node-device relationship matrix, where each element is a variable with a value of 0 or 1. Based on the connection relationships of the smallest logical units and the relationship between each node and each verification device, the relationship between each connection and each verification device is obtained. When the connection relationships of the smallest logical units are represented by a connection-node relationship matrix, and the relationship between each node and each verification device is represented by a node-device relationship matrix, the connection-device relationship matrix obtained by multiplying the connection-node relationship matrix and the node-device relationship matrix represents the relationship between each connection and each verification device. A target segmentation function is constructed based on the relationship between each connection and each verification device and the interconnection relationships between the verification devices. The target segmentation function is: The Cut represents the equivalent number of connections across verification devices in the netlist, d represents the serial number of the verification device, n represents the connection serial number, and y represents the number of connections. d,n W represents an element in the connection device relationship matrix. d This represents the connection capacity of each device; the target segmentation function is solved by a solver based on the conditional constraints of all variables; when the solver has a solution, the output of the solver is the segmentation result of the netlist.

2. The netlist segmentation method as described in claim 1, characterized in that, The connection relationship of the smallest logical unit is represented by a connection node relationship matrix. Each row or column of the connection node relationship matrix represents a branchless connection formed by the sequential connection of nodes.

3. The netlist segmentation method as described in claim 1, characterized in that, The constraints include: the sum of all variables in each row or column corresponding to each node is 1; the sum of all variables in each column or row corresponding to each verification device is less than or equal to the resource constraint of that verification device.

4. A circuit simulation method, characterized in that, include: The netlist of the circuit is segmented using the netlist segmentation method described in any one of claims 1 to 3; The segmented netlists are then subjected to parallel simulation processing.

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