A Method for Constructing In-Memory Neural Networks Based on Two-Dimensional Material Floating Gate Transistors
By constructing an in-memory computing neural network based on two-dimensional material floating gate transistors, and using analog circuits to build connection layers and activation functions, the problem of high energy consumption in multi-layer neural networks is solved, and high-precision, low-power all-hardware neural network computing is realized.
Patent Information
- Application Number
- CN202211538004.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-02
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2042-12-02
AI Technical Summary
Existing technologies still rely on software and digital processors when building multi-layer neural networks, resulting in frequent analog-to-digital conversions and data transmissions, causing unnecessary energy consumption and making it difficult to achieve high-precision, low-power neural network computing.
A memory-computing neural network construction method based on two-dimensional material floating gate transistors is adopted. The connection layer and activation function are constructed using analog circuits to realize the construction of a fully hardware multilayer neural network. Current-voltage conversion, voltage positive and negative determination and voltage inversion output are realized through floating gate transistor crossbar array and peripheral analog circuits.
It achieves high-precision, low-power neural network computation, simplifies the system structure, reduces energy consumption during data transmission, and improves computational efficiency.
Smart Images
Figure CN115994568B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of two-dimensional semiconductor devices, and more specifically, relates to a method for constructing an in-memory computing neural network based on a two-dimensional material floating gate transistor. Background Technology
[0002] Artificial neural networks (ANNs) are information processing systems designed to mimic the structure and function of the human brain. Currently, ANN methods can effectively achieve important functions such as machine vision, speech recognition, and analytical reasoning. Traditional computers are based on the von Neumann architecture, where data storage and computation units are separated. During neural network training and computation, a large amount of data flows back and forth between memory and computation units, significantly increasing system power consumption. The development of non-volatile emerging memory devices such as memristors provides a good solution for in-memory computing without a von Neumann architecture. The resistance of a single memristor can be continuously adjusted by applying an excitation voltage, and more importantly, the resistance remains unchanged when the voltage is removed, thus enabling long-term data storage. Furthermore, by organizing these memristors into a cross array, vector-matrix multiplication and simulation operations can be performed using physical laws such as Ohm's law for multiplication and Kirchhoff's current law, and the computation process can be completed in one step regardless of the array size. Therefore, this in-memory computing scheme avoids the data shuttle required by the traditional von Neumann architecture, thereby greatly reducing power consumption.
[0003] While memristors have been successfully used to build artificial neural networks, they are currently mainly used for single-layer neural networks. Hidden layers in multi-layer neural networks still rely on software and digital processors. Therefore, frequent analog-to-digital conversions and data interpretation still occur during computation, resulting in unnecessary energy consumption. To enhance the computational potential of neural networks, it is necessary to build multi-layer, all-hardware neural networks to achieve high-precision, low-power neural network computation. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention provides a method for constructing an in-memory computing neural network based on two-dimensional material floating gate transistors. The aim is to utilize analog circuits to construct connection layers and activation functions, thereby realizing the construction of a fully hardware multilayer neural network for high-precision, low-power neural network computation.
[0005] To achieve the above objectives, this invention provides a method for constructing an in-memory computing neural network based on a two-dimensional material floating gate transistor, comprising the following steps:
[0006] (1) Fabrication of neural network elements: The neural network elements are semiconductor single-point devices. Each single-point device, according to its structural distribution from bottom to top, consists of a substrate, a back gate electrode, a gate dielectric layer, a floating gate electrode, a tunneling layer, and a two-dimensional material layer. Source and drain electrodes are symmetrically deposited on the upper surface of the two-dimensional material. A neural network array is fabricated using chip technology. The neural network array is a row-column distribution of semiconductor single-point devices. Each drain layer receives a collinear input voltage signal for signal input, and each column of sources outputs a collinear current signal for signal output.
[0007] (2) Prepare the neural network connection layer and activation function. The connection layer and activation function are peripheral analog circuits used for current-to-voltage conversion, voltage positive / negative determination, and voltage inversion output. Map the weight information of the neural network to be trained to the gate voltage of each single-point device in the crossbar array. Adjust the resistance of each single-point device to the resistance value required for the corresponding weight state through the gate voltage. Combined with the collinear output in the second step, data calculation is realized.
[0008] Compared to traditional single-layer neural networks, the neural network array and analog circuit provided in this invention can be used to construct multi-layer, all-hardware neural networks. The analog circuit includes connection layers and activation functions, enabling current-to-voltage conversion, voltage sign determination, and positive / negative output. The processed positive and negative voltage inputs can be used to concisely implement positive and negative weights in the lower-layer neural network array.
[0009] In one embodiment, the fabrication steps of the neural network elements and array are as follows:
[0010] (a) A layer of photoresist is spin-coated on a silicon oxide substrate, and the first layer of photoresist is patterned using a photolithography machine and a mask. Then, the patterned back gate electrodes are fabricated using an electron beam evaporation process and a lift-off process.
[0011] (b) A layer of hafnium oxide is prepared on the upper surface of the back gate electrode as a gate dielectric layer using atomic force deposition. Then, a second photoresist is spin-coated on the surface of the gate dielectric layer. The second photoresist layer is then patterned using a photolithography machine and a mask. Finally, a patterned floating gate electrode is prepared using electron beam evaporation and lift-off processes.
[0012] (c) A layer of hafnium oxide is prepared on the surface of the floating gate electrode as a tunneling layer using atomic force deposition.
[0013] (d) A two-dimensional material monolayer film grown by chemical vapor deposition is transferred to the upper surface of the tunneling layer using a wet transfer method, and a third layer of photoresist is spin-coated on the upper surface of the film. The third photoresist is then patterned using a photolithography machine and a mask. Subsequently, source and drain electrodes are prepared by electron beam evaporation and lift-off processes.
[0014] In one embodiment, current-to-voltage conversion, voltage sign determination, and voltage inversion output are achieved through the cooperation of an operational amplifier, a voltage comparator circuit, and a voltage inversion circuit.
[0015] In one embodiment, an overlay alignment process is used to place the channel region between the floating gate electrode and the source / drain electrode on the same plane coordinate.
[0016] In one embodiment, the metal types of the back gate electrode, the floating gate electrode, and the source / drain electrode are Cr / Au, Pt, and Cr / Au, respectively. Metal Cr can improve the adhesion between the electrode and the substrate, metal Au can protect the underlying Cr from oxidation, and at the same time improve the conductivity of the electrode; metal Pt, as a floating gate electrode, can provide sufficient tunneling charge.
[0017] In one embodiment, the thickness of the tunneling layer is 5 nm to 10 nm. If the thickness is less than 5 nm, it may cause leakage current; conversely, if it is greater than 10 nm, it will increase the voltage required for tunneling and increase the system power consumption.
[0018] In one embodiment, the thickness of the gate dielectric layer is 20 nm to 50 nm. This thickness range ensures stable transistor performance while resulting in a lower gate voltage compared to traditional silicon oxide dielectric layers, which helps reduce system power consumption.
[0019] The present invention also provides an in-memory neural network based on a two-dimensional material floating gate transistor, which is obtained by the above-described method for constructing an in-memory neural network based on a two-dimensional material floating gate transistor.
[0020] This invention provides a method for constructing an in-memory neural network based on two-dimensional material floating gate transistors, including a floating gate transistor crossbar array device and peripheral analog circuits. The analog circuits are used to construct connection layers and activation functions, which can realize the construction of a fully hardware multilayer neural network and can be used for high-precision, low-power neural network operations. Attached Figure Description
[0021] Figure 1 This is a flowchart illustrating the implementation of the in-memory computing neural network construction method based on two-dimensional material floating gate transistors provided in this embodiment of the invention.
[0022] Figure 2 This is a schematic diagram of the floating gate transistor structure provided in an embodiment of the present invention;
[0023] Figure 3 This is a flowchart of the floating gate transistor fabrication process provided in an embodiment of the present invention;
[0024] Figure 4 This is a schematic diagram of the neural network array structure provided in an embodiment of the present invention;
[0025] Figure 5 This is a schematic diagram of an analog circuit provided in an embodiment of the present invention. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0027] Figure 1 This invention illustrates a method for constructing an in-memory neural network based on a two-dimensional material floating gate transistor, comprising the following steps:
[0028] S1 obtains a neural network device by sequentially attaching a back gate electrode, a gate dielectric layer, a floating gate electrode, a tunneling layer, and a two-dimensional material layer on a substrate, and depositing a source and a drain on the upper surface.
[0029] S2 obtains a neural network array by arranging the neural network elements in rows and columns;
[0030] In the neural network array, each layer has a common drain input voltage signal for signal input, and each column has a common source output current signal for signal output.
[0031] S3 connects multiple neural network arrays through peripheral analog circuits to form a neural network;
[0032] The peripheral analog circuit includes a connection layer, an activation function, and an inverter, used to realize current-to-voltage conversion, voltage positive / negative determination, and voltage inversion output.
[0033] The process includes the following steps after step S3: S4 mapping the weight information of the neural network to be trained to the gate voltage of each neural network element in the neural network array, adjusting the resistance of each neural network element to the resistance value required for the corresponding weight state through the gate voltage, and combining collinear output to realize data calculation.
[0034] In this embodiment of the invention, step S1 specifically includes:
[0035] S11 spin-coats a layer of photoresist on a silicon oxide substrate, uses a photolithography machine and a mask to pattern the first layer of photoresist, and uses electron beam evaporation and lift-off processes to prepare patterned back gate electrodes.
[0036] S12 uses atomic force deposition to prepare a layer of hafnium oxide as a gate dielectric layer on the upper surface of the back gate electrode. A second layer of photoresist is spin-coated on the surface of the gate dielectric layer. The second layer of photoresist is patterned using a photolithography machine and a mask. Patterned floating gate electrodes are prepared using electron beam evaporation and lift-off processes.
[0037] S13 uses atomic force deposition to prepare a layer of hafnium oxide as a tunneling layer on the upper surface of the floating gate electrode;
[0038] S14 uses wet transfer to transfer a two-dimensional material monolayer film grown by chemical vapor deposition to the upper surface of the tunneling layer, and spin-coates a third layer of photoresist on the upper surface of the two-dimensional material film. The third layer of photoresist is patterned using a photolithography machine and a mask, and source and drain electrodes are prepared by electron beam evaporation and lift-off processes.
[0039] As an embodiment of the present invention, in step S14, the channel region between the floating gate electrode and the source / drain electrode can be placed on the same plane coordinate using an overlay alignment process.
[0040] In step S14, the two-dimensional material can be MoS2, MoSe2, or WSe2. These materials have mature processing techniques, are easy to prepare on a large scale, and exhibit stable properties, allowing them to adapt to changes in the external environment.
[0041] As an embodiment of the present invention, the thickness of the tunneling layer can be 5nm to 10nm; the thickness of the gate dielectric layer can be 20nm to 50nm.
[0042] The peripheral analog circuit includes an operational amplifier, a voltage comparator circuit, and a voltage inverting circuit. The current output from each column is summed according to Kirchhoff's current law and then input to the operational amplifier. The operational amplifier converts the circuit signal into a voltage signal. Then, the operational amplifier passes the voltage signal to the voltage comparator circuit. The voltage comparator circuit determines the positive or negative value of the voltage. If it is positive, it is input to the voltage inverting circuit in its original position. If it is negative, the voltage is zeroed and then input to the voltage inverting circuit. Finally, the voltage inverting circuit inputs the voltage signal to the next layer of the neural network.
[0043] This invention provides a method for constructing an in-memory computing neural network based on a two-dimensional material floating-gate transistor, and implements a fully hardware-based multilayer neural network simulation computation based on this neural network. A schematic diagram of the floating-gate transistor structure and a flowchart of its fabrication process are shown below. Figure 2 and Figure 3 As shown, because the tunneling layer is very thin, electrons or holes can pass through the tunneling layer and be stored on the floating gate electrode under the influence of the back gate voltage. When the voltage is removed, the stored charge remains unchanged. Therefore, information storage can be achieved by continuously changing the transistor resistance value through the back gate voltage. A schematic diagram of the neural network array structure is shown below. Figure 4 As shown, in-memory computation can be achieved in one step through matrix multiplication and simulation operations. By using analog circuits to construct inter-layer connection layers and activation functions, multi-layer all-hardware neural network computation can be realized.
[0044] Analog circuit diagram as shown Figure 5As shown, the circuit consists of two parts: an activation function circuit for voltage comparison and an inverter circuit for voltage inversion output. The activation function circuit works as follows: Vin is compared with a 0 level via a comparator. When Vin > 0, the comparator outputs a high level; otherwise, it outputs a low level. The comparator output serves as the control signal for analog switch S1. When the control signal is high, Vout = Vin; otherwise, Vout = 0. This achieves: when Vin > 0, Vout = Vin; when Vin < 0, Vout = 0, thus implementing the ReLU activation function in hardware. The inverter circuit: Vin first passes through a pre-amplifier to achieve Vout' = -(R2 / R1)*Vin, where R2 is typically greater than or equal to R1. The subsequent stage is a follower circuit, where Vout = Vout', primarily reducing the overall internal resistance and increasing the load capacity of Vout.
[0045] Example 1:
[0046] The implementation scheme for obtaining neural network elements is as follows:
[0047] Fabrication of the back gate electrode: First, the Si / SiO2 silicon wafer is cut into appropriate sizes, then cleaned and dried according to standard cleaning procedures. Next, a layer of photoresist is spin-coated on the surface of the silicon wafer and patterned using photolithography. Then, a 50nm thick Cr / Au film is deposited on the surface of the photoresist using electron beam evaporation. Finally, the photoresist and excess metal film are peeled off using a lift-off process to obtain the patterned back gate electrode.
[0048] Fabrication of the gate dielectric layer, floating gate electrode, and tunneling layer: A 20 nm hafnium oxide gate dielectric layer was fabricated using atomic force deposition, followed by selective deposition of the gate dielectric layer surface. Figure 1 A layer of photoresist is first applied, then patterned using photolithography. A Pt thin film is then deposited on the photoresist surface using electron beam evaporation. The photoresist and excess metal film are then peeled off using a lift-off process to obtain a patterned floating gate electrode. Finally, an 8nm thick hafnium oxide layer is deposited on the silicon wafer surface using atomic force deposition as a tunneling layer.
[0049] Transfer of two-dimensional materials (taking MoS2 as an example): Large-area continuous monolayer MoS2 material is grown on copper foil by chemical vapor deposition. The MoS2 film is transferred to the surface of the tunneling layer by wet transfer, and the film is patterned by reactive ion etching.
[0050] Fabrication of source and drain electrodes and metal interconnects: Then, using the same photolithography process, 50 nm thick source and drain electrodes are fabricated on a patterned molybdenum sulfide film. The drains of floating gate transistors in the same row are connected, and the sources in the same column are connected. At the point where the row and column lines overlap, an aluminum oxide insulating layer is deposited to prevent short circuits.
[0051] Example 2:
[0052] Analog circuit design and multilayer neural network calculation: This example uses a three-layer neural network for illustration.
[0053] The first layer of the neural network consists of 24 floating-gate transistors (8 rows, 3 columns); the second layer consists of 18 floating-gate transistors (6 rows, 3 columns); and the third layer consists of 12 floating-gate transistors (6 rows, 2 columns). The layers are connected via analog circuitry. The working principle is as follows: eight current signals generated by external stimuli are input to the eight drains of the first layer. After matrix multiplication, three current signals are obtained. These current signals are then transmitted to the inter-layer analog circuitry. The analog circuitry uses operational amplifiers to convert the current into voltage signals, and then uses a comparator circuit to determine the voltage sign, treating negative voltages as zero and positive voltages as unchanged. Furthermore, to introduce equivalent negative weights, an inverter is used to invert the compared voltages, thus transforming one current signal into a set of equal-magnitude, opposite-signal voltage signals. The analog circuitry inputs the six voltage signals obtained from the calculations into the six drains of the second layer. After matrix multiplication, three current signals are obtained. The same analog circuitry is used to obtain six more voltage signals, which are then input to the six drains of the third layer. Finally, matrix summation is used to obtain two more current signals, which are then processed by a comparator circuit to complete the neural network calculation.
[0054] This invention provides a method for constructing an in-memory computing neural network based on two-dimensional material floating gate transistors. Floating gate transistors provide stable and low-power information storage, while crossbar arrays provide fast matrix summation operations. Furthermore, the analog circuits between layers not only realize analog conversion between signals without the need for external software and microprocessors, simplifying the system structure, but also indirectly provide negative weights through the activation functions and inverters introduced in the analog circuits, optimizing the data structure and improving computational accuracy.
[0055] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for constructing an in-memory computing neural network based on a two-dimensional material floating-gate transistor, characterized in that, Includes the following steps: S1 obtains a neural network device by sequentially attaching a back gate electrode, a gate dielectric layer, a floating gate electrode, a tunneling layer, and a two-dimensional material layer on a substrate, and depositing a source and a drain on the upper surface. S2 obtains a neural network array by arranging the neural network elements in rows and columns; In the neural network array, each layer has a common drain input voltage signal for signal input, and each column has a common source output current signal for signal output. S3 connects multiple neural network arrays through peripheral analog circuits to form a neural network; The peripheral analog circuit includes a connection layer, an activation function, and an inverter, which are used to realize current-to-voltage conversion, voltage positive / negative determination, and voltage inversion output. The peripheral analog circuit includes: an operational amplifier, a voltage comparator circuit, and a voltage inverting circuit connected in sequence; The operational amplifier is used to convert the circuit signal into a voltage signal and transmit it to the voltage comparison circuit; the current output from each column is summed according to Kirchhoff's current law and used as the circuit signal. The voltage comparison circuit is used to determine the positive or negative nature of the voltage. If it is positive, it outputs the voltage to the voltage inverting circuit in its original position. If it is negative, the voltage is zeroed and then output to the voltage inverting circuit. The voltage inverting circuit is used to output the voltage signal to the next layer of the neural network. The process after step S3 also includes: S4 maps the weight information of the neural network to be trained to the gate voltage of each neural network element in the neural network array. The gate voltage is used to adjust the resistance of each neural network element to the resistance value required for the corresponding weight state, and data calculation is achieved by combining collinear output.
2. The method for constructing an in-memory computing neural network as described in claim 1, characterized in that, Step S1 is as follows: S11 spin-coats a layer of photoresist on a silicon oxide substrate, uses a photolithography machine and a mask to pattern the first layer of photoresist, and uses electron beam evaporation and lift-off processes to prepare patterned back gate electrodes. S12 uses atomic force deposition to prepare a layer of hafnium oxide as a gate dielectric layer on the upper surface of the back gate electrode. A second layer of photoresist is spin-coated on the surface of the gate dielectric layer. The second layer of photoresist is patterned using a photolithography machine and a mask. Patterned floating gate electrodes are prepared using electron beam evaporation and lift-off processes. S13 uses atomic force deposition to prepare a layer of hafnium oxide as a tunneling layer on the upper surface of the floating gate electrode; S14 uses wet transfer to transfer a two-dimensional material monolayer film grown by chemical vapor deposition to the upper surface of the tunneling layer, and spin-coates a third layer of photoresist on the upper surface of the two-dimensional material film. The third layer of photoresist is patterned using a photolithography machine and a mask, and source and drain electrodes are prepared by electron beam evaporation and lift-off processes.
3. The method for constructing an in-memory computing neural network as described in claim 2, characterized in that, In step S14, the channel region between the floating gate electrode and the source / drain electrode is placed on the same plane coordinate using an overlay alignment process.
4. The method for constructing an in-memory computing neural network as described in claim 2, characterized in that, The metal types of the back gate electrode, the floating gate electrode, and the source / drain electrode are Cr / Au, Pt, and Cr / Au, respectively.
5. The method for constructing an in-memory computing neural network as described in any one of claims 2 to 4, characterized in that, In step S14, the two-dimensional material is MoS2, MoSe2, or WSe2.
6. The method for constructing an in-memory computing neural network as described in any one of claims 2 to 4, characterized in that, The thickness of the tunneling layer is 5nm to 10nm.
7. The method for constructing an in-memory computing neural network as described in any one of claims 2 to 4, characterized in that, The thickness of the gate dielectric layer is 20 nm to 50 nm.
8. A memory-integrated neural network based on two-dimensional material floating-gate transistors, characterized in that, It is obtained by using the in-memory computing neural network construction method as described in any one of claims 1 to 7.