Semiconductor structure and method of forming the same, stack structure and method of forming the same

Abstract

The embodiments of the present disclosure provide a semiconductor structure and a forming method thereof, and a stack structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises: providing an initial substrate; the initial substrate at least comprises an initial back-end-of-line layer, and an initial wiring layer located on the initial back-end-of-line layer and having a first groove; etching the initial substrate along the first groove to form a wiring layer and a via; and filling a conductive material in the via to form a conductive column in communication with the wiring layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same, and a stacked structure and a method for forming the same. Background Technology

[0002] Through-Silicon Via (TSV) technology in Dynamic Random Access Memory (DRAM) enables the stacking of 4X / 8X DRAM chips for high-speed and broadband applications. However, the large copper-filled TSVs (5×5 / 10×10 micrometers) degrade the Chemical Mechanical Polishing (CMP) process conditions; furthermore, the thermal budget of the bonding results in poor planarization of the copper pillar-to-pump surface. Therefore, a new method for forming TSVs is needed. Summary of the Invention

[0003] This disclosure provides a semiconductor structure and a method for forming the same, as well as a stacked structure and a method for forming the same.

[0004] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, comprising: providing an initial substrate; the initial substrate comprising at least an initial back-end process layer and an initial wiring layer located on the initial back-end process layer and having a first groove; etching the initial substrate along the first groove to form the wiring layer and a via; and filling the via with a conductive material to form a conductive pillar communicating with the wiring layer.

[0005] In some embodiments, the thickness of a portion of the initial wiring layer at the bottom of the first groove is less than the thickness of a portion of the initial wiring layer on the initial subsequent process layer.

[0006] In some embodiments, the first groove of the initial wiring layer includes a first opening and a second opening, the first opening being on the second opening, and the opening size and / or tilt angle of the first opening being greater than that of the second opening.

[0007] In some embodiments, the initial substrate further includes an initial device layer and an initial substrate located below the initial back-end process layer; providing the initial substrate includes: providing an initial substrate and forming an initial device layer on the initial substrate; sequentially forming a metal interconnect layer, an initial etch stop layer, and an initial interlayer dielectric layer on the initial device layer; etching the initial interlayer dielectric layer down to the initial etch stop layer to form a second groove to form the initial back-end process layer; and forming the initial wiring layer in the second groove and on the initial interlayer dielectric layer.

[0008] In some embodiments, the thickness of the initial wiring layer on the initial interlayer dielectric layer ranges from 5 to 7 micrometers; the thickness of the initial wiring layer on the second groove ranges from 0.3 to 0.6 micrometers.

[0009] In some embodiments, etching the initial substrate along the first groove to form a wiring layer and a via includes: etching the initial wiring layer downwards based on the first groove to expose the initial interlayer dielectric layer while forming the wiring layer; etching the initial interlayer dielectric layer and the initial etch stop layer to expose the initial device layer; and etching the initial device layer and the initial substrate to form the via.

[0010] In some embodiments, before filling the via with conductive material, the method further includes: forming an initial isolation layer and an initial barrier layer sequentially in the via; etching back the initial isolation layer and the initial barrier layer located on the top sidewall of the via and on the wiring layer to form an isolation layer and a barrier layer; wherein the top surface of the isolation layer and the barrier layer is lower than the top surface of the wiring layer.

[0011] In some embodiments, the thickness of the insulating layer ranges from 0.2 to 0.5 micrometers; the thickness of the barrier layer ranges from 100 to 500 angstroms.

[0012] In some embodiments, the width of the first groove ranges from 5 to 10 micrometers; the depth of the first groove ranges from 3 to 5 micrometers; the diameter of the conductive post ranges from 3 to 15 micrometers; and the length of the conductive post ranges from 30 to 100 micrometers.

[0013] In a second aspect, embodiments of this disclosure provide a semiconductor structure, comprising: a substrate, the substrate including at least a back-end processing layer and a wiring layer located on the surface of the back-end processing layer; and a conductive pillar penetrating the substrate, wherein the wiring layer includes a portion surrounding and physically contacting the conductive pillar.

[0014] In some embodiments, the subsequent process layer includes a first hole and a second hole, wherein the first hole is located on the second hole, and the opening size of the first hole is larger than the opening size of the second hole; the top surface of the conductive post is located between the top surface of the second hole and the top surface of the wiring layer.

[0015] In some embodiments, the surface of the second hole has a portion of the wiring layer, and the thickness of the portion of the wiring layer in the direction of the sidewall of the second hole gradually decreases with increasing depth.

[0016] In some embodiments, the portion of the wiring layer surrounding the conductive post includes a first opening and a second opening, the first opening being on top of the second opening, and the opening size and / or tilt angle of the first opening being greater than that of the second opening.

[0017] Thirdly, embodiments of this disclosure provide a method for forming a stacked structure, comprising: providing a first chip and a second chip; wherein at least one of the first chip and the second chip is formed using the forming method described in any of the above embodiments; and bonding the first chip and the second chip together.

[0018] Fourthly, embodiments of this disclosure provide a stacked structure, including: a first chip and a second chip, wherein at least one of the first chip and the second chip is formed using the formation method described in any of the above embodiments; the first chip and / or the second chip includes a substrate and conductive pillars; the substrate includes at least a back-end processing layer and a wiring layer located on the surface of the back-end processing layer; the conductive pillars penetrate the substrate, and the wiring layer includes a portion surrounding and physically contacting the conductive pillars; the first chip and the second chip are bonded through the conductive pillars.

[0019] In this embodiment, firstly, an initial substrate is provided; the initial substrate includes at least an initial subsequent process layer and an initial wiring layer located on the initial subsequent process layer and having a first groove; secondly, the initial substrate is etched along the first groove to form the wiring layer and vias; finally, conductive material is filled into the vias to form conductive pillars communicating with the wiring layer. In this way, on the one hand, when etching the initial substrate to form vias, the initial wiring layer can be used directly as a mask, eliminating the need to form an additional mask layer, thereby simplifying the process and reducing costs; on the other hand, since the size of the conductive pillar is limited by the width of the wiring layer when forming it, the end area of ​​the formed conductive pillar is small, thereby reducing the parasitic capacitance between the conductive pillar and the metal interconnect layer in the subsequent process layer. Attached Figure Description

[0020] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0021] Figure 1 A schematic diagram illustrating the implementation process of a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0022] Figures 2 to 6 This is a schematic diagram illustrating the formation process of a semiconductor structure according to an embodiment of the present disclosure;

[0023] Figure 7 A schematic diagram illustrating the implementation flow of a method for forming a stacked structure according to an embodiment of this disclosure;

[0024] Figure 8 This is a schematic diagram of the composition of a stacked structure provided in an embodiment of the present disclosure. Detailed Implementation

[0025] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0026] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0027] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0030] Before introducing the embodiments of this disclosure, TSV and related terms in the related art will be introduced first.

[0031] In related technologies, two methods are used to form TSVs: one is a middle process, where the TSV is formed first, and then a metal interconnect layer M1 is formed on the TSV; the other is a last process, where the metal interconnect layer M1 is formed first, then the wafer is flipped over, and finally the TSV is formed. Both methods result in TSVs located on the metal interconnect layer M1, which are then processed through a back end of line (BEOL) process to the top metal layer, the redistribution layer (RDL). This results in higher contact / metal resistance.

[0032] Meanwhile, in the multi-chip stacked structure, the TSV, M1, parasitic capacitance / resistance (RC / RS) of the back-end process and the bonding surface of chip 1 will form a path with the TSV, M1, parasitic capacitance / resistance of the back-end process and the bonding surface of chip 2. As a result, the parasitic capacitance and resistance of the entire stacked structure are relatively large.

[0033] In addition, the large area of ​​the metal structure at both ends of the formed through-silicon via (TSV) will increase the parasitic capacitance between the TSV and the metal interconnect layer.

[0034] The front end of the line (FEOL) process includes: defining the active area on the substrate to fabricate memory devices (transistors), followed by ion implantation to create N-type and P-type regions, then fabricating the gate, and finally ion implantation again to complete the source and drain of each transistor. This part of the process is for forming memory devices, such as N-type and P-type field-effect transistors, on the substrate.

[0035] The intermediate process (MOL) can be the process of forming contact holes such as source / drain contacts, gate contacts, and via structures.

[0036] The subsequent process can be to build several layers of conductive metal lines and interconnect the different layers of metal lines through columnar metal.

[0037] In view of this, embodiments of this disclosure provide a method for forming a semiconductor structure, with reference to... Figure 1 The method includes steps S101 to S103, wherein:

[0038] Step S101, providing an initial substrate; the initial substrate includes at least an initial subsequent process layer and an initial wiring layer located on the initial subsequent process layer and having a first groove;

[0039] Here, the initial post-process layer can be a general term for the structural layers formed by subsequent processes, and therefore can include metal interconnect layers, vias, initial inter-metal dielectric (IMD) layers, initial etch stop layers, etc. The number of metal interconnect layers can be set according to design requirements; for example, four metal interconnect layers can be set, namely metal interconnect layers M0, M1, M2, and M3. The number of via layers can be designed according to the number of metal interconnect layers; for example, four metal interconnect layers can be set with three vias, namely vias V0, V1, and V2.

[0040] The function of the metal interconnect layer M1 is to connect the vias V1 in different regions. Vias V1 are the connection channels between metal interconnect layers M1 and M2 formed on the initial interlayer dielectric layer, and vias V2 are the connection channels between metal interconnect layers M2 and M3 formed on the initial interlayer dielectric layer. The initial etch stop layer can be located between the metal interconnect layer and the initial interlayer dielectric layer.

[0041] In some embodiments, the initial substrate further includes an initial device layer and an initial substrate located below the subsequent process layer. Here, the initial device layer may include a structural layer formed in the preceding process and a structural layer formed in the intermediate process. For example, the initial device layer may include a memory device (e.g., a transistor) and contact holes. The contact holes are connection channels between the memory device and the metal interconnect layer M0.

[0042] In some embodiments, step S101 may include steps S1011 to S1014, wherein:

[0043] Step S1011: Provide an initial substrate and form an initial device layer on the initial substrate;

[0044] Here, the initial substrate can be a single layer, such as a silicon (Si) substrate, a germanium (Ge) substrate, a germanium-silicon (SiGe) substrate, a gallium arsenide substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display; it can also be multilayered, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In other embodiments, the initial substrate can also be an ion-doped substrate, such as a p-type doped substrate or an n-type doped substrate.

[0045] In some embodiments, shallow trench isolation (STI) may also be formed within the initial substrate, isolating several active regions arranged in an array or other distribution type within the initial substrate. STI is formed by forming trenches within the initial substrate and then filling the trenches with an isolation material layer. The material filling the STI may include silicon nitride or silicon oxide, with silicon oxide formed by thermal oxidation.

[0046] refer to Figure 2 An initial substrate 11a is provided, which includes a shallow trench isolation 111; an initial device layer (not shown) is then formed on the initial substrate 11a.

[0047] Step S1012: A metal interconnect layer, an initial etch stop layer, and an initial interlayer dielectric layer are sequentially formed on the initial device layer;

[0048] Here, when selecting materials for the metal interconnect layer, factors such as the resistivity of the interconnect material, the step coverage and surface smoothness of the deposition process, electromigration, and stress need to be considered. Using materials with low resistivity for interconnects can reduce chip losses and RC delay, thereby increasing chip speed. RC delay refers to the signal delay caused by resistance and capacitance during charging and discharging. The materials for the metal interconnect layer can be conductive materials such as copper, tungsten, or aluminum. The initial etch stop layer serves to reduce over-etching; the materials used can be silicon carbide (SiCN) or silicon nitride (SiN).

[0049] The initial interlayer dielectric layer serves to isolate different metal interconnect layers. It is made of low-k or ultra-low-k materials, such as carbon-doped oxide (SiCOH) or silicon oxide.

[0050] During implementation, an electroplating process can be used to form the metal interconnect layer; the initial etch stop layer and the initial interlayer dielectric layer can be formed by any of the following suitable deposition processes: Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), spin coating, or coating process.

[0051] Continue to refer to Figure 2 Metal interconnect layers M0 / M1 / M2 / M3, an initial etch stop layer, and an initial interlayer dielectric layer 121a are sequentially formed on the initial device layer.

[0052] Step S1013: Etch the initial interlayer dielectric layer to the initial etching stop layer to form a second groove, thereby forming the initial subsequent process layer;

[0053] Here, either wet or dry etching processes can be used to etch the initial interlayer dielectric layer. Dry etching processes can include reactive ion etching technology, plasma etching technology, etc. This disclosure does not limit the type of wet or dry etching process.

[0054] It should be noted that the second groove is a re-distribution layer via (RDV). The sidewalls of the second groove can be vertical or inclined, and this embodiment of the present disclosure is not limited in this respect.

[0055] Continue to refer to Figure 2 The initial interlayer dielectric layer 121a is etched to the initial etch stop layer to form the second groove A, thereby forming the initial post-process layer 12a.

[0056] Step S1014: An initial wiring layer is formed in the second groove and on the initial interlayer dielectric layer.

[0057] Here, a suitable deposition process, such as physical vapor deposition, can be used to form the initial wiring layer. The material of the initial wiring layer can be aluminum or copper, which can reduce the resistivity of the wiring layer.

[0058] refer to Figure 3 An initial wiring layer 13a is formed in the second groove A and on the initial interlayer dielectric layer 121a, thus forming the initial substrate 10. It should be noted that after the initial wiring layer 13a is formed, for example by physical vapor deposition, an automatic layer will form... Figure 3 The morphology in the initial wiring layer 13a is such that it has a first groove B.

[0059] In some embodiments, continue to refer to Figure 3 The thickness d1 of a portion of the initial wiring layer 13a at the bottom of the first groove B is less than the thickness d2 of a portion of the initial wiring layer 13a on the initial subsequent process layer 12a. That is, the initial wiring layer consists of three parts: a first part located at the bottom of the first groove B, a second part located on the initial subsequent process layer 12a, and a third part located on the side wall of the first groove B, and the thickness of the first part is less than the thickness of the second part.

[0060] In some embodiments, the thickness of the initial wiring layer 13a located on the initial interlayer dielectric layer 121a ranges from 5 to 7 μm; the thickness of the initial wiring layer 13a located on the second groove A ranges from 0.3 to 0.6 μm.

[0061] In this way, when etching the initial substrate along the first groove in the subsequent process, the initial wiring layer at the bottom of the first groove can be etched in a self-aligned manner without the need for a photomask, thereby simplifying the process flow.

[0062] In some embodiments, the width of the first groove ranges from 5 to 10 μm, and the depth of the first groove ranges from 3 to 5 μm. This makes it easier to etch the initial substrate.

[0063] In some embodiments, continue to refer to Figure 3 The first groove B includes a first opening B1 and a second opening B2, with the first opening B1 situated on the second opening B2. The opening size L1 of the first opening B1 is larger than the opening size L2 of the second opening B2. In some embodiments, the tilt angle θ1 of the first opening B1 is larger than the tilt angle θ2 of the second opening B2. In other embodiments, the opening size L1 of the first opening B1 is larger than the opening size L2 of the second opening B2, and the tilt angle θ1 of the first opening B1 is larger than the tilt angle θ2 of the second opening B2. In embodiments of this disclosure, the opening size and / or tilt angle of the first opening are larger than those of the second opening, which is beneficial for etching the initial substrate or for self-aligned etching of the initial substrate.

[0064] Step S102: Etch the initial substrate along the first groove to form a wiring layer and vias;

[0065] Here, either wet etching or dry etching can be used to etch the initial substrate.

[0066] Also refer to Figure 3 and Figure 4The initial substrate 10 is etched along the first groove B to form a wiring layer 13 and a via 20. While forming the via 20, the remaining initial post-process layer forms the post-process layer 12. It can be seen that the post-process layer 12 includes two holes, namely a first hole 122 and a second hole 123; wherein, the first hole 122 is located on the second hole 123, and the opening size of the first hole 122 is larger than the opening size of the second hole 123.

[0067] In some embodiments, the process of forming the wiring layer and vias may include: etching an initial wiring layer downwards based on a first groove to expose an initial interlayer dielectric layer while forming the wiring layer; etching the initial interlayer dielectric layer and an initial etch stop layer to expose a device layer; and etching the initial device layer and an initial substrate to form vias.

[0068] It should be noted that after etching the initial wiring layer at the bottom of the first groove, a wiring layer is formed. After etching the initial interlayer dielectric layer, the initial etch stop layer, the initial device layer and the initial substrate, the remaining initial interlayer dielectric layer, the initial etch stop layer, the initial device layer and the initial substrate are respectively formed into interlayer dielectric layer 121, etch stop layer, device layer and substrate 11.

[0069] Step S103: Fill the through hole with conductive material to form a conductive pillar that communicates with the wiring layer.

[0070] Here, the conductive pillar is called a through-silicon via (TSV). Conductive pillars are used to achieve electrical connections between two wafers after wafer bonding. The conductive material can be tungsten, aluminum, or copper, etc. Different conductive materials require different deposition processes. For example, tungsten is used with Chemical Vapor Deposition (CVD); aluminum is used with both CVD and PVD; and copper is used with Chemical Plating (CP).

[0071] In this embodiment of the disclosure, the wiring layer is mainly used to supply power to the inside of the chip.

[0072] In practical applications, due to the small diameter, large depth, and high depth-to-width ratio of through holes, plating voids may form when copper is plated using a uniform electroplating process. Therefore, a "bottom-up" electroplating process can be adopted, which uses special electroplating accelerators and inhibitors to accelerate the deposition rate inside the through hole and inhibit the deposition rate on the outer surface of the through hole. By adjusting the ratio of accelerators and inhibitors, the two can be balanced to prevent the formation of plating voids.

[0073] It should be noted that both the wiring layer and the conductive pillars are conductive materials. Since the wiring layer surrounds and is in physical contact with the conductive pillars, the two are connected.

[0074] refer to Figure 5 Conductive material is filled into the through-hole 20 to form a conductive pillar 30 communicating with the wiring layer 13. In some embodiments, the diameter of the conductive pillar 30 ranges from 3 to 15 μm, and the length of the conductive pillar 30 ranges from 30 to 100 μm.

[0075] In practical applications, after the conductive pillars are formed, excess conductive material will be deposited on the upper surface of the interlayer dielectric layer, causing some protrusions and grooves to form on the upper surface of the interlayer dielectric layer. The excess conductive material can be removed by etching, grinding, polishing and other processes.

[0076] In this embodiment, firstly, an initial substrate is provided; the initial substrate includes at least an initial subsequent process layer and an initial wiring layer located on the initial subsequent process layer and having a first groove; secondly, the initial substrate is etched along the first groove to form the wiring layer and vias; finally, conductive material is filled into the vias to form conductive pillars communicating with the wiring layer. In this way, on the one hand, when etching the initial substrate to form vias, the initial wiring layer can be used directly as a mask, eliminating the need to form an additional mask layer, thereby simplifying the process and reducing costs; on the other hand, since the size of the conductive pillar is limited by the width of the wiring layer when forming it, the end area of ​​the formed conductive pillar is small, thereby reducing the parasitic capacitance between the conductive pillar and the metal interconnect layer in the subsequent process layer.

[0077] During implementation, the initial wiring layer can be made of aluminum, which is easy to etch when forming vias, thus having less impact on the flatness of the subsequent wiring layer, resulting in a wiring layer with better flatness.

[0078] The conductive material in the conductive pillar can be copper, and the material of the initial wiring layer can be aluminum. In the subsequent bonding of the two chips, solder balls need to be formed in related technologies, but in the embodiments of this disclosure, solder balls do not need to be formed, so the bonding is better.

[0079] In some embodiments, copper can be deposited in the via to form a conductive pillar communicating with the wiring layer; alternatively, a seed layer can be formed in the via first, followed by copper electroplating to form the conductive pillar.

[0080] In some embodiments, the method for forming a semiconductor structure further includes, before filling the via with conductive material:

[0081] Step S104: An initial isolation layer and an initial barrier layer are formed sequentially in the through hole;

[0082] It should be noted that the initial isolation layer and initial barrier layer do not completely fill the vias. The initial isolation layer is used to prevent conductivity between the conductive material filled in subsequent processes and the substrate, thereby protecting the substrate from damage. The material of the initial isolation layer can be an oxide (e.g., silicon dioxide), a silicon nitride (e.g., silicon nitride), etc. The initial isolation layer can be formed using PECVD, thermal oxidation, or vacuum vapor deposition. Among these, PECVD has a high deposition rate, low process temperature, and strong film coverage, and is widely used for depositing isolation layer materials such as silicon dioxide and silicon nitride.

[0083] The initial barrier layer not only prevents the diffusion of conductive materials filled in subsequent processes, but also improves the adhesion strength of the seed layer. Common materials for the barrier layer include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium, vanadium nitride, niobium, or niobium nitride.

[0084] During implementation, suitable processes such as PVD, CVD, or Plasma Enhanced Magnetron Sputtering (PEMS) can be used to form the initial barrier layer. When depositing the initial isolation layer and initial barrier layer in the vias, initial isolation layers and initial barrier layers are also deposited on the wiring layers and interlayer dielectric layers.

[0085] Step S105: Irregulate the initial isolation layer and initial barrier layer located on the top sidewall of the via and the wiring layer to form the isolation layer and barrier layer; wherein the top surface of the isolation layer and barrier layer is lower than the top surface of the wiring layer.

[0086] Here, etching back the initial isolation layer and initial barrier layer located on the top sidewall of the via is to make the conductive pillars formed in subsequent processes conductive with the wiring layer. In practice, dry or wet etching processes can be used to etch back the initial isolation layer and initial barrier layer on the top sidewall and wiring layer. For example, the initial isolation layer and initial barrier layer located between 75 and 85 degrees (°) can be removed.

[0087] In some embodiments, the thickness of the insulating layer ranges from 0.2 to 0.5 μm; the thickness of the barrier layer ranges from 100 to 500 angstroms.

[0088] refer to Figure 6 The initial isolation layer and the initial barrier layer located on the top sidewall of the via and on the wiring layer 13 are etched back to form isolation layer 301 and barrier layer 302. It can be seen that the top surface of isolation layer 301 and barrier layer 302 is lower than the top surface of wiring layer 13.

[0089] Continue to refer to Figure 6A seed layer can be formed on the barrier layer, and a conductive layer 303 can be formed using an electroplating process. Thus, the conductive pillar 30, from the inside out, includes a conductive layer 303, a seed layer, a barrier layer 302, and an isolation layer 301. The seed layer serves to provide a connection for the subsequent formation of the conductive layer 303 in the via. The seed layer can be made of any conductive material, such as tungsten, cobalt, copper, aluminum, or any combination thereof. In practice, the method for forming the seed layer can be the same as the method for forming the barrier layer.

[0090] This disclosure provides a semiconductor structure, with reference to... Figure 5 or Figure 6 The semiconductor structure includes:

[0091] The substrate 40 includes at least a downstream process layer 12 and a wiring layer 13 located on the surface of the downstream process layer 12.

[0092] The conductive post 30 penetrates the substrate 40, and the wiring layer 13 includes a portion surrounding and physically in contact with the conductive post 30.

[0093] In some embodiments, the conductive post 30 includes, from the inside out, a conductive layer 303, a seed layer, a barrier layer 302, and an isolation layer 301; in some embodiments, the conductive post 30 may include, from the inside out, a conductive layer 303, a barrier layer 302, and an isolation layer 301; in some embodiments, the conductive post 30 may include only the conductive layer 303.

[0094] In some embodiments, the substrate 40 further includes a device layer and a substrate 11 penetrated by conductive pillars 30 located under the back-end process layer 12. The back-end process layer 12 includes metal interconnect layers M1, M2 and M3, vias V1 and V2, an initial interlayer dielectric layer 121 and an etch stop layer, etc.

[0095] In this embodiment, the conductive pillar is surrounded by a wiring layer, and the end area of ​​the conductive pillar is small, which can reduce the parasitic capacitance between the conductive pillar and the metal interconnect layer in the subsequent process layer.

[0096] In some embodiments, continue to refer to Figure 5 The subsequent process layer 12 includes a first hole 122 and a second hole 123; wherein, the first hole 122 is located on the second hole 123, and the opening size of the first hole 122 is larger than the opening size of the second hole 123; the top surface of the conductive post 30 is located between the top surface of the second hole 123 and the top surface of the wiring layer 13.

[0097] It should be noted that the opening size of the second hole 123 can be the same as the diameter of the conductive post.

[0098] In some embodiments, the top surface of the conductive post 30 may be flush with the top surface of the wiring layer 13.

[0099] In some embodiments, continue to refer to Figure 5 The surface of the second hole 123 has a partial wiring layer 13, and the thickness of the partial wiring layer 13 in the direction of the sidewall of the second hole 123 gradually decreases with increasing depth.

[0100] In some embodiments, reference Figure 6 The portion of the wiring layer 13 surrounding the conductive pillar 30 includes a first opening B1 and a second opening B2. The first opening B1 is on the second opening B2. The opening size of the first opening B1 is larger than the opening size of the second opening B2; or the tilt angle of the first opening B1 is larger than the tilt angle of the second opening B2; or the opening size of the first opening B1 is larger than the opening size of the second opening B2 and the tilt angle of the first opening B1 is larger than the tilt angle of the second opening B2.

[0101] This disclosure also provides a method for forming a stacked structure, see embodiments thereof. Figure 7 The method includes steps S201 and S202, wherein:

[0102] Step S201: Provide a first chip and a second chip; wherein at least one of the first chip and the second chip is formed using the forming method in any of the above embodiments;

[0103] Here, the first chip and the second chip can be the same chip or different chips. The first chip and the second chip can be memory chips or other chips formed after the wafers manufactured by the chip manufacturer are diced. The side of the chip with circuits or devices is called the front side of the chip, that is, the functional side of the chip, and its opposite side is called the back side of the chip.

[0104] Step S202: Bond the first chip and the second chip together.

[0105] Here, the first and second chips can be bonded together using conductive pillars, eliminating the need for solder balls. This simplifies the process and allows for a thinner stacked structure. In implementation, face-to-face, face-to-back, or back-to-back bonding can be used; the bonding method can be suitable, such as thermal bonding or hybrid bonding.

[0106] In this embodiment, since at least one of the first and second chips is formed using the formation method described in this embodiment, when the first and second chips are bonded, a pathway is formed between the conductive pillars, wiring layers, and bonding surfaces of the first chip and the conductive pillars, wiring layers, and bonding surfaces of the second chip. Compared to pathways in related technologies (conductive pillars, metal interconnect layer M1, other metal interconnect layers, wiring layers, and bonding surfaces in the first chip and conductive pillars, metal interconnect layer M1, other metal interconnect layers, wiring layers, and bonding surfaces in the second chip), the pathways in this embodiment have lower resistance and parasitic capacitance. In other words, the method in this embodiment can reduce the parasitic capacitance and resistance of multi-chip stacked structures. Furthermore, since the end area of ​​the conductive pillars is smaller, the parasitic capacitance between the conductive pillars and the metal interconnect layers in the subsequent process layers can be reduced.

[0107] In some embodiments, a third chip may be formed on the front side of the first chip, and / or a fourth chip may be formed on the back side of the second chip, thereby forming a stacked structure comprising multiple chips.

[0108] The structures of the first chip and the second chip in this embodiment can be understood with reference to the above-described semiconductor structure. The structures of the first chip and the second chip have the same technical effects as the above-described semiconductor structure, and will not be described again here.

[0109] This disclosure also provides a stacking structure, see reference. Figure 8 It includes: a first chip 100 and a second chip 200, wherein at least one of the first chip and the second chip is formed using the forming method in any of the above embodiments;

[0110] The first chip 100 and / or the second chip 200 include a substrate 40 and conductive pillars 30; the substrate 40 includes at least a back-end processing layer 12 and a wiring layer 13 located on the surface of the back-end processing layer 12; the conductive pillars 30 penetrate the substrate 40, and the wiring layer 13 includes a portion surrounding and physically contacting the conductive pillars 30; the first chip 100 and the second chip 200 are bonded through the conductive pillars 30.

[0111] In this embodiment, the chips in the stacked structure are formed using the above-described forming method. As a result, the resulting stacked structure has lower parasitic capacitance and resistance. Furthermore, since the two chips are bonded together by conductive pillars, solder balls are not required, resulting in a thinner stacked structure. In addition, since the size of the conductive pillars is limited by the width of the wiring layer, the end area of ​​the formed conductive pillars is smaller, thereby reducing the parasitic capacitance between the conductive pillars and the metal interconnect layer in the subsequent process layer.

[0112] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled or directly coupled to each other.

[0113] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0114] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0115] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide the initial base; The initial substrate includes at least an initial downstream process layer and an initial wiring layer located on the initial downstream process layer and having a first groove. The first groove of the initial wiring layer includes a first opening and a second opening. The first opening is on the second opening, and the opening size and / or tilt angle of the first opening is greater than that of the second opening. The initial substrate is etched along the first groove to form a wiring layer and vias; The through-hole is filled with conductive material to form a conductive pillar that communicates with the wiring layer.

2. The forming method according to claim 1, characterized in that, The thickness of a portion of the initial wiring layer at the bottom of the first groove is less than the thickness of a portion of the initial wiring layer on the initial subsequent process layer.

3. The forming method according to claim 1, characterized in that, The initial substrate also includes an initial device layer and an initial substrate located below the initial downstream process layer; Providing an initial substrate includes: Provide an initial substrate and form an initial device layer on the initial substrate; A metal interconnect layer, an initial etch stop layer, and an initial interlayer dielectric layer are sequentially formed on the initial device layer; The initial interlayer dielectric layer is etched down to the initial etch stop layer to form a second groove, thereby forming the initial subsequent process layer; The initial wiring layer is formed in the second groove and on the initial interlayer dielectric layer.

4. The forming method according to claim 3, characterized in that, The thickness of the initial wiring layer on the initial interlayer dielectric layer ranges from 5 to 7 micrometers; the thickness of the initial wiring layer on the second groove ranges from 0.3 to 0.6 micrometers.

5. The forming method according to claim 3, characterized in that, Etching the initial substrate along the first groove to form a wiring layer and vias includes: Based on the first groove, the initial wiring layer is etched downwards to expose the initial interlayer dielectric layer and form the wiring layer at the same time. The initial interlayer dielectric layer and the etching stop layer are etched to expose the initial device layer; The initial device layer and the initial substrate are etched to form the via.

6. The method according to any one of claims 1 to 5, characterized in that, Before filling the through-hole with conductive material, the method further includes: An initial isolation layer and an initial barrier layer are formed sequentially in the through-hole; The initial isolation layer and the initial barrier layer located on the top sidewall of the through hole and on the wiring layer are etched back to form an isolation layer and a barrier layer; The top surfaces of the isolation layer and the barrier layer are lower than the top surface of the wiring layer.

7. The method according to claim 6, characterized in that, The thickness of the isolation layer ranges from 0.2 to 0.5 micrometers; the thickness of the barrier layer ranges from 100 to 500 angstroms.

8. The forming method according to any one of claims 1 to 5, characterized in that, The width of the first groove ranges from 5 to 10 micrometers; the depth of the first groove ranges from 3 to 5 micrometers. The diameter of the conductive post ranges from 3 to 15 micrometers; the length of the conductive post ranges from 30 to 100 micrometers.

9. A semiconductor structure, characterized in that, include: The substrate includes at least a downstream processing layer and a wiring layer located on the surface of the downstream processing layer; A conductive pillar extends through the substrate, and the wiring layer includes a portion surrounding and physically contacting the conductive pillar. The portion of the wiring layer surrounding the conductive pillar includes a first opening and a second opening, the first opening being on top of the second opening, and the opening size and / or tilt angle of the first opening being greater than that of the second opening.

10. The semiconductor structure according to claim 9, characterized in that, The subsequent process layer includes a first hole and a second hole, wherein the first hole is located on the second hole, and the opening size of the first hole is larger than the opening size of the second hole; the top surface of the conductive post is located between the top surface of the second hole and the top surface of the wiring layer.

11. The semiconductor structure according to claim 10, characterized in that, The second hole surface has a portion of the wiring layer, and the thickness of the portion of the wiring layer in the direction of the second hole sidewall gradually decreases with increasing depth.

12. A method for forming a stacked structure, characterized in that, include: A first chip and a second chip are provided; wherein at least one of the first chip and the second chip is formed using the forming method according to any one of claims 1 to 8; The first chip and the second chip are bonded together.

13. A stacked structure, characterized in that, include: A first chip and a second chip, wherein at least one of the first chip and the second chip is formed using the forming method according to any one of claims 1 to 8; The first chip and / or the second chip includes a substrate and conductive pillars; the substrate includes at least a back-end processing layer and a wiring layer located on the surface of the back-end processing layer; the conductive pillars penetrate the substrate, and the wiring layer includes a portion surrounding and physically contacting the conductive pillars; the first chip and the second chip are bonded through the conductive pillars.

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