Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package includes a package substrate, a semiconductor chip, and a plurality of bonding wires. The package substrate includes a connection pad. The semiconductor chip is disposed on the package substrate and includes a chip pad, a bonding pad, and a redistribution layer. The bonding pad is closer to an outer edge of the semiconductor chip than the chip pad. The redistribution layer is connected between the chip pad and the bonding pad. The bonding wires are connected in parallel between the connection pad and the bonding pad. By the above configuration, the inductive resistance of the circuit can be effectively reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor package and a manufacturing method thereof. BACKGROUND

[0002] In a semiconductor package, the use of lines, especially long lines, can cause power supply problems (e.g., insufficient current) due to the inductive reactance of the lines. SUMMARY

[0003] Accordingly, one object of the present disclosure is to provide a semiconductor package with stable power supply.

[0004] To achieve the above object, according to some embodiments of the present disclosure, a semiconductor package includes a package substrate, a first semiconductor chip, and a plurality of first bonding wires. The package substrate includes a first connection pad. The first semiconductor chip is disposed on the package substrate and includes a first chip pad, a first bonding pad, and a first redistribution layer. The first bonding pad is closer to an outer edge of the first semiconductor chip than the first chip pad. The first redistribution layer is connected between the first chip pad and the first bonding pad. The first bonding wires are connected in parallel between the first connection pad and the first bonding pad.

[0005] In one or more embodiments of the present disclosure, the first chip pad is a power pad or a ground pad, which serves as a power supply interface of the first semiconductor chip.

[0006] In one or more embodiments of the present disclosure, the first semiconductor chip further includes a second chip pad, which is electrically connected to the package substrate through a second bonding wire. The second chip pad is a data signal pad or an instruction or address signal pad.

[0007] In one or more embodiments of the present disclosure, the first semiconductor chip further includes a second bonding pad and a second redistribution layer connected between the second chip pad and the second bonding pad. The package substrate further includes a second connection pad. The second bonding wire is connected between the second connection pad and the second bonding pad, and the second bonding wire is the only conductive path between the second connection pad and the second bonding pad.

[0008] In one or more embodiments of the present disclosure, the cross-sectional area of one or more of the first bonding wires is greater than the cross-sectional area of the second bonding wire.

[0009] In one or more embodiments of the present disclosure, the plurality of first bonding wires includes a first wire and a second wire. The first wire and the second wire each have a first end and a second end. The first end of each wire contacts the first bonding pad of the first semiconductor chip, and the second end of each wire contacts the first connection pad of the package substrate.

[0010] In one or more embodiments of the disclosure, the first end of the first wire contacts the first end of the second wire.

[0011] In one or more embodiments of the disclosure, the second end of the first wire is separated from the second end of the second wire.

[0012] In one or more embodiments of the disclosure, the semiconductor package further includes a second semiconductor chip disposed on the first semiconductor chip. The first bond wire extends into a gap between the first semiconductor chip and the second semiconductor chip.

[0013] In one or more embodiments of the disclosure, the second semiconductor chip includes a chip pad, a bond pad, and a redistribution layer. The redistribution layer of the second semiconductor chip is connected between the chip pad of the second semiconductor chip and the bond pad of the second semiconductor chip. The semiconductor package further includes a plurality of second bond wires connected in parallel between the second connection pad of the package substrate and the bond pad of the second semiconductor chip. The chip pad of the second semiconductor chip is a power pad or a ground pad.

[0014] According to some embodiments of the disclosure, a method of manufacturing a semiconductor package includes providing a package substrate including a first connection pad; disposing a semiconductor chip on the package substrate, the semiconductor chip including a first chip pad, a first bond pad, and a first redistribution layer, wherein the first bond pad is closer to an outer edge of the semiconductor chip than the first chip pad, and the first redistribution layer is connected between the first chip pad and the first bond pad; and forming a plurality of first bond wires connected in parallel between the first connection pad of the package substrate and the first bond pad of the semiconductor chip.

[0015] In one or more embodiments of the disclosure, the first chip pad is a power pad or a ground pad as a power interface of the semiconductor chip.

[0016] In one or more embodiments of the disclosure, the semiconductor chip further includes a second chip pad, a second bond pad, and a second redistribution layer. The second redistribution layer is connected between the second chip pad and the second bond pad. The second chip pad is a data signal pad or an instruction or address signal pad. The method of manufacturing a semiconductor package further includes connecting the second bond pad and a second connection pad of the package substrate with a second bond wire, wherein the second bond wire is the only conductive path between the second connection pad and the second bond pad.

[0017] In one or more embodiments of the disclosure, a cross-sectional area of one or more of the first bond wires is greater than a cross-sectional area of the second bond wire.

[0018] In one or more embodiments of the present disclosure, the step of forming the first bonding wire includes: drawing a first wire from the first connection pad of the package substrate to the first bonding pad of the semiconductor chip; and drawing a second wire from a position of the first bonding pad, at which the first bonding pad is connected to the first wire, to the first connection pad of the package substrate.

[0019] In the semiconductor package of the present disclosure, the bonding pads of the semiconductor chip are connected to the connection pads of the package substrate via a plurality of parallel bonding wires, which configuration can effectively reduce the inductance of the lines (including the bonding wires and the redistribution layer).

[0020] It is to be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further explanation of the application claimed. BRIEF DESCRIPTION OF DRAWINGS

[0021] The embodiments described in detail below can be better understood when read in conjunction with the following drawings:

[0022] Figure 1 FIG. 1 is a top view showing a semiconductor package according to an embodiment of the present disclosure; and

[0023] Figure 2 FIG. 2 is a cross-sectional view of the semiconductor package shown in FIG. 1 along line 1-1'. Figure 1 The semiconductor package shown in FIG. 1 includes a package substrate 190 and one or more semiconductor chips 110, 120 stacked on the package substrate 190. In the embodiment shown, the semiconductor package 100 includes a first semiconductor chip 110 disposed above the package substrate 190 and a second semiconductor chip 120 disposed above the first semiconductor chip 110 with a gap G therebetween. DETAILED DESCRIPTION

[0024] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. The same or similar components are denoted by the same reference numerals throughout the drawings and the description.

[0025] Reference will now be made to Figure 1 and Figure 2 . Figure 1 FIG. 1 is a top view showing a semiconductor package 100 according to an embodiment of the present disclosure. Figure 2 FIG. 2 is a cross-sectional view of the semiconductor package 100 shown in FIG. 1 along line 1-1'. Figure 1 The semiconductor package 100 shown in FIG. 1 includes a package substrate 190 and one or more semiconductor chips 110, 120 stacked on the package substrate 190. In the embodiment shown, the semiconductor package 100 includes a first semiconductor chip 110 disposed above the package substrate 190 and a second semiconductor chip 120 disposed above the first semiconductor chip 110 with a gap G therebetween.

[0026] In some embodiments, the semiconductor package 100 is a memory package, and the first semiconductor chip 110 and the second semiconductor chip 120 comprise dynamic random access memory (DRAM) chips. In some embodiments, the package substrate 190 is a copper clad laminate (CCL).

[0027] As shown in FIG. 1, the semiconductor package 100 further comprises a package substrate 190. The first semiconductor chip 110 is fixed on the package substrate 190. The second semiconductor chip 120 is fixed on the first semiconductor chip 110. Figure 1 With Figure 2 As shown in FIG. 1, in some embodiments, the semiconductor package 100 further comprises an adhesive layer 130 disposed between the first semiconductor chip 110 and the second semiconductor chip 120. The second semiconductor chip 120 is fixed on the first semiconductor chip 110 through the adhesive layer 130. In some embodiments, the semiconductor package 100 can comprise another adhesive layer (not shown), and the first semiconductor chip 110 can be fixed on the package substrate 190 through the other adhesive layer.

[0028] As shown in FIG. 1, the semiconductor package 100 further comprises a package substrate 190. The first semiconductor chip 110 is fixed on the package substrate 190. The second semiconductor chip 120 is fixed on the first semiconductor chip 110. Figure 1 With Figure 2 As shown in FIG. 1, the second semiconductor chip 120 has a lower surface 120L and an upper surface 120U opposite to the lower surface 120L. The lower surface 120L faces the first semiconductor chip 110, and the upper surface 120U is away from the first semiconductor chip 110. The second semiconductor chip 120 comprises a plurality of groups of chip pads 122, bonding pads 124, and a redistribution layer 126. The chip pads 122, the bonding pads 124, and the redistribution layer 126 are disposed on the upper surface 120U of the second semiconductor chip 120, in other words, the upper surface 120U of the second semiconductor chip 120 is an active surface of the second semiconductor chip 120. In this configuration, the second semiconductor chip 120 is referred to as a “face up” chip.

[0029] As shown in FIG. 1, the semiconductor package 100 further comprises a package substrate 190. The first semiconductor chip 110 is fixed on the package substrate 190. The second semiconductor chip 120 is fixed on the first semiconductor chip 110. Figure 1 With Figure 2 As shown in FIG. 1, the chip pads 122 are disposed near the center of the upper surface 120U, and the bonding pads 124 are disposed near the edges of the upper surface 120U. In other words, the bonding pads 124 are closer to the outer edge of the second semiconductor chip 120 than the chip pads 122. The redistribution layer 126 is connected between the chip pads 122 and the bonding pads 124. Specifically, the redistribution layer 126 has opposite ends contacting the chip pads 122 and the bonding pads 124, respectively. The chip pads 122 and the bonding pads 124 are electrically connected via the redistribution layer 126.

[0030] As shown in FIG. 1, the semiconductor package 100 further comprises a package substrate 190. The first semiconductor chip 110 is fixed on the package substrate 190. The second semiconductor chip 120 is fixed on the first semiconductor chip 110. Figure 1 With Figure 2As shown, the first semiconductor chip 110 has a lower surface 110L and an upper surface 110U, with the upper surface 110U opposite to the lower surface 110L. The lower surface 110L faces the packaging substrate 190, while the upper surface 110U is away from the packaging substrate 190. The first semiconductor chip 110 includes multiple sets of chip pads 112, bonding pads 114, and redistribution layers 116. The chip pads 112, bonding pads 114, and redistribution layers 116 are disposed on the upper surface 110U of the first semiconductor chip 110; in other words, the upper surface 110U of the first semiconductor chip 110 is the active surface of the first semiconductor chip 110. In this configuration, the first semiconductor chip 110 is referred to as "facing upwards".

[0031] like Figure 1 and Figure 2 As shown, chip pad 112 is disposed near the center of the upper surface 110U, while bonding pad 114 is disposed near the edge of the upper surface 110U. In other words, bonding pad 114 is closer to the outer edge of the first semiconductor chip 110 than chip pad 112. A redistribution layer 116 connects chip pad 112 and bonding pad 114. Specifically, redistribution layer 116 has two opposing ends that contact chip pad 112 and bonding pad 114, respectively. Chip pad 112 and bonding pad 114 are electrically connected via redistribution layer 116.

[0032] like Figure 1 and Figure 2 As shown, in some embodiments, the chip pads 122 of the second semiconductor chip 120 are arranged in one or more rows near the center of the upper surface 120U. In some embodiments, the bonding pads 124 of the second semiconductor chip 120 are arranged in one or more rows near the edge of the upper surface 120U. Similarly, the chip pads 112 of the first semiconductor chip 110 may be arranged in one or more rows near the center of the upper surface 110U, and the bonding pads 114 of the first semiconductor chip 110 may be arranged in one or more rows near the edge of the upper surface 110U.

[0033] like Figure 1 and Figure 2 As shown, in some embodiments, the chip pad 122 of the second semiconductor chip 120 includes one or more power pads VDD, one or more ground pads GND, one or more data signal pads DQ, and one or more command / address signal pads CA. The power pads VDD and GND serve as the power supply interface for the second semiconductor chip 120, the data signal pads DQ are used to transmit data signals, and the command / address signal pads CA are used to transmit command / address signals.

[0034] like Figure 1 andFigure 2 As shown, in some embodiments, the bonding pads 124 of the second semiconductor chip 120 include one or more power bonding pads BV, one or more ground bonding pads BG, one or more data bonding pads BD, and one or more instruction or address bonding pads BC. Each power bonding pad BV is electrically connected to one of the power pads VDD via the redistribution layer 126, each ground bonding pad BG is electrically connected to one of the ground pads GND via the redistribution layer 126, each data bonding pad BD is electrically connected to one of the data signal pads DQ via the redistribution layer 126, and each instruction or address bonding pad BC is electrically connected to one of the instruction or address signal pads CA via the redistribution layer 126.

[0035] Similarly, the chip pad 112 of the first semiconductor chip 110 may include one or more power pads VDD, one or more ground pads GND, one or more data signal pads DQ, and one or more instruction or address signal pads CA. The bonding pad 114 of the first semiconductor chip 110 may include one or more power bonding pads BV, one or more ground bonding pads BG, one or more data bonding pads BD, and one or more instruction or address bonding pads BC. The configuration or connection relationship of the power pads VDD, GND, DQ, CA, BV, BG, BD, and BC of the first semiconductor chip 110 may be similar to, the same as, or substantially the same as the corresponding elements of the second semiconductor chip 120.

[0036] like Figure 1 and Figure 2 As shown, the package substrate 190 includes a plurality of upper connection pads 192. The upper connection pads 192 are disposed on the upper surface 190U of the package substrate 190 and arranged in one or more rows on one side of the first semiconductor chip 110. The semiconductor package 100 further includes a plurality of bonding leads 140, each bonding pad 114, 124 being connected to one of the upper connection pads 192 of the package substrate 190 via at least one bonding lead 140. The bonding leads 140 connecting the bonding pads 114 of the first semiconductor chip 110 may extend into the gap G between the first semiconductor chip 110 and the second semiconductor chip 120. In some embodiments, the bonding leads 140 comprise gold, silver, other suitable conductive materials, or any combination of the above materials.

[0037] like Figure 1 and Figure 2As shown, at least one of the bonding pads 114 and 124 is connected to the upper connecting pad 192 via two or more bonding leads 140 connected in parallel. In other words, the two or more bonding leads 140 form a parallel circuit between the bonding pad 114 or 124 and the corresponding upper connecting pad 192. In the illustrated embodiment, the bonding lead 140 includes a first lead 141 and a second lead 142. The first lead 141 and the second lead 142 each have a first end E1 and a second end E2. The first end E1 contacts one of the bonding pads 114 or 124, and the second end E2 contacts one of the upper connecting pads 192. Connecting two or more bonding leads 140 in parallel between the bonding pad 114 or 124 and the upper connecting pad 192 can effectively reduce the inductive reactance of the circuit (including the bonding leads 140 and the redistribution layer 116 or 126).

[0038] like Figure 1 and Figure 2 As shown, in some embodiments, at least one of the power connection pad BV and the ground connection pad BG is connected to one of the upper connection pads 192 via two or more connection leads 140 connected in parallel. As described above, using two or more connection leads 140 connected in parallel can effectively reduce the inductive reactance of the line. Therefore, applying this method to power connections that typically require a large current can enable the first semiconductor chip 110 and the second semiconductor chip 120 to obtain a stable power supply. In some embodiments, each power connection pad BV and the ground connection pad BG is connected to one of the upper connection pads 192 via two or more connection leads 140 connected in parallel.

[0039] like Figure 1 and Figure 2 As shown, in some embodiments, at least one of the data signal pad DQ and the command or address signal pad CA is electrically connected to the package substrate 190 via exactly one bonding lead 140, since the current required for the transmission of data or command / address signals is typically small. In some embodiments, each data signal pad DQ and each command or address signal pad CA is electrically connected to the package substrate 190 via exactly one bonding lead 140.

[0040] like Figure 1 and Figure 2 As shown, in some embodiments, the bonding lead 140 may include a third lead 143 having a first end and a second end opposite to the first end. The first end of the third lead 143 contacts one of the data bonding pads BD or instruction or address bonding pads BC, and the second end of the third lead 143 contacts one of the upper connection pads 192 of the package substrate 190. The third lead 143 is the only conductive path between the data bonding pad BD or instruction or address bonding pad BC and the corresponding upper connection pad 192.

[0041] As shown in FIG. 1A, in some embodiments, the cross-sectional area of at least one of the first wire 141 and the second wire 142 (i.e., the wire connecting the power bonding pad BV or the ground bonding pad BG) is greater than the cross-sectional area of the third wire 143 (i.e., the wire connecting the data bonding pad BD or the command or address bonding pad BC). For example, the diameter of at least one of the first wire 141 and the second wire 142 is greater than the diameter of the third wire 143. By such a configuration, the inductive reactance of the power line can be further reduced. Figure 1 Figure 2 As shown in FIG. 1A, in some embodiments, the cross-sectional area of the redistribution layer 116 or 126 connecting the power bonding pad BV or the ground bonding pad BG is greater than the cross-sectional area of the redistribution layer 116 or 126 connecting the data bonding pad BD or the command or address bonding pad BC. In some embodiments, the width of the redistribution layer 116 or 126 connecting the power bonding pad BV or the ground bonding pad BG is greater than the width of the redistribution layer 116 or 126 connecting the data bonding pad BD or the command or address bonding pad BC.

[0042] As shown in FIG. 1A, in some embodiments, the cross-sectional area of at least one of the first wire 141 and the second wire 142 (i.e., the wire connecting the power bonding pad BV or the ground bonding pad BG) is greater than the cross-sectional area of the third wire 143 (i.e., the wire connecting the data bonding pad BD or the command or address bonding pad BC). For example, the diameter of at least one of the first wire 141 and the second wire 142 is greater than the diameter of the third wire 143. By such a configuration, the inductive reactance of the power line can be further reduced.

[0043] As shown in FIG. 1A, in some embodiments, the cross-sectional area of at least one of the first wire 141 and the second wire 142 (i.e., the wire connecting the power bonding pad BV or the ground bonding pad BG) is greater than the cross-sectional area of the third wire 143 (i.e., the wire connecting the data bonding pad BD or the command or address bonding pad BC). For example, the diameter of at least one of the first wire 141 and the second wire 142 is greater than the diameter of the third wire 143. By such a configuration, the inductive reactance of the power line can be further reduced. Figure 1 Figure 2 As shown in FIG. 1A, in some embodiments, the first end E1 of the first wire 141 contacts the first end E1 of the second wire 142. In some embodiments, the second end E2 of the first wire 141 is separated from the second end E2 of the second wire 142. In some embodiments, the first wire 141 and the second wire 142 are formed in the following manner: the first wire 141 is pulled from the upper connection pad 192 to the bonding pad 114 or 124, and then the second wire 142 is pulled from the position of the bonding pad 114 or 124 where the bonding pad 114 or 124 is connected to the first wire 141 to the upper connection pad 192.

[0044] As shown in FIG. 1A, in some embodiments, the package substrate 190 further comprises a plurality of lower connection pads 194 and a plurality of internal lines 196. The lower connection pads 194 are disposed on the lower surface 190L of the package substrate 190. The internal lines 196 extend through the package substrate 190 and are connected between the upper connection pads 192 and the lower connection pads 194. In some embodiments, the internal lines 196 can comprise conductive lines, conductive vias, or a combination thereof. Figure 1 Figure 2 As shown in FIG. 1A, in some embodiments, the package substrate 190 further comprises a plurality of lower connection pads 194 and a plurality of internal lines 196. The lower connection pads 194 are disposed on the lower surface 190L of the package substrate 190. The internal lines 196 extend through the package substrate 190 and are connected between the upper connection pads 192 and the lower connection pads 194. In some embodiments, the internal lines 196 can comprise conductive lines, conductive vias, or a combination thereof.

[0045] As shown in FIG. 1A, in some embodiments, the package substrate 190 further comprises a plurality of lower connection pads 194 and a plurality of internal lines 196. The lower connection pads 194 are disposed on the lower surface 190L of the package substrate 190. The internal lines 196 extend through the package substrate 190 and are connected between the upper connection pads 192 and the lower connection pads 194. In some embodiments, the internal lines 196 can comprise conductive lines, conductive vias, or a combination thereof. Figure 1 Figure 2 ​​​​As shown, in some embodiments, the semiconductor package 100 further includes a plurality of external connection terminals 150 disposed under the package substrate 190, each of the external connection terminals 150 disposed on and contacting one of the lower connection pads 194. In some embodiments, the external connection terminals 150 can include solder balls, solder bumps, or a combination thereof.

[0046] As shown, in some embodiments, the semiconductor package 100 further includes a molding compound 160 disposed on the package substrate 190 and covering the first semiconductor chip 110, the second semiconductor chip 120, and the bonding wires 140. Specifically, the molding compound 160 covers the upper surface 120U of the second semiconductor chip 120, the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120, and the upper surface 190U of the package substrate 190. Figure 1 Figure 2 As shown, in some embodiments, the semiconductor package 100 further includes a plurality of external connection terminals 150 disposed under the package substrate 190, each of the external connection terminals 150 disposed on and contacting one of the lower connection pads 194. In some embodiments, the external connection terminals 150 can include solder balls, solder bumps, or a combination thereof.

[0047] Next, referring to FIG. 2, a method of manufacturing the semiconductor package 100 is introduced. Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure A method of manufacturing the semiconductor package 100 is introduced.

[0048] The method of manufacturing the semiconductor package 100 starts from step SI, which includes providing a package substrate 190 including upper connection pads 192.

[0049] The method of manufacturing the semiconductor package 100 proceeds to step S3, which includes disposing a first semiconductor chip 110 on the package substrate 190, the first semiconductor chip 110 including chip pads 112, bonding pads 114, and a redistribution layer 116 connecting between the chip pads 112 and the bonding pads 114.

[0050] In some embodiments, step S3 includes fixing the first semiconductor chip 110 to the upper surface 190U of the package substrate 190 using an adhesive layer (not shown).

[0051] The method of manufacturing the semiconductor package 100 proceeds to step S5, which includes forming a plurality of bonding wires 140 connecting between one of the upper connection pads 192 of the package substrate 190 and the bonding pads 114 of the first semiconductor chip 110 in a parallel manner. In some embodiments, the bonding wires 140 are formed by ball bonding.

[0052] ​​In some embodiments, step S5 comprises: pulling the first wire 141 from the upper connection pad 192 of the package substrate 190 to the bonding pad 114, and then pulling the second wire 142 from a position of the bonding pad 114 to the upper connection pad 192, the position being where the bonding pad 114 is connected with the first wire 141. In some embodiments, the chip pad 112 to which the first wire 141 and the second wire 142 are coupled is a power pad VDD or a ground pad GND.

[0053] In some embodiments, the method of manufacturing the semiconductor package 100 further comprises: connecting a data bonding pad BD or an instruction or address bonding pad BC of the first semiconductor chip 110 to one of the upper connection pads 192 of the package substrate 190 by using a third wire 143.

[0054] In some embodiments, the method of manufacturing the semiconductor package 100 further comprises: disposing a second semiconductor chip 120 on the first semiconductor chip 110 (e.g., fixing the second semiconductor chip 120 on the upper surface 110U of the first semiconductor chip 110 by using the adhesive layer 130); and forming a plurality of bonding wires 140 connected in parallel between one of the upper connection pads 192 of the package substrate 190 and the bonding pad 124 of the second semiconductor chip 120. In some embodiments, the method of manufacturing the semiconductor package 100 further comprises: disposing a molding compound 160 on the package substrate 190, the molding compound 160 covering the first semiconductor chip 110, the second semiconductor chip 120, and the bonding wires 140.

[0055] In the semiconductor package of the present disclosure, the bonding pads of the semiconductor chips are connected to the connection pads of the package substrate via a plurality of parallel bonding wires, which can effectively reduce the inductance of the circuitry (including the bonding wires and the redistribution layer).

[0056] Although the present disclosure has been described in detail with particular references to certain illustrative embodiments thereof, other embodiments will be obvious to those skilled in the art. Accordingly, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0057] Obviously, many modifications and changes can be made to the present disclosure by those skilled in the art without departing from the scope or spirit of the present disclosure. Accordingly, the present disclosure is intended to embrace all modifications and changes that fall within the scope of the appended claims.

[0058]

List of Symbols

[0059] 100: semiconductor package

[0060] 110: first semiconductor chip

[0061] 110L, 120L, 190L: lower surface

[0062] 110U, 120U, 190U: upper surface

[0063] 112, 122: chip pad

[0064] 114, 124: bonding pad

[0065] 116, 126: redistribution layer

[0066] 120: second semiconductor chip

[0067] 130: adhesive layer

[0068] 140: bonding wire

[0069] 141: first wire

[0070] 142: second wire

[0071] 143: third wire

[0072] 150: external connection terminal

[0073] 160: molding compound

[0074] 190: package substrate

[0075] 192: upper connection pad

[0076] 194: lower connection pad

[0077] 196: internal line

[0078] BC: command or address bonding pad

[0079] BD: data bonding pad

[0080] BG: ground bonding pad

[0081] BV: power bonding pad

[0082] CA: command or address signal pad

[0083] DQ: data signal pad

[0084] E1: first end

[0085] E2: second end

[0086] G: gap

[0087] GND: ground pad

[0088] VDD: power pad

Claims

1. A semiconductor package, characterized by, Comprising: a package substrate comprising a first connection pad and a second connection pad; a first semiconductor chip disposed on the package substrate and comprising a first chip pad, a first bond pad, and a first redistribution layer, wherein the first bond pad is closer to an outer edge of the first semiconductor chip than the first chip pad, the first redistribution layer is connected between the first chip pad and the first bond pad, wherein the first chip pad is a power pad or a ground pad, the power pad or the ground pad serves as a power interface of the first semiconductor chip; and a plurality of first bond wires connected in parallel between the first connection pad and the first bond pad; wherein the first semiconductor chip further comprises a second chip pad, a second bond pad, and a second redistribution layer connected between the second chip pad and the second bond pad, the semiconductor package further comprises a second bond wire connected between the second connection pad and the second bond pad, and the second bond wire is the only conductive path between the second connection pad and the second bond pad, wherein the second chip pad is a data signal pad or an instruction or address signal pad.

2. The semiconductor package of claim 1, wherein, A cross-sectional area of one or more of the first bond wires is greater than a cross-sectional area of the second bond wire.

3. The semiconductor package of claim 1, wherein, The first bond wires comprise a first wire and a second wire, the first wire and the second wire each have a first end and a second end, wherein the first end contacts the first bond pad of the first semiconductor chip, and the second end contacts the first connection pad of the package substrate.

4. The semiconductor package of claim 3, wherein, The first end of the first wire contacts the first end of the second wire.

5. The semiconductor package of claim 3, wherein, The second end of the first wire is separate from the second end of the second wire.

6. The semiconductor package of claim 1, wherein, Further comprising a second semiconductor chip disposed on the first semiconductor chip, wherein the first bond wires extend into a gap between the first semiconductor chip and the second semiconductor chip.

7. The semiconductor package of claim 6, wherein, The second semiconductor chip comprises a chip pad, a bond pad, and a redistribution layer, the redistribution layer of the second semiconductor chip is connected between the chip pad of the second semiconductor chip and the bond pad of the second semiconductor chip, wherein the semiconductor package further comprises a plurality of third bond wires connected in parallel between a third connection pad of the package substrate and the bond pad of the second semiconductor chip, wherein the chip pad of the second semiconductor chip is a power pad or a ground pad.

8. A method of manufacturing a semiconductor package, characterized by, Comprising: providing a package substrate, the package substrate comprising a first connection pad and a second connection pad; A semiconductor chip is disposed on the packaging substrate, the semiconductor chip including a first chip pad, a first bonding pad, and a first redistribution layer, wherein the first bonding pad is closer to an outer edge of the semiconductor chip than the first chip pad, the first redistribution layer is connected between the first chip pad and the first bonding pad, the first chip pad is a power pad or a ground pad, the power pad or the ground pad serves as a power supply interface of the semiconductor chip, the semiconductor chip further includes a second chip pad, a second bonding pad, and a second redistribution layer, the second redistribution layer is connected between the second chip pad and the second bonding pad, the second chip pad is a data signal pad or an instruction or address signal pad; a plurality of first bonding wires are formed, the first bonding wires are connected in parallel between the first connection pads of the packaging substrate and the first bonding pads of the semiconductor chip; and a second bonding wire is used to connect the second bonding pads of the semiconductor chip and the second connection pads of the packaging substrate, wherein the second bonding wire is the only conductive path between the second connection pads and the second bonding pads.

9. The method of manufacturing a semiconductor package according to claim 8, wherein The cross-sectional area of one or more of the first bonding wires is greater than the cross-sectional area of the second bonding wire.

10. The method of manufacturing a semiconductor package according to claim 8, wherein The formation of the first bonding wires includes: a first wire is drawn from the first connection pads of the packaging substrate to the first bonding pads of the semiconductor chip; and a second wire is drawn from the position of the first bonding pads to the first connection pads of the packaging substrate, wherein the position is where the first bonding pads are connected to the first wire.

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