A semiconductor structure and wiring method thereof and semiconductor memory

Abstract

The disclosed embodiment provides a semiconductor structure and a wiring method thereof and a semiconductor memory, wherein the semiconductor structure includes: a plurality of wirings, wherein the wirings include a first wiring, a second wiring, and a third wiring, wherein the first wiring has the same properties as the second wiring, and the third wiring has different properties from the first wiring; the first wiring and the second wiring are respectively formed in different metal layers, and the orthographic projection of the first wiring and the orthographic projection of the second wiring at least partially cross or partially overlap; the third wiring or the orthographic projection of the third wiring is located on one side of the first wiring. In this way, not only the distance between the wirings can be reduced, but also the coupling crosstalk between different metal layers can be reduced, thereby saving layout space.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a wiring method thereof, and a semiconductor memory. Background Art

[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements for data transmission speed when manufacturing and using computers and other equipment. In order to obtain faster data transmission speed, a series of devices such as memory that can transmit data at double data rate (DDR) have emerged.

[0003] The memory can have multiple groups of data paths, and different groups of data paths will be coupled with each other, which may cause inaccurate data transmission. Usually, the data paths that affect each other are wired to avoid mutual coupling by increasing the spatial distance, but this will increase the layout space requirements. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor structure, a wiring method thereof, and a semiconductor memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, comprising: a plurality of wirings, the wirings comprising a first wiring, a second wiring, and a third wiring, the first wiring having the same property as the second wiring, and the third wiring having a different property from the first wiring;

[0006] The first wiring and the second wiring are respectively formed in different metal layers, and an orthographic projection of the first wiring and an orthographic projection of the second wiring at least partially cross or partially overlap;

[0007] The third wiring or an orthographic projection of the third wiring is located on one side of the first wiring.

[0008] In some embodiments, the attribute includes a signal flow direction; wherein:

[0009] The signal flow directions of the first wiring and the second wiring are both in the first direction, and the signal flow direction of the third wiring is in the second direction;

[0010] The first direction and the second direction are opposite to each other.

[0011] In some embodiments, the type of the wiring includes at least one of the following: a data line, a signal line, and a power line.

[0012] In some embodiments, when the type of the wiring is a data line, the attribute further includes a data type; wherein:

[0013] The data types transmitted by the first wiring and the second wiring are both first values, and the data type transmitted by the third wiring is a second value;

[0014] The first value is one of 0 and 1, and the second value is the other of 0 and 1.

[0015] In some embodiments, the semiconductor structure further comprises an isolation line, wherein:

[0016] The first wiring and the third wiring are located in the same metal layer, and the isolation track is arranged between the first wiring and the third wiring.

[0017] In some embodiments, the second wiring is located above the first wiring, wherein

[0018] The orthographic projection of the second wiring completely overlaps with the orthographic projection of the first wiring; or,

[0019] The orthographic projection of the second wiring partially overlaps with the orthographic projection of the first wiring; or,

[0020] The orthographic projection of the second wiring is located in a spacing region between adjacent first wirings.

[0021] In some embodiments, the first wiring and the second wiring both have a first arrangement direction, the orthographic projection of the center line of the second wiring coincides with the center line of the spacing area between adjacent first wirings, and the width of the second wiring in the first arrangement direction is greater than the width of the spacing area in the first arrangement direction.

[0022] In some embodiments, the wiring further includes a fourth wiring;

[0023] The fourth wiring has the same property as the third wiring, the fourth wiring and the third wiring are respectively formed in different metal layers, and the orthographic projection of the fourth wiring and the orthographic projection of the third wiring at least partially intersect or partially overlap;

[0024] The fourth wiring has a different property from that of the second wiring, and the fourth wiring or an orthographic projection of the fourth wiring is located on one side of the second wiring.

[0025] In some embodiments, the first wiring includes a first wiring portion and a second wiring portion, and the second wiring includes a third wiring portion and a fourth wiring portion, wherein:

[0026] The first wiring portion and the second wiring portion are respectively formed in different metal layers, and an orthographic projection of the first wiring portion and an orthographic projection of the second wiring portion at least partially intersect or partially overlap;

[0027] The third wiring portion and the fourth wiring portion are respectively formed in different metal layers, and an orthographic projection of the third wiring portion and an orthographic projection of the fourth wiring portion at least partially intersect or partially overlap.

[0028] In a second aspect, an embodiment of the present disclosure provides a wiring method for a semiconductor structure, the method comprising:

[0029] forming a first wiring;

[0030] forming a second wiring having the same properties as the first wiring, wherein the first wiring and the second wiring are respectively formed in different metal layers, and an orthographic projection of the first wiring and an orthographic projection of the second wiring at least partially intersect or partially overlap;

[0031] A third wiring having a different property from that of the first wiring is formed, and the third wiring or an orthographic projection of the third wiring is located on one side of the first wiring.

[0032] In some embodiments, the method further comprises:

[0033] forming a fourth wiring having the same property as the third wiring;

[0034] The fourth wiring and the third wiring are respectively formed in different metal layers, and the orthographic projection of the fourth wiring and the orthographic projection of the third wiring at least partially cross or overlap, and the fourth wiring or the orthographic projection of the fourth wiring is located on one side of the second wiring.

[0035] In a third aspect, an embodiment of the present disclosure provides a semiconductor memory, which includes at least a semiconductor structure as described in any one of the first aspects.

[0036] The disclosed embodiment provides a semiconductor structure and a wiring method thereof and a semiconductor memory, the semiconductor structure comprising: a plurality of wirings, the wirings comprising a first wiring, a second wiring, and a third wiring, the first wiring and the second wiring have the same properties, and the third wiring has different properties from the first wiring; the first wiring and the second wiring are respectively formed in different metal layers, and the orthographic projection of the first wiring and the orthographic projection of the second wiring at least partially cross or overlap; the third wiring or the orthographic projection of the third wiring is located on one side of the first wiring. In this way, for the first wiring and the second wiring with the same properties, different metal layers are used, and the orthographic projection of the first wiring and the orthographic projection of the second wiring at least partially cross or overlap; for the first wiring and the third wiring with different properties, the third wiring or the orthographic projection of the third wiring is located on one side of the first wiring; in this way, placing the wirings with the same properties together and using different metal layers can not only reduce the distance between the wirings, but also reduce the coupling crosstalk between different metal layers, so that the coupling capacitance between different metal layers will not affect the data, thereby saving the layout space. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A timing diagram of a data signal;

[0038] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0039] Figure 3 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0040] Figure 4 A schematic diagram of a signal flow of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0041] Figure 5 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 3 ;

[0042] Figure 6 A partial enlarged schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0043] Figure 7 A partial enlarged schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0044] Figure 8 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 4 ;

[0045] Fig. 9 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 5 ;

[0046] Fig.10 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 6 ;

[0047] Fig.11 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 7 ;

[0048] Fig.12 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 8 ;

[0049] Fig.13 A schematic diagram of a signal flow of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0050] Fig.14 A detailed schematic diagram of the composition of a semiconductor structure provided by an embodiment of the present disclosure;

[0051] Fig.15 A schematic diagram of a process flow of a wiring method for a semiconductor structure provided by an embodiment of the present disclosure;

[0052] Fig.16 A schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant applications, rather than to limit the present disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant applications are shown in the drawings.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0055] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0056] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0057] It should also be pointed out that layout is the bridge from integrated circuit design to manufacturing. It is the process by which integrated circuit designers transform simulated and optimized circuits into a series of geometric figures. It contains physical information data related to the device, such as the size of the integrated circuit, the topology definition of each layer, etc. The manufacture of integrated circuits is inevitably limited by the level of process technology and the physical parameters of the device. In order to ensure the correct operation of the device and improve the yield of the chip, the layout designer is required to follow certain design rules when designing the layout. Layout design is the process of creating an accurate physical description of engineering drawings, that is, the process of defining the shape, size and relative position of each process layer.

[0058] In semiconductor memory, there are multiple groups of data paths, and different groups of data are coupled with each other. Usually, the data lines that affect each other will use the same or different levels of metal wiring when wiring, and then avoid mutual coupling by using isolation lines or increasing the distance between metal wiring.

[0059] For example, see Figure 1 , which shows a timing diagram of a data signal. Figure 1As shown, the semiconductor memory transmits a signal source when working, including four groups of data signals A, B, C, and D. Among them, A<7:0> indicates that the data signal of group A includes A <0> To A <7> Similarly, B<7:0> indicates that the data signal of group B includes B <0> To B <7> Eight signals, C<7:0> indicates that the C group data signal includes C <0> to C <7> Eight signals, D<7:0> indicates that the D group data signal includes D <0> To D <7> Eight signals. These four groups of data signals are transmitted using corresponding data lines. When the data type transmitted by group A data line is 1 (A=1), the data type transmitted by group B data line is 0 (B=0), the data type transmitted by group C data line is 1 (C=1), and the data type transmitted by group D data line is 0 (D=0); conversely, when A=0, B=1, C=0, and D=1. Further, when the four groups of data signals are respectively inverted by the inverters in the signal lines, the corresponding relationship of the data types transmitted by the four groups of data lines remains unchanged, that is, when A=1, B=0, C=1, and D=0; or when A=0, B=1, C=0, and D=1. Here, in order to avoid mutual coupling between different data lines during data transmission, isolation lines need to be used between each group of data lines or the distance between the data lines needs to be increased, but this will increase the demand for layout space.

[0060] Based on this, the embodiment of the present disclosure provides a semiconductor structure, by forming a first wiring and a second wiring with the same properties in different metal layers, and the orthographic projection of the first wiring and the orthographic projection of the second wiring at least partially cross or overlap; and forming a third wiring with different properties from the first wiring, and the third wiring or the orthographic projection of the third wiring is located on one side of the first wiring. In this way, placing wirings with the same properties together and using different metal layers can not only reduce the distance between the wirings, but also reduce the coupling crosstalk between different metal layers, so that the coupling capacitance between different metal layers will not affect the data, thereby saving layout space.

[0061] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0062] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a semiconductor structure provided by an embodiment of the present disclosure Figure 1 .like Figure 2 As shown, the semiconductor structure 10 may include: a plurality of wirings, the wirings include a first wiring 11, a second wiring 12, and a third wiring 13, the first wiring 11 and the second wiring 12 have the same properties, and the third wiring 13 has a different property from the first wiring 11;

[0063] The first wiring 11 and the second wiring 12 are respectively formed in different metal layers, and the orthographic projection of the first wiring 11 and the orthographic projection of the second wiring 12 at least partially cross or partially overlap;

[0064] The third wiring 13 or an orthographic projection of the third wiring 13 is located on one side of the first wiring 11 .

[0065] It should be noted that the semiconductor structure 10 may specifically refer to a layout structure of a memory. The layout structure of the embodiment of the present disclosure not only reduces the coupling effect between data paths, but also achieves the goal and optimization of circuit performance.

[0066] It should also be noted that the orthographic projection of the first wiring 11 refers to the orthographic projection on the substrate; similarly, the orthographic projection of the second wiring 12 and the orthographic projection of the third wiring 13 also refer to the orthographic projection on the substrate. In addition, in the embodiments of the present disclosure, unless otherwise specified, the "orthographic projection" here refers to the orthographic projection on the substrate.

[0067] It should also be noted that in the embodiment of the present disclosure, the number of the first wiring 11 can be one or more, the number of the second wiring 12 can be one or more, and the number of the third wiring 13 can be one or more. The specific number of each wiring is set according to the actual situation and is not specifically limited here. For example, Figure 3 As shown, the first wiring 11 may include eight metal wirings for transmitting A <0> To A <7> Eight signals; the second wiring 12 may include eight metal wirings for transmitting C <0> to C <7> Eight signals; the third wiring 13 may include eight metal wirings for transmitting B <0> To B <7> Eight signals.

[0068] In some embodiments, Figure 3 As shown, the metal layer of the semiconductor structure 10 may include a first metal layer 100 and a second metal layer 200, and the second metal layer 200 is located on the first metal layer 100, wherein:

[0069] The first wiring 11 may be formed in the first metal layer 100 , and the second wiring 12 may be formed in the second metal layer 200 . The second wiring 12 is located above the first wiring 11 , and the orthographic projection of the first wiring 11 and the orthographic projection of the second wiring 12 partially intersect or overlap.

[0070] It should be noted that, for the third wiring 13, Figure 3As shown, the third wiring 13 can be formed on the same metal layer as the first wiring 11, such as the first metal layer 100. In this case, the third wiring 13 is located on one side of the first wiring 11 and is far away from each other. In addition, the third wiring 13 can also be formed on a different metal layer from the first wiring 11. For example, the third wiring 13 and the second wiring 12 are formed on the same metal layer, such as the second metal layer 200. In this case, the orthographic projection of the third wiring 13 is located on one side of the first wiring 11 and is far away from each other. This is not specifically limited here.

[0071] It should also be noted that, in the embodiments of the present disclosure, the above letters only represent abbreviations of signals and do not constitute specific limitations on signal types. In practical applications, each signal may also be described in other ways, which are not specifically limited here.

[0072] In some embodiments, there may be many types of wiring. Exemplarily, the types of wiring include at least one of the following: a data line, a signal line, and a power line.

[0073] It should be noted that in the embodiments of the present disclosure, the data line can be used to transmit data, such as data "0" or data "1"; the signal line can be used to transmit enable signals, pre-charge signals, control signals, drive signals, etc., and the power line can be used to transmit voltage and current.

[0074] Thus, when the type of wiring is different, the attributes of the wiring will also be different. When the type of wiring is a data line, a signal line or a power line, the attribute of the wiring can be a signal flow direction; when the type of wiring is a data line, the attribute of the wiring can also be a data type; but this is not specifically limited.

[0075] In a possible implementation, the attribute may include a signal flow direction; wherein: the signal flow directions of the first wiring 11 and the second wiring 12 are both in the first direction, and the signal flow direction of the third wiring 13 is in the second direction.

[0076] Here, the first direction and the second direction are opposite directions to each other.

[0077] It should be noted that Figure 4 Taking the signal flow direction shown in the figure as an example, the signal flow directions of A<7:0> and C<7:0> are the same, and the signal flow directions of A<7:0> and B<7:0> are different. Among them, for A<7:0> and C<7:0>, the positive projections of A<7:0> and C<7:0> on the substrate can overlap or intersect each other; therefore, illustratively, A<7:0> can be transmitted using the first wiring 11, C<7:0> can be transmitted using the second wiring 12, and B<7:0> can be transmitted using the third wiring 13. That is to say, in Figure 3In the semiconductor structure 10 shown, the signal flow directions of the first wiring 11 and the second wiring 12 are in the same direction, and the signal flow direction of the third wiring 13 is in the opposite direction. At this time, the first wiring 11 and the second wiring 12 with the same signal flow direction can be arranged together, that is, the data lines in the same direction use the upper and lower layers of metal wiring, which can not only minimize the wiring space, but also reduce the coupling crosstalk between different metal layers.

[0078] In another possible implementation, when the wiring type is a data line, the attribute may further include a data type; wherein: the data types transmitted by the first wiring 11 and the second wiring 12 are both first values, and the data type transmitted by the third wiring 13 is a second value.

[0079] Here, the first value is one of 0 or 1, and the second value is the other of 0 or 1.

[0080] It should be noted that in the embodiment of the present disclosure, the data types transmitted by the first wiring 11 and the second wiring 12 may be the same, and the data types transmitted by the third wiring 13 and the first wiring 11 may be different. For example, the data types transmitted by the first wiring 11 and the second wiring 12 may both be 0, and the data type transmitted by the third wiring 13 may be 1; or, the data types transmitted by the first wiring 11 and the second wiring 12 may both be 1, and the data type transmitted by the third wiring 13 may be 0, and this is not specifically limited. At this time, the first wiring 11 and the second wiring 12 having the same data type may also be laid out together, thereby reducing the wiring space.

[0081] In some embodiments, Figure 2 Based on the semiconductor structure 10 shown, see Figure 5 , the semiconductor structure 10 further includes an isolation line 15, wherein:

[0082] The first wiring 11 and the third wiring 13 are located in the same metal layer, and an isolation track 15 is disposed between the first wiring 11 and the third wiring 13 .

[0083] It should be noted that in the disclosed embodiment, since the properties of the first wiring 11 and the third wiring 13 are different, in order to avoid coupling crosstalk between the two, the first wiring 11 and the third wiring 13 in the same metal layer need to be far away from each other. Among them, if the first wiring 11 and the third wiring 13 are located in the same metal layer, then an isolation line 15 can be set between the first wiring 11 and the third wiring 13 in the metal layer or the distance between the first wiring 11 and the third wiring 13 can be increased to make them far away from each other; or, if the third wiring 13 and the second wiring 12 are located in the same metal layer, then an isolation line 15 can be set between the second wiring 12 and the third wiring 13 or the distance between the second wiring 12 and the third wiring 13 can be increased, and this is not specifically limited. In this way, the influence of mutual coupling between data wirings of different properties can be reduced, avoiding the problem of inaccurate data transmission.

[0084] In some embodiments, the second wiring 12 is located above the first wiring 11, wherein:

[0085] The orthographic projection of the second wiring 12 completely overlaps with the orthographic projection of the first wiring 11; or,

[0086] The orthographic projection of the second wiring 12 partially overlaps with the orthographic projection of the first wiring 11; or,

[0087] The orthographic projection of the second wiring 12 is located in the spacing region between adjacent first wirings 11 , or in other words, the orthographic projection of the second wiring 12 is intersecting with the first wiring 11 .

[0088] For example, Figure 6 As shown, for the first wiring 11 and the second wiring 12 with the same properties, (a) shows that the orthographic projection of the second wiring 12 and the orthographic projection of the first wiring 11 completely overlap, (b) shows that the orthographic projection of the second wiring 12 and the orthographic projection of the first wiring 11 have a partial overlapping area, and (c) shows that the orthographic projection of the second wiring 12 is located in the interval area between the orthographic projections of two adjacent first wirings 11. In addition, for the orthographic projection of the second wiring 12 and the orthographic projection of the first wiring 11, there is a partial overlapping area, except Figure 6 In the example provided in (b), the partially overlapping area here can also be as follows Figure 7 The orthographic projection of the second wiring 12 shown and the orthographic projections of at least two first wirings 11 partially overlap, which is not specifically limited here.

[0089] In the embodiment of the present disclosure, the width of the first wiring 11 and the width of the second wiring 12 may be equal or unequal, and the spacing distance between adjacent first wirings 11 and the spacing distance between adjacent second wirings 12 may be equal or unequal, which is not specifically limited here. In addition, in the embodiment of the present disclosure, in order to reduce the wiring space, the orthographic projection of the second wiring 12 and the orthographic projection of the first wiring 11 may completely overlap; in order to reduce the influence of the coupling capacitance generated between metal wirings on the accuracy of transmitted data, the orthographic projection of the second wiring 12 may be located in the spacing area between adjacent first wirings 11; however, considering the compromise effect, in order to reduce the wiring space and reduce the influence of the coupling capacitance generated between metal wirings on the accuracy of transmitted data, the orthographic projection of the second wiring 12 and the orthographic projection of the first wiring 11 may partially overlap, specifically as follows: Figure 7 That is to say, the positional relationship between the first wiring 11 and the second wiring 12 is not specifically limited here either.

[0090] In some embodiments, the first wiring 11 and the second wiring 12 both have a first arrangement direction, the orthographic projection of the center line of the second wiring 12 coincides with the center line of the spacing area between adjacent first wirings 11, and the width of the second wiring 12 in the first arrangement direction is greater than the width of the spacing area in the first arrangement direction. That is, in the embodiments of the present disclosure, Figure 7 For example, the orthographic projection of the second wiring 12 can partially overlap with the orthographic projection of the first wiring 11. At this time, the metal distance for the same properties or the same group of wirings can be minimized as much as possible. At the same time, the coupling capacitance generated between the metal wirings will not affect the data line, thereby achieving the purpose of saving layout area.

[0091] In some embodiments, Figure 2 Based on the semiconductor structure 10 shown, see Figure 8 , the wiring may further include a fourth wiring 14; wherein: the fourth wiring 14 has the same properties as the third wiring 13, the fourth wiring 14 and the third wiring 13 are respectively formed in different metal layers, and the orthographic projection of the fourth wiring 14 and the orthographic projection of the third wiring 13 at least partially cross or partially overlap; the fourth wiring 14 has different properties from the second wiring 12, and the fourth wiring 14 or the orthographic projection of the fourth wiring 14 is located on one side of the second wiring 12.

[0092] In the embodiment of the present disclosure, the orthographic projection of the third wiring 13 refers to the orthographic projection on the substrate, and the orthographic projection of the fourth wiring 14 also refers to the orthographic projection on the substrate.

[0093] In the embodiment of the present disclosure, the number of the fourth wiring 14 is one or more. The specific number of the fourth wiring 14 can be set according to actual conditions and is not specifically limited here. For example, Fig. 9As shown, the fourth wiring 14 may include eight metal wirings for transmitting D <0> To D <7> Eight signals. Fig. 9 In the embodiment, the first wiring 11 and the third wiring 13 may be formed in the first metal layer 100, and the second wiring 12 and the fourth wiring 14 may be formed in the second metal layer 200. For the fourth wiring 14, the fourth wiring 14 is located above the third wiring 13, and the orthographic projection of the fourth wiring 14 and the orthographic projection of the third wiring 13 at least partially cross or overlap; and in the second metal layer 200, the fourth wiring 14 is located on one side of the second wiring 12, away from each other.

[0094] It should also be noted that, for the fourth wiring 14, the fourth wiring 14 can be formed in the same metal layer as the second wiring 12, in which case the fourth wiring 14 is located on one side of the second wiring 12; alternatively, the fourth wiring 14 can also be formed in a different metal layer from the second wiring 12. For example, the fourth wiring 14 and the first wiring 11 are formed in the same metal layer, in which case the orthographic projection of the fourth wiring 14 is located on one side of the second wiring 12. This is not specifically limited here.

[0095] In some embodiments, the second wiring 12 and the fourth wiring 14 are located in the same metal layer. In order to reduce the coupling crosstalk between metal wirings with different properties, the second wiring 12 and the fourth wiring 14 also need to be away from each other. Here, the distance between the second wiring 12 and the fourth wiring 14 can be increased, or an isolation line can be set between the second wiring 12 and the fourth wiring 14. For example, Fig.10 As shown, the first wiring 11 and the third wiring 13 are formed in the first metal layer 100, and an isolation track 15 is arranged between the first wiring 11 and the third wiring 13; the second wiring 12 and the fourth wiring 14 are formed in the second metal layer 200, and an isolation track 16 is arranged between the second wiring 12 and the fourth wiring 14; in this way, when the properties of A and C are the same, and the properties of B and D are the same, A<7:0> and C<7:0> are wired together, and B<7:0> and D<7:0> are wired together, thereby reducing the wiring space, and adding isolation tracks between the different-directional data lines, so that the coupling capacitance generated between the metal wirings will not affect the data lines.

[0096] It should be noted that in the embodiment of the present disclosure, the fourth wiring 14 is located above the third wiring 13, wherein the orthographic projection of the fourth wiring 14 completely overlaps with the orthographic projection of the third wiring 13; or, the orthographic projection of the fourth wiring 14 partially overlaps with the orthographic projection of the third wiring 13; or, the orthographic projection of the fourth wiring 14 is located in the spacing area between adjacent third wirings 13, or, in other words, the orthographic projection of the fourth wiring 14 is cross-distributed with the third wiring 13. It should also be noted that both the third wiring 13 and the fourth wiring 14 have a first arrangement direction, the orthographic projection of the center line of the fourth wiring 14 coincides with the center line of the spacing area between adjacent third wirings 13, and the width of the fourth wiring 14 in the first arrangement direction is greater than the width of the spacing area in the first arrangement direction. Specifically, the positional relationship between the fourth wiring 14 and the third wiring 13 is as follows: Figure 6 or Figure 7 The positional relationship between the first wiring 11 and the second wiring 12 is similar and will not be described in detail here.

[0097] In some embodiments, see Fig.11 , the first wiring 11 includes a first wiring portion 111 and a second wiring portion 112, and the second wiring 12 includes a third wiring portion 121 and a fourth wiring portion 122, wherein:

[0098] The first wiring portion 111 and the second wiring portion 112 are respectively formed in different metal layers, and the orthographic projection of the first wiring portion 111 and the orthographic projection of the second wiring portion 112 at least partially intersect or partially overlap;

[0099] The third wiring portion 121 and the fourth wiring portion 122 are respectively formed in different metal layers, and the orthographic projection of the third wiring portion 121 and the orthographic projection of the fourth wiring portion 122 at least partially cross or partially overlap.

[0100] It should be noted that in the embodiment of the present disclosure, the orthographic projection of the first wiring portion 111, the orthographic projection of the second wiring portion 112, the orthographic projection of the third wiring portion 121 and the orthographic projection of the fourth wiring portion 122 all refer to orthographic projections on the substrate.

[0101] It should be noted that in the embodiment of the present disclosure, in the first wiring 11, the number of the first wiring portion 111 can be one or more, and the number of the second wiring portion 112 can be one or more; in the second wiring 12, the number of the third wiring portion 121 can be one or more, and the number of the fourth wiring portion 122 can be one or more. The specific number of each wiring portion can be set according to actual conditions and is not specifically limited here. For example, Fig.11As shown, the first wiring portion 111 may include four metal wirings for transmitting A <0> , A <2> , A <4> , A <6> The second wiring portion 112 may include four metal wirings for transmitting A <1> , A <3> , A <5> , A <7> The third wiring portion 121 may include four metal wirings for transmitting C <0> , C <2> , C <4> , C <6> The fourth wiring portion 122 may include four metal wirings for transmitting C <1> , C <3> , C <5> , C <7> Wait for four signals.

[0102] It should also be noted that if Fig.11 As shown, the first wiring portion 111 and the third wiring portion 121 can be formed in the first metal layer 100, the second wiring portion 112 and the fourth wiring portion 122 can be formed in the second metal layer 200, the second wiring portion 112 is located above the first wiring portion 111, and the orthographic projection of the first wiring portion 111 and the orthographic projection of the second wiring portion 112 at least partially cross or partially overlap; the fourth wiring portion 122 is located above the third wiring portion 121, and the orthographic projection of the third wiring portion 121 and the orthographic projection of the fourth wiring portion 122 at least partially cross or partially overlap. Wherein, for the second wiring portion 112 being located above the first wiring portion 111, specifically, it can be: the orthographic projection of the second wiring portion 112 completely overlaps with the orthographic projection of the first wiring portion 111; or, the orthographic projection of the second wiring portion 112 partially overlaps with the orthographic projection of the first wiring portion 111; or, the orthographic projection of the second wiring portion 112 is located in the interval area between adjacent first wiring portions 111, or, the orthographic projection of the second wiring portion 112 is intersecting with the first wiring portion 111. For the fourth wiring portion 122 being located above the third wiring portion 121, specifically, it can be: the orthographic projection of the fourth wiring portion 122 completely overlaps with the orthographic projection of the third wiring portion 121; or, the orthographic projection of the fourth wiring portion 122 partially overlaps with the orthographic projection of the third wiring portion 121; or, the orthographic projection of the fourth wiring portion 122 is located in the interval area between adjacent third wiring portions 121, or, the orthographic projection of the fourth wiring portion 122 is intersecting with the third wiring portion 121.

[0103] Further, in the embodiment of the present disclosure, the first wiring portion 111 and the second wiring portion 112 may have a first arrangement direction, the orthographic projection of the center line of the second wiring portion 112 coincides with the center line of the spacing region between adjacent first wiring portions 111, and the width of the second wiring portion 112 in the first arrangement direction is greater than the width of the spacing region in the first arrangement direction. The third wiring portion 121 and the fourth wiring portion 122 both have a first arrangement direction, the orthographic projection of the center line of the fourth wiring portion 122 coincides with the center line of the spacing region between adjacent third wiring portions 121, and the width of the fourth wiring portion 122 in the first arrangement direction is greater than the width of the spacing region in the first arrangement direction.

[0104] In some embodiments, Fig.11 Based on the semiconductor structure 10 shown, see Fig.12 , the third wiring 13 includes a fifth wiring portion 131 and a sixth wiring portion 132, and the fourth wiring 14 includes a seventh wiring portion 141 and an eighth wiring portion 142, wherein:

[0105] The fifth wiring portion 131 and the sixth wiring portion 132 are respectively formed in different metal layers, and the orthographic projection of the fifth wiring portion 131 and the orthographic projection of the sixth wiring portion 132 at least partially cross or partially overlap;

[0106] The seventh wiring portion 141 and the eighth wiring portion 142 are respectively formed in different metal layers, and the orthographic projection of the seventh wiring portion 141 and the orthographic projection of the eighth wiring portion 142 at least partially cross or partially overlap.

[0107] It should be noted that in the embodiment of the present disclosure, the orthographic projection of the fifth wiring portion 131, the orthographic projection of the sixth wiring portion 132, the orthographic projection of the seventh wiring portion 141 and the orthographic projection of the eighth wiring portion 142 all refer to orthographic projections on the substrate.

[0108] It should be noted that in the embodiment of the present disclosure, in the third wiring 13, the number of the fifth wiring portion 131 can be one or more, and the number of the sixth wiring portion 132 can be one or more; in the fourth wiring 14, the number of the seventh wiring portion 141 can be one or more, and the number of the eighth wiring portion 142 can be one or more. For example, Fig.12As shown, the fifth wiring portion 131 may include four metal wirings for transmitting B <0> , B <2> , B <4> , B <6> The sixth wiring portion 132 may include four metal wirings for transmitting B <1> , B <3> , B <5> , B <7> The seventh wiring portion 141 may include four metal wirings for transmitting D <0> , D <2> , D <4> , D <6> The eighth wiring portion 142 may include four metal wirings for transmitting D <1> , D <3> , D <5> , D <7> Wait for four signals.

[0109] It should also be noted that if Fig.12 As shown, if the third wiring portion 121 and the fifth wiring portion 131 are in the same metal layer and correspond to different properties, an isolation track 15 can be set between the third wiring portion 121 and the fifth wiring portion 131; if the fourth wiring portion 122 and the sixth wiring portion 132 are in the same metal layer and correspond to different properties, an isolation track 16 can be set between the fourth wiring portion 122 and the sixth wiring portion 132, thereby reducing the coupling crosstalk between metal wirings of different properties, so that the coupling capacitance generated between the metal wirings will not affect the data line.

[0110] It should also be noted that if Fig.12 As shown, the fifth wiring portion 131 and the seventh wiring portion 141 can be formed in the first metal layer 100, and the sixth wiring portion 132 and the eighth wiring portion 142 can be formed in the second metal layer 200. Among them, the sixth wiring portion 132 is located above the fifth wiring portion 131, and the positional relationship between the fifth wiring portion 131 and the sixth wiring portion 132 is similar to the positional relationship between the first wiring portion 111 and the second wiring portion 112; the eighth wiring portion 142 is located above the seventh wiring portion 141, and the positional relationship between the seventh wiring portion 141 and the eighth wiring portion 142 is similar to the positional relationship between the third wiring portion 121 and the fourth wiring portion 122, which will not be described in detail here.

[0111] In summary, the embodiment of the present disclosure provides a semiconductor structure, which includes: multiple wirings, the wirings include a first wiring, a second wiring, and a third wiring, the first wiring and the second wiring have the same properties, and the third wiring has different properties from the first wiring; the first wiring and the second wiring are respectively formed in different metal layers, and the orthographic projection of the first wiring and the orthographic projection of the second wiring at least partially cross or overlap; the third wiring or the orthographic projection of the third wiring is located on one side of the first wiring. In this way, for the first wiring and the second wiring with the same properties, different metal layers are used, and the orthographic projection of the first wiring and the orthographic projection of the second wiring at least partially cross or overlap; for the first wiring and the third wiring with different properties, the third wiring or the orthographic projection of the third wiring is located on one side of the first wiring; in this way, placing the wirings with the same properties together and using different metal layers can not only reduce the distance between the wirings, but also reduce the coupling crosstalk between different metal layers, so that the coupling capacitance between different metal layers will not affect the data, thereby saving layout space.

[0112] In another embodiment of the present disclosure, see Fig.13 , which shows a signal flow diagram of a semiconductor structure provided by an embodiment of the present disclosure Figure 2 .like Fig.13 As shown, different metal layers can be used for wiring of signal A<7:0>, such as the second metal layer (metal 2) and the third metal layer (metal 3), where A<7,5,3,1> is wired with metal 2 and A<6,4,2,0> is wired with metal 3; in addition, different metal layers can also be used for wiring of signals B<7:0>, C<7:0> and D<7:0>, such as B<7,5,3,1> is wired with metal 2 and B<6,4,2,0> is wired with metal 3; C<7,5,3,1> is wired with metal 2 and C<6,4,2,0> is wired with metal 3; D<7,5,3,1> is wired with metal 2 and D<6,4,2,0> is wired with metal 3. Fig.13 In the embodiment, the signal flow directions of A<7:0> and C<7:0> are the same, both are in the first direction; the signal flow directions of B<7:0> and D<7:0> are the same, both are in the second direction; and the first direction is different from the second direction.

[0113] for Fig.13 The signal flow shown in the figure can be represented by the corresponding semiconductor structure. Fig.10 or Fig.12As shown. In the disclosed embodiment, in order to avoid data deviation during transmission, layout design can be used here to wire A<7:0> and C<7:0> together, B<7:0> and D<7:0> together, and use upper and lower layers of metal wiring for data lines in the same direction, so that the layout can be minimized, and the coupling capacitance between different metal wirings will not affect the data. In addition, it is only necessary to place isolation tracks or increase the distance (space) between the coupled address lines, without placing isolation tracks between each group of signals. In other words, data lines in the same direction are wired together and use different metal layers, and isolation tracks are placed or the space is increased between data lines in opposite directions, so as to save layout space and reduce the coupling crosstalk between different metal layers.

[0114] In a specific embodiment, coupling capacitance (or "parasitic capacitance") may exist between various metal wirings, and coupling capacitance may exist between metal wirings of the same direction or different directions. Fig.14 , which shows a detailed composition diagram of a semiconductor structure provided by an embodiment of the present disclosure. Fig.14 As shown, (a) shows Fig.12 Example of corresponding coupling capacitance, A <0> and C <6> There is a coupling capacitor, C <6> and C <4> There is a coupling capacitor between them, A <0> and A <1> There is a coupling capacitor between them, A <0> and C <7> There are also coupling capacitors between them. (b) shows Fig.10 An example of a corresponding coupling capacitor, C <0> and C <1> There is a coupling capacitor, C <1> and C <2> There is a coupling capacitor, C <0> and A <0> There is a coupling capacitor between them, A <0> and C <1> There are also coupling capacitors and so on.

[0115] In simple terms, there is coupling capacitance between metal layers, between adjacent metal wirings in the same metal layer, and between metal wirings in different metal layers. Due to the existence of coupling capacitance, metal wirings are susceptible to coupling crosstalk, so it is necessary to minimize the coupling capacitance during the layout and wiring process to reduce the impact of coupling capacitance.

[0116] The disclosed embodiments provide a semiconductor structure. The specific implementation of the aforementioned embodiments is described in detail through the above embodiments. It can be seen that the data lines in the same direction or in the same group are arranged together, and the data lines in the same direction or in the same group are arranged with upper and lower layers of metal wiring. In this way, the wiring distance of the data lines in the same direction or in the same group can be minimized, and the coupling capacitance between the metal wirings will not affect the data. Moreover, the more data lines there are, the more space can be saved, thereby achieving the purpose of saving layout space.

[0117] In another embodiment of the present disclosure, see Fig.15 , which shows a schematic flow chart of a wiring method for a semiconductor structure provided by an embodiment of the present disclosure. Fig.15 As shown, the method may include:

[0118] S201 , forming a first wiring.

[0119] S202 , forming a second wiring having the same properties as the first wiring, wherein the first wiring and the second wiring are respectively formed in different metal layers, and an orthographic projection of the first wiring and an orthographic projection of the second wiring at least partially intersect or partially overlap.

[0120] S203 , forming a third wiring having a different property from that of the first wiring, wherein the third wiring or an orthographic projection of the third wiring is located on one side of the first wiring.

[0121] It should be noted that the wiring method provided in the embodiment of the present disclosure can be applied to designing the layout structure of a memory. Among them, using the layout structure of the embodiment of the present disclosure can not only reduce the coupling effect between data paths, but also achieve the goal and optimization of circuit performance.

[0122] It should also be noted that the order of steps S201 to S203 does not limit the order of wiring formation. In addition, wiring located in the same metal layer can be formed in the same process. For example, when the first wiring and the third wiring with different properties are located in the same metal layer, the first wiring and the third wiring can be formed in the same process, which is not specifically limited here.

[0123] It should also be noted that the type of wiring includes at least one of the following: data line, signal line and power line. In the embodiments of the present disclosure, when the type of wiring is different, the attributes of the wiring may also be different. When the type of wiring is a data line, a signal line or a power line, the attribute of the wiring may be the signal flow direction; when the type of wiring is a data line, the attribute of the wiring may be the data type.

[0124] In some embodiments, the signal flow directions of the first wiring and the second wiring are both in the first direction, and the signal flow direction of the third wiring is in the second direction; wherein the first direction and the second direction are opposite directions to each other.

[0125] In some other embodiments, the data types transmitted by the first wiring and the second wiring are both first values, and the data type transmitted by the third wiring is second value; wherein the first value is one of 0 or 1, and the second value is the other of 0 or 1.

[0126] In the embodiment of the present disclosure, when the first wiring and the third wiring are located in the same metal layer, in order to reduce coupling crosstalk between different metal wirings, the method may further include: providing an isolation line between the first wiring and the third wiring.

[0127] In some embodiments, the method may further include: forming a fourth wiring having the same properties as the third wiring; wherein the fourth wiring and the third wiring are respectively formed in different metal layers, and the orthographic projection of the fourth wiring and the orthographic projection of the third wiring at least partially cross or partially overlap, and the fourth wiring or the orthographic projection of the fourth wiring is located on one side of the second wiring.

[0128] In some embodiments, when the second wiring and the fourth wiring are located in the same metal layer, in order to reduce coupling crosstalk between different metal wirings, the method may further include: providing an isolation line between the second wiring and the fourth wiring.

[0129] It should be noted that when the second wiring and the fourth wiring with different properties are located in the same metal layer, the second wiring and the fourth wiring can also be formed in the same process, and there is no specific limitation on this.

[0130] The embodiments of the present disclosure provide a wiring method for a semiconductor structure. During the wiring process, different metal layers are used for a first wiring and a second wiring with the same properties, and the orthographic projection of the first wiring and the orthographic projection of the second wiring at least partially cross or overlap; for a first wiring and a third wiring with different properties, the third wiring or the orthographic projection of the third wiring is located on one side of the first wiring; in this way, wirings with the same properties are placed together and different metal layers are used, which can not only reduce the distance between the wirings, but also reduce the coupling crosstalk between different metal layers, so that the coupling capacitance between different metal layers will not affect the data, thereby saving layout space.

[0131] In another embodiment of the present disclosure, see Fig.16 , which shows a schematic diagram of the composition structure of a semiconductor memory provided by an embodiment of the present disclosure. Fig.16 As shown, the semiconductor memory 30 includes the semiconductor structure 10 described in any one of the aforementioned embodiments.

[0132] In some embodiments, the semiconductor structure 10 can be applied to a semiconductor memory 30. The semiconductor memory 30 may be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), etc., which are not specifically limited here.

[0133] It should also be noted that in the embodiments of the present disclosure, the layout design of semiconductors, especially the layout structure of memories, can be applied to the layout design of various memories. Among them, the layout layout of the embodiments of the present disclosure can achieve the goal and optimization of circuit performance, and in different data paths, the coupling effect between data paths can be reduced to avoid inaccurate data transmission.

[0134] Furthermore, in some embodiments, the semiconductor memory 30 may include a DRAM chip. The DRAM chip may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., which are not specifically limited here.

[0135] In summary, in the embodiment of the present disclosure, for the semiconductor memory 30, since it includes the semiconductor structure 10 described in the aforementioned embodiment, it can not only reduce the distance between the wirings, but also reduce the coupling crosstalk between different metal layers, so that the coupling capacitance between different metal layers will not affect the data, thereby saving layout space.

[0136] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0137] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0138] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0139] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0140] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0141] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0142] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0143] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, It is characterized in that include: A plurality of wirings, the wirings comprising a first wiring, a second wiring, and a third wiring, the first wiring and the second wiring having the same property, and the third wiring having a different property from the first wiring; The first wiring and the second wiring are respectively formed in different metal layers, and an orthographic projection of the first wiring and an orthographic projection of the second wiring at least partially cross or partially overlap; The third wiring or the orthographic projection of the third wiring is located on one side of the first wiring; wherein, The attribute includes a signal flow direction, the signal flow directions of the first wiring and the second wiring are both in a first direction, the signal flow direction of the third wiring is in a second direction, and the first direction and the second direction are opposite directions to each other; Alternatively, the attribute includes a data type, the data types transmitted by the first wiring and the second wiring are both first values, the data type transmitted by the third wiring is a second value, the first value is one of 0 or 1, and the second value is the other of 0 or 1.

2. The semiconductor structure according to claim 1, It is characterized in that The type of the wiring includes at least one of the following: a data line, a signal line, and a power line, and when the type of the wiring is the data line, the attribute of the wiring includes the data type.

3. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure further comprises an isolation channel, wherein: The first wiring and the third wiring are located in the same metal layer, and the isolation track is arranged between the first wiring and the third wiring.

4. The semiconductor structure according to claim 1, It is characterized in that The second wiring is located above the first wiring, wherein The orthographic projection of the second wiring completely overlaps with the orthographic projection of the first wiring; or, The orthographic projection of the second wiring partially overlaps with the orthographic projection of the first wiring; or, The orthographic projection of the second wiring is located in a spacing region between adjacent first wirings.

5. The semiconductor structure according to claim 4, It is characterized in that Both the first wiring and the second wiring have a first arrangement direction, the orthographic projection of the center line of the second wiring coincides with the center line of the spacing area between adjacent first wirings, and the width of the second wiring in the first arrangement direction is greater than the width of the spacing area in the first arrangement direction.

6. The semiconductor structure according to claim 5, It is characterized in that The wiring further includes a fourth wiring; The fourth wiring has the same property as the third wiring, the fourth wiring and the third wiring are respectively formed in different metal layers, and the orthographic projection of the fourth wiring and the orthographic projection of the third wiring at least partially intersect or partially overlap; The fourth wiring has a different property from that of the second wiring, and the fourth wiring or an orthographic projection of the fourth wiring is located on one side of the second wiring.

7. The semiconductor structure according to claim 1, It is characterized in that The first wiring includes a first wiring portion and a second wiring portion, and the second wiring includes a third wiring portion and a fourth wiring portion, wherein: The first wiring portion and the second wiring portion are respectively formed in different metal layers, and an orthographic projection of the first wiring portion and an orthographic projection of the second wiring portion at least partially intersect or partially overlap; The third wiring portion and the fourth wiring portion are respectively formed in different metal layers, and an orthographic projection of the third wiring portion and an orthographic projection of the fourth wiring portion at least partially intersect or partially overlap.

8. A wiring method for a semiconductor structure, It is characterized in that The method comprises: forming a first wiring; forming a second wiring having the same properties as the first wiring, wherein the first wiring and the second wiring are respectively formed in different metal layers, and an orthographic projection of the first wiring and an orthographic projection of the second wiring at least partially intersect or partially overlap; A third wiring having a different property from that of the first wiring is formed, and the third wiring or an orthographic projection of the third wiring is located on one side of the first wiring; wherein, The attribute includes a signal flow direction, the signal flow directions of the first wiring and the second wiring are both in a first direction, the signal flow direction of the third wiring is in a second direction, and the first direction and the second direction are opposite directions to each other; Alternatively, the attribute includes a data type, the data types transmitted by the first wiring and the second wiring are both first values, the data type transmitted by the third wiring is a second value, the first value is one of 0 or 1, and the second value is the other of 0 or 1.

9. The method according to claim 8, It is characterized in that The method further comprises: forming a fourth wiring having the same property as the third wiring; The fourth wiring and the third wiring are respectively formed in different metal layers, and the orthographic projection of the fourth wiring and the orthographic projection of the third wiring at least partially cross or overlap, and the fourth wiring or the orthographic projection of the fourth wiring is located on one side of the second wiring.

10. A semiconductor memory, It is characterized in that The semiconductor memory at least comprises the semiconductor structure according to any one of claims 1 to 7.

Images