A semiconductor device and a method for manufacturing the same

Abstract

Embodiments of the present application disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate, a first groove and a second groove located in the substrate; wherein, the second groove is formed by etching the substrate downward from a partial bottom surface of the first groove, and a side wall of the second groove is recessed inward by a preset length relative to a side wall of the first groove; a word line layer, including a first sub-part located in the second groove and a second sub-part located in the first groove; wherein, there is a gap between a side wall of the second sub-part and a side wall of the first groove; a word line capping layer, located in the first groove and covering the second sub-part; wherein, an air gap structure is provided in the word line capping layer at least at the gap.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Semiconductor devices, such as memories, include an embedded word line layer and source / drain doping regions on both sides of the word line layer. In actual processes, there is usually a partial overlap between the word line layer and the source / drain doping regions.

[0003] However, this overlap easily induces gate-induced drain leakage current (GIDL), affecting the reliability of semiconductor devices. Summary of the Invention

[0004] In view of this, embodiments of this application provide a semiconductor device and a manufacturing method thereof to solve at least one problem in the background art.

[0005] To achieve the above object, the technical solution of this application is realized as follows:

[0006] Embodiments of this application provide a semiconductor device, including:

[0007] A substrate and a first groove and a second groove located in the substrate; wherein, the second groove is formed by etching the substrate downward from a partial bottom surface of the first groove, and a side wall of the second groove is recessed inward by a preset length relative to a side wall of the first groove;

[0008] A word line layer, including a first sub-part located in the second groove and a second sub-part located in the first groove; wherein, there is a gap between a side wall of the second sub-part and a side wall of the first groove;

[0009] A word line capping layer, located in the first groove and covering the second sub-part; wherein, an air gap structure is provided in the word line capping layer at least at the gap.

[0010] In the above solution, a ratio of the preset length to a width of the word line layer is between 1:7 and 1:4.

[0011] In the above solution, the word line capping layer includes a first sub-layer, a second sub-layer located on the first sub-layer, and the air gap structure sandwiched between the first sub-layer and the second sub-layer; wherein, the first sub-layer covers a side wall and a bottom surface of the first groove, and a side wall and an upper surface of the second sub-part.

[0012] In the above solution, the air gap structure in the word line capping layer extends from the gap to above the second sub - part, so that the side wall and the upper surface of the second sub - part are surrounded by the air gap structure.

[0013] In the above solution, the air gap structure located at the gap has a uniform first width along the extending direction of the word line layer, and the ratio of the first width to the width of the word line layer is between 1:10 and 1:5.

[0014] In the above solution, the air gap structure located above the second sub - part has a uniform second width along the extending direction of the word line layer, and the ratio of the second width to the width of the word line layer is between 5:4 and 3:2.

[0015] In the above solution, the air gap structure located above the second sub - part has a uniform first height along the extending direction of the word line layer, and the ratio of the first height to the height of the word line layer is between 1:20 and 1:10.

[0016] In the above solution, the first sub - layer and the second sub - layer are formed of the same material.

[0017] In the above solution, the semiconductor device further includes: a dielectric layer, which is located in the second groove and covers the side wall and the bottom surface of the second groove.

[0018] In the above solution, the thickness of the dielectric layer is less than the preset length.

[0019] The embodiment of the present application also provides a manufacturing method of a semiconductor device, including:

[0020] Forming a first groove in a substrate;

[0021] Etching the substrate downward from a partial bottom surface of the first groove to form a second groove, and the side wall of the second groove is recessed inward by a preset length relative to the side wall of the first groove;

[0022] Forming a word line layer in the first groove and the second groove, the word line layer includes a first sub - part located in the second groove and a second sub - part located in the first groove; wherein, there is a gap between the side wall of the second sub - part and the side wall of the first groove;

[0023] Forming a word line capping layer in the first groove; wherein, an air gap structure is formed at least at the gap in the word line capping layer.

[0024] In the above solution, etching the substrate downward from a partial bottom surface of the first groove to form a second groove includes:

[0025] Filling an insulating material in the first groove;

[0026] Remove a portion of the insulating material to form a first opening exposing the partial bottom surface of the first groove, the distance between the sidewalls of the first opening and the sidewalls of the first groove being the preset length;

[0027] Etch the substrate downward from the first opening to form the second groove.

[0028] In the above solution, forming a word line layer in the first groove and the second groove includes:

[0029] Deposit a conductive material in the second groove to form the first sub - portion of the word line layer;

[0030] Continue to deposit the conductive material in the first opening, and perform a back - etching process to remove a portion of the conductive material in the first opening to form the second sub - portion of the word line layer.

[0031] In the above solution, after forming the second sub - portion of the word line layer, it further includes:

[0032] Remove the remaining insulating material in the first groove to form the gap.

[0033] In the above solution, the word line capping layer includes a first sub - layer, a second sub - layer located on the first sub - layer, and the air - gap structure sandwiched between the first sub - layer and the second sub - layer; forming a word line capping layer in the first groove includes:

[0034] Form the first sub - layer in the first groove, the first sub - layer covering the sidewalls and the bottom surface of the first groove, and covering the sidewalls and the upper surface of the second sub - portion;

[0035] Form a sacrificial layer on the first sub - layer, the sacrificial layer at least filling the gap;

[0036] Form the second sub - layer on the sacrificial layer;

[0037] Remove the sacrificial layer to form the air - gap structure.

[0038] In the above solution, removing the sacrificial layer includes:

[0039] Form at least one second opening in the second sub - layer to expose the sacrificial layer;

[0040] Use a wet etching process to remove the sacrificial layer.

[0041] In the above solution, the substrate includes an isolation region and an active region defined by the isolation region; wherein, the second opening is formed on the second sub - layer located in the isolation region.

[0042] Before forming the word line layer in the first groove and the second groove in the above solution, the method further includes: forming a dielectric layer in the second groove, and the dielectric layer covers the side wall and the bottom surface of the second groove.

[0043] The semiconductor device and its manufacturing method provided by the embodiments of the present application, wherein the semiconductor device includes: a substrate and a first groove and a second groove located in the substrate; wherein, the second groove is formed by etching the substrate downward from a part of the bottom surface of the first groove, and the side wall of the second groove is recessed inward by a preset length relative to the side wall of the first groove; a word line layer, including a first sub - part located in the second groove and a second sub - part located in the first groove; wherein, there is a gap between the side wall of the second sub - part and the side wall of the first groove; a word line capping layer, located in the first groove and covering the second sub - part; wherein, the word line capping layer has an air - gap structure at least at the gap. The second sub - part of the word line layer is spaced apart from the substrate by a relatively thick word line capping layer including an air - gap structure, which can effectively reduce the GIDL leakage phenomenon and improve the reliability of the semiconductor device.

[0044] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. Description of the Drawings

[0045] FIG. 1 is a schematic diagram of a semiconductor device provided in the related art;

[0046] Figure 2 is a top - view schematic diagram of the semiconductor device provided by the embodiments of the present application;

[0047] Figure 3 is a cross - sectional structure schematic diagram of the semiconductor device provided by the embodiments of the present application taken along Figure 2 line A - A';

[0048] Figure 4 is a flowchart of the manufacturing method of the semiconductor device provided by the embodiments of the present application;

[0049] Figures 5a to 5k is a cross - sectional structure schematic diagram of each step in the manufacturing method of the semiconductor device provided by the embodiments of the present application taken along Figure 2 line A - A'. Detailed Embodiments

[0050] Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully conveyed to those skilled in the art.

[0051] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these details. In other instances, well-known features of some technologies are not described in order to avoid confusion with the present application; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0052] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0053] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not necessarily mean that the present application necessarily has a first element, component, region, layer, or part.

[0054] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figure with other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the drawing is flipped, then an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0055] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0056] A semiconductor device, such as a dynamic random access memory (DRAM), includes an embedded word line layer and source / drain doping regions located on both sides of the word line layer. In an actual process, there is often a partial overlap between the word line layer and the source / drain doping regions.

[0057] Figure 1a A schematic diagram of a semiconductor device provided in the related art, as Figure 1a shown, the semiconductor device includes a substrate 10 and a groove T located in the substrate 10; a word line layer WL located in the groove T; a gate dielectric layer 11 located between the word line layer WL and the substrate 10; a word line capping layer 12 located in the groove T and covering the word line layer WL and the gate dielectric layer 11; a first source / drain doping region d1 and a second source / drain doping region d2 located on both sides of the word line layer WL, and there is an overlap region 13 between the first source / drain doping region d1, the second source / drain doping region d2 and the word line layer WL. The first source / drain doping region d1, the second source / drain doping region d2 and the word line layer WL are separated by the gate dielectric layer 11 in the overlap region 13.

[0058] However, since the thickness of the gate dielectric layer 11 is relatively thin, the electric field intensity generated in the gate-drain overlap region, i.e., the overlap region 13, is relatively large, which exacerbates the GIDL effect, resulting in an increase in the leakage current when the device is in the off state, an increase in static power consumption, and a reduction in the device lifetime.

[0059] To solve the above problems, researchers have tried to increase the thickness of the dielectric layer at the overlap region. Figure 1b As a schematic diagram of another semiconductor device provided in the related art, as Figure 1b shown, the semiconductor device includes a substrate 10 and a groove T located in the substrate 10; a word line layer WL located in the groove T, and there is a gap (not marked) between the upper part of the word line layer WL and the groove T; a word line capping layer 12 located in the groove T and covering the upper surface of the word line layer WL; a gate dielectric layer 11 located between the word line layer WL and the substrate 10; a dielectric layer 14 at least filling the gap, and the thickness of the dielectric layer 14 is greater than the thickness of the gate dielectric layer 11; a first source / drain doping region d1 and a second source / drain doping region d2 located on both sides of the word line layer WL, and there is an overlap region 13 between the first source / drain doping region d1, the second source / drain doping region d2 and the word line layer WL; wherein, the first source / drain doping region d1, the second source / drain doping region d2 and the word line layer WL are separated by the dielectric layer 14 in the overlap region 13, and the dielectric layer 14 has a relatively large thickness, which can effectively reduce the GIDL leakage phenomenon in the overlap region 13.

[0060] However, in the actual process, the word line layer WL is deposited in the groove T after the dielectric layer 14 is formed. Since the dielectric layer 14 has a relatively large thickness, it will affect the filling of the word line layer WL, and air gaps 15 are likely to be generated in the word line layer WL, affecting the performance of the semiconductor device. Based on this, the following technical solutions of the embodiments of the present application are proposed:

[0061] The embodiments of the present application provide a semiconductor device, including:

[0062] a substrate and a first groove and a second groove located in the substrate; wherein, the second groove is etched downward from a partial bottom surface of the first groove to form the substrate, and the side wall of the second groove is recessed inward by a preset length relative to the side wall of the first groove;

[0063] a word line layer, including a first sub-part located in the second groove and a second sub-part located in the first groove; wherein, there is a gap between the side wall of the second sub-part and the side wall of the first groove;

[0064] The word line capping layer is located in the first groove and covers the second sub - part; wherein, an air - gap structure is provided in the word line capping layer at least at the gap.

[0065] In the semiconductor device provided by the embodiment of the present application, an air - gap structure is provided between the second sub - part of the word line layer and the substrate, reducing the dielectric constant of the word line capping layer in contact with the word line layer, and thus reducing the Figure 1a and 1b electric field intensity generated at the overlapping region 13 as shown. It effectively enhances the control of the word line layer over the channel, improves the ability of the transistor to drive current, and thus effectively reduces the GIDL effect and improves the reliability of the semiconductor device.

[0066] In the semiconductor device provided by the embodiment of the present application, the side wall of the second groove is recessed inward by a preset length relative to the side wall of the first groove, resulting in a lower porosity of the formed word line layer and improving the performance of the semiconductor device. At the same time, the word line layer does not require secondary etching during formation, saving process steps.

[0067] The semiconductor device provided by the embodiment of the present application can be a dynamic random access memory (DRAM). However, it is not limited thereto. The semiconductor device can also be any semiconductor device with an embedded word line layer.

[0068] To make the above - mentioned objects, features, and advantages of the present application more obvious and understandable, the following will describe the specific embodiments of the present application in detail with reference to the accompanying drawings. When describing the embodiments of the present application in detail, for the convenience of explanation, the schematic diagrams will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the protection scope of the present application herein.

[0069] Figure 2 It is a top - view schematic diagram of the semiconductor device provided by the embodiment of the present application; Figure 3 For Figure 2 the cross - sectional structure schematic diagram taken along the dotted line A - A'. As Figure 2 and Figure 3 shown, the semiconductor device includes:

[0070] A substrate 20 and a first groove T1 and a second groove T2 located in the substrate 20; wherein, the second groove T2 is formed by etching the substrate 20 downward from a partial bottom surface of the first groove T1, and the side wall of the second groove T2 is recessed inward by a preset length L relative to the side wall of the first groove T1;

[0071] A word line layer WL, including a first sub - part WL1 located in the second groove T2 and a second sub - part WL2 located in the first groove T1; wherein, a gap (not labeled) is provided between the side wall of the second sub - part WL2 and the side wall of the first groove T1;

[0072] The word line capping layer 22 is located within the first groove T1 and covers the second sub - portion WL2; wherein, an air gap structure 223 is provided within the word line capping layer 22 at least at the gap (not labeled).

[0073] The substrate may be a semiconductor substrate and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III - V compound semiconductor material, at least one II - VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate, and the silicon substrate may be doped or undoped.

[0074] In one embodiment, the surface of the substrate includes a passivation layer (not shown in the figure), and the passivation layer is used to protect the substrate from oxidation, nitridation, damage, or contamination, etc. The material of the passivation layer may be a nitride, for example, silicon nitride.

[0075] In one embodiment, the substrate 20 includes an isolation region 23 and an active region AA defined by the isolation region 23.

[0076] Specifically, as Figure 2 shown, the substrate 20 includes a plurality of parallel - arranged active regions AA, and the isolation region 23 is disposed between the plurality of active regions AA. The material of the isolation region 23 may include one or more of an oxide (such as silicon oxide), a nitride (such as silicon nitride), and a oxynitride (such as silicon oxynitride).

[0077] In one embodiment, the semiconductor device further includes a first source / drain doping region d1 at both ends of the active region AA and a second source / drain doping region d2 in the middle region of the active region AA, and the first source / drain doping region d1 and the second source / drain doping region d2 are separated by the word line layer WL and the word line capping layer 22 located on the word line layer WL.

[0078] In one embodiment, the first source / drain doping region d1 and the second source / drain doping region d2 are formed on the top of the active region AA by ion implantation. In a specific embodiment, the first source / drain doping region d1 and the second source / drain doping region d2 have the same conduction type, such as n - type. It can be understood that when the first source / drain doping region d1 and the second source / drain doping region d2 are n - type doped, the substrate 20 located below the first source / drain doping region d1 and the second source / drain doping region d2 has p - type doping.

[0079] In one embodiment, the lower surfaces of the first source / drain doping region d1 and the second source / drain doping region d2 are flush with or higher than the bottom surface of the first groove T1. That is to say, the lower surfaces of the first source / drain doping region d1 and the second source / drain doping region d2 are flush with or higher than the lower surface of the second sub-part WL2. Thus, the first source / drain doping region d1, the second source / drain doping region d2 and the word line layer WL are separated by the word line capping layer 22 having the air gap structure 223 at least at the gap (not labeled).

[0080] The side wall of the second groove T2 is recessed inward by a preset length L relative to the side wall of the first groove T1. In one embodiment, the ratio of the preset length L to the width of the word line layer WL is between 1:7 and 1:4, for example, 1:8 to 1:5.

[0081] In one embodiment, the number of the word line layers WL is multiple. The multiple word line layers WL extend in the same direction in the active region AA and the isolation region 23, and the word line layer WL has a uniform height in the extending direction. The material of the word line layer WL includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination thereof. In a specific embodiment, the second sub-part WL2 has a uniform height and width in the extending direction, and the width of the top of the first sub-part WL1 is equal to the width of the second sub-part WL2.

[0082] In one embodiment, the word line capping layer 22 includes a first sub-layer 221, a second sub-layer 222 located on the first sub-layer 221, and the air gap structure 223 sandwiched between the first sub-layer 221 and the second sub-layer 222; wherein, the first sub-layer 221 covers the side wall and the bottom surface of the first groove T1 and covers the side wall and the upper surface of the second sub-part WL2.

[0083] The material of the first sub-layer 221 can be a dielectric material, specifically a nitride, such as silicon nitride. In some embodiments, the second sub-layer 222 and the first sub-layer 221 are formed of the same material.

[0084] In one embodiment, the air gap structure 223 in the word line capping layer 22 extends from the gap (not labeled) to above the second sub - portion WL2, surrounding the sidewall and the upper surface of the second sub - portion WL2. The extension of the air gap structure 223 above the second sub - portion WL2 can further reduce the dielectric constant of the word line capping layer 22, thereby reducing the electric field strength between the second sub - portion WL2 of the word line layer WL and the substrate 20, effectively enhancing the control of the word line layer WL over the channel, improving the transistor's ability to drive current, and further effectively reducing the GIDL effect and improving the reliability of the semiconductor device.

[0085] In one embodiment, the air gap structure 223 located at the gap (not labeled) has a uniform first width L1 along the extending direction of the word line layer WL, and the ratio of the first width L1 to the width of the word line layer WL is between 1:10 and 1:5.

[0086] In one embodiment, the air gap structure 223 located above the second sub - portion WL2 has a uniform second width L2 along the extending direction of the word line layer WL, and the ratio of the second width L2 to the width of the word line layer WL is between 5:4 and 3:2.

[0087] In one embodiment, the air gap structure 223 located above the second sub - portion WL2 has a uniform first height H1 along the extending direction of the word line layer WL, and the ratio of the first height H1 to the height of the word line layer WL is between 1:20 and 1:10.

[0088] In one embodiment, the semiconductor device further includes: a dielectric layer 21, which is located in the second groove T2 and covers the sidewall and the bottom surface of the second groove T2, for separating the substrate 20 and the word line layer WL. In a specific embodiment, the thickness of the dielectric layer 21 is less than the preset length L. The material of the dielectric layer 21 includes but is not limited to oxides, such as silicon oxide.

[0089] In a more specific embodiment, the dielectric layer 21 is formed by in - situ thermal oxidation to convert part of the active region AA into an oxide.

[0090] It can be seen that the air gap structure 223 reduces the dielectric constant of the word line capping layer 22, thereby reducing the electric field strength generated between the second sub - portion WL2 of the word line layer WL and the first source / drain doping region d1 and the second source / drain doping region d2, effectively enhancing the control of the word line layer WL over the channel, improving the transistor's ability to drive current, and further effectively reducing the GIDL effect and improving the reliability of the semiconductor device.

[0091] The embodiments of the present application also provide a manufacturing method of a semiconductor device, as Figure 4 shown, the method includes the following steps:

[0092] Step 401: Form a first groove in the substrate;

[0093] Step 402: Etch the substrate downward from a partial bottom surface of the first groove to form a second groove, and a side wall of the second groove is recessed inward by a preset length relative to a side wall of the first groove;

[0094] Step 403: Form a word line layer in the first groove and the second groove, the word line layer includes a first sub - part located in the second groove and a second sub - part located in the first groove; wherein, there is a gap between a side wall of the second sub - part and a side wall of the first groove;

[0095] Step 404: Form a word line capping layer in the first groove; wherein, an air gap structure is formed at least at the gap in the word line capping layer.

[0096] Next, in combination with Figures 5a-5k further detailed description of the manufacturing method of the semiconductor device provided by the embodiments of the present application will be made.

[0097] First, execute Step 401 to form a first groove T1 in the substrate 20, as Figure 5a shown.

[0098] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III - V compound semiconductor material, at least one II - VI compound semiconductor material, at least one organic semiconductor material or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate, and the silicon substrate may be doped or undoped.

[0099] In one embodiment, the substrate 20 includes isolation regions 23 and active regions AA defined by the isolation regions 23.

[0100] Specifically, as Figure 2 shown, the substrate 20 includes a plurality of parallel - arranged active regions AA, and the isolation regions 23 are disposed between the plurality of active regions AA. The material of the isolation regions 23 may include one or more of oxides (such as silicon oxides), nitrides (such as silicon nitrides), and oxynitrides (such as silicon oxynitrides).

[0101] Specifically, a first groove T1 is formed in the substrate 20, including: forming a patterned mask (not shown in the figure) on the substrate 20, and using the patterned mask (not shown in the figure) as an etching mask to perform an etching process on the isolation region 23 and the active region AA to form the first groove T1. In some embodiments, the etching process includes but is not limited to a dry etching process, such as a plasma etching process.

[0102] In one embodiment, the number of the first grooves T1 is multiple, and the multiple first grooves T1 extend in the same direction on the substrate 20, and the first grooves T1 have a uniform height and width along the extending direction.

[0103] The multiple first grooves T1 intersect with the active region AA and divide the top of the active region AA into multiple parts. In a specific embodiment, a pair of the first grooves T1 divides the top of the active region AA into three parts, and the two end portions and the middle region of the top of the active region AA are spaced apart by the first grooves T1. Specifically, refer to Figure 2 .

[0104] Next, step 402 is performed to etch the substrate 20 downward from a partial bottom surface of the first groove T1 to form a second groove T2, and the side wall of the second groove T2 is recessed inward by a preset length L relative to the side wall of the first groove T1, as Figures 5b-5c shown.

[0105] Specifically, etching the substrate 20 downward from a partial bottom surface of the first groove T1 to form the second groove T2 includes:

[0106] Filling the first groove T1 with an insulating material 24, as Figure 5b shown;

[0107] Removing a part of the insulating material 24 to form a first opening R1 exposing the partial bottom surface of the first groove T1, and the distance between the side wall of the first opening R1 and the side wall of the first groove T1 is the preset length L; etching the substrate 20 downward from the first opening R1 to form the second groove T2, as Figure 5c shown.

[0108] The insulating material 24 can be formed in the multiple first grooves T1 by processes such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). Optionally, after the insulating material 24 is formed in the first groove T1, a planarization process, such as chemical mechanical polishing (CMP) and / or an etching process, can be used to make the upper surface of the insulating material 24 coplanar with the upper surface of the substrate 20. In one embodiment, the insulating material 24 includes a nitride, such as silicon nitride.

[0109] In one embodiment, the first opening R1 and the second groove T2 can be formed in a single etching process, and the etching process includes but is not limited to dry etching, such as, plasma etching process.

[0110] In one embodiment, the first opening R1, the second groove T2 and the first groove T1 have the same extending direction, and the first opening R1 has a uniform height and width in the extending direction.

[0111] The side wall of the second groove T2 is recessed inward by a preset length L relative to the side wall of the first groove T1. In a specific embodiment, the ratio of the preset length L to the width of the first opening R1 is between 1:7 and 1:4, for example, 1:8 to 1:5.

[0112] Next, step 403 is executed to form a word line layer WL in the first groove T1 and the second groove T2. The word line layer WL includes a first sub - portion WL1 located in the second groove T2 and a second sub - portion WL2 located in the first groove T1. Wherein, there is a gap (not labeled) between the side wall of the second sub - portion WL2 and the side wall of the first groove T1, as Figures 5e-5f shown.

[0113] Specifically, please refer to Figure 5e , forming a word line layer WL in the first groove T1 and the second groove T2 includes:

[0114] Depositing a conductive material in the second groove T2 to form the first sub - portion WL1 of the word line layer WL;

[0115] Continuing to deposit the conductive material in the first opening R1 and performing an etch - back process to remove part of the conductive material in the first opening R1 to form the second sub - portion WL2 of the word line layer WL. It can be seen that the gap (not labeled) filled with the insulating material 24 is located outside the first opening R1 and will not affect the deposition of the conductive material. Therefore, it is beneficial to form a word line layer WL with a lower porosity.

[0116] The conductive material includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination thereof. The conductive material can be formed in the second groove T2 and the first opening R1 by processes such as chemical vapor deposition (CVD), plasma - enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, etc.

[0117] Specifically, the back etching process includes, but is not limited to, a wet etching process. For example, etching is performed using a mixed solution containing ammonium hydroxide and hydrogen peroxide.

[0118] The second sub - part WL2 has a uniform height and width in the extending direction, and the width at the top of the first sub - part WL1 is equal to the width of the second sub - part WL2.

[0119] In one embodiment, after forming the second sub - part WL2 of the word - line layer WL, it further includes: removing the remaining insulating material 24 in the first groove T1 to form the gap (not labeled), as Figure 5f shown. In some embodiments, the process of removing the insulating material 24 includes, but is not limited to, a wet etching process. For example, etching is performed using an etching solution containing phosphoric acid.

[0120] In one embodiment, before forming the word - line layer WL in the first groove T1 and the second groove T2, the method further includes: forming a dielectric layer 21 in the second groove T2, and the dielectric layer 21 covers the side walls and the bottom surface of the second groove T2, and is used to separate the substrate 20 and the word - line layer WL, as Figure 5d shown. In a specific embodiment, the thickness of the dielectric layer 21 is less than the preset length L.

[0121] Optionally, the dielectric layer 21 can be formed by in - situ thermal oxidation to convert part of the active region AA into an oxide. The material of the dielectric layer 21 includes, but is not limited to, silicon oxide.

[0122] Finally, step 404 is executed to form a word - line capping layer 22 in the first groove T1; wherein, the word - line capping layer 22 has an air - gap structure 223 formed at least at the gap (not labeled), as Figures 5g-5k shown.

[0123] In one embodiment, the word - line capping layer 22 includes a first sub - layer 221, a second sub - layer 222 located on the first sub - layer 221, and the air - gap structure 223 sandwiched between the first sub - layer 221 and the second sub - layer 222; forming the word - line capping layer 22 in the first groove T1 includes:

[0124] Forming the first sub - layer 221 in the first groove T1, and the first sub - layer 221 covers the side walls and the bottom surface of the first groove T1, and covers the side walls and the upper surface of the second sub - part WL2, as Figure 5g shown;

[0125] Forming a sacrificial layer 25 on the first sub - layer 221, and the sacrificial layer 25 at least fills the gap (not labeled), as Figure 5h shown;

[0126] Form the second sub-layer 222 on the sacrificial layer 25, as Figure 5i shown;

[0127] Remove the sacrificial layer 25 to form the air gap structure 223, as Figures 5j-5k shown.

[0128] The material of the first sub-layer 221 is a dielectric material, specifically it can be a nitride, such as silicon nitride. In some embodiments, the second sub-layer 222 and the first sub-layer 221 are formed of the same material. The formation processes of the first sub-layer 221 and the second sub-layer 222 include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.

[0129] The sacrificial layer 25 can be formed in the first groove T1 by processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. Optionally, after forming the sacrificial layer 25 in the first groove T1, a wet etching process can be used to remove part of the sacrificial layer 25 so that the sacrificial layer 25 at least fills the gap (not labeled). The material of the sacrificial layer 25 is different from the materials of the first sub-layer 221 and the second sub-layer 222. In a specific embodiment, the material of the sacrificial layer 25 can be an oxide, such as silicon oxide, and the wet etching process can be etching with an etching solution containing hydrofluoric acid.

[0130] In one embodiment, removing the sacrificial layer 25 includes: forming at least one second opening R2 on the second sub-layer 222 to expose the sacrificial layer 25, as Figure 5j shown, the second opening R2 can be formed by a dry etching process, such as a plasma etching process; removing the sacrificial layer 25 by a wet etching process, as Figure 5k shown, the wet etching process can be etching with an etching solution containing hydrofluoric acid.

[0131] In a specific embodiment, the bottom of the second opening R2 can penetrate into the sacrificial layer 25 to increase the contact area between the etching solution and the sacrificial layer 25, so as to remove the sacrificial layer 25 faster.

[0132] The second opening R2 is formed on the second sub-layer 222 located in the isolation region 23, as Figure 2 shown.

[0133] In one embodiment, the sacrificial layer 25 not only fills the gap (not labeled), but also covers the upper surface of the second sub - portion WL2, such that the finally - formed air - gap structure 223 extends from the gap (not labeled) to above the second sub - portion WL2, surrounding the sidewalls and the upper surface of the second sub - portion WL2 with the air - gap structure 223. The extension of the air - gap structure 223 above the second sub - portion WL2 can further reduce the dielectric constant of the word - line capping layer 22, thereby reducing the electric - field strength between the second sub - portion WL2 and the substrate 20, effectively enhancing the control of the word - line layer WL over the channel, improving the ability of the transistor to drive current, and further effectively reducing the GIDL effect and improving the reliability of the semiconductor device.

[0134] In one embodiment, the air - gap structure 223 located at the gap (not labeled) has a uniform first width L1 along the extending direction of the word - line layer WL, and the ratio of the first width L1 to the width of the word - line layer WL is between 1:10 and 1:5.

[0135] In one embodiment, the air - gap structure 223 located above the second sub - portion WL2 has a uniform second width L2 along the extending direction of the word - line layer WL, and the ratio of the second width L2 to the width of the word - line layer WL is between 5:4 and 3:2.

[0136] In one embodiment, the air - gap structure 223 located above the second sub - portion WL2 has a uniform first height H1 along the extending direction of the word - line layer WL, and the ratio of the first height H1 to the height of the word - line layer WL is between 1:20 and 1:10.

[0137] In one embodiment, the manufacturing method further includes performing an ion - implantation process on the substrate 20 to form a first source / drain doping region d1 and a second source / drain doping region d2 at the top of the active region AA, and finally forming a semiconductor device as Figure 3 shown. In a specific embodiment, the first source / drain doping region d1 is located in the middle region of the active region AA, the second source / drain doping region d2 is located at two ends of the active region AA, and the first source / drain doping region d1 and the second source / drain doping region d2 are separated by the word - line layer WL and the word - line capping layer 22 located on the word - line layer WL.

[0138] In a more specific embodiment, the first source / drain doping region d1 and the second source / drain doping region d2 have the same conductivity type, such as n - type. It can be understood that when the first source / drain doping region d1 and the second source / drain doping region d2 are n - type doped, the substrate 20 located below the first source / drain doping region d1 and the second source / drain doping region d2 has p - type doping.

[0139] In one embodiment, the lower surfaces of the first source / drain doping region d1 and the second source / drain doping region d2 are flush with or higher than the bottom surface of the first groove T1, that is, the lower surfaces of the first source / drain doping region d1 and the second source / drain doping region d2 are flush with or higher than the lower surface of the second sub-part WL2.

[0140] In this way, the air gap structure 223 reduces the dielectric constant of the word line capping layer 22, thereby reducing the electric field strength generated between the second sub-part WL2 of the word line layer WL and the first source / drain doping region d1 and the second source / drain doping region d2, effectively enhancing the control of the word line layer WL over the channel, improving the ability of the transistor to drive current, further effectively reducing the GIDL effect, and improving the reliability of the semiconductor device.

[0141] The above is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate, a first groove and a second groove located in the substrate; wherein, the second groove is formed by etching the substrate downward from a partial bottom surface of the first groove, and a side wall of the second groove is recessed inward by a preset length relative to a side wall of the first groove; A word line layer, including a first sub - part located in the second groove and a second sub - part located in the first groove; wherein, there is a gap between a side wall of the second sub - part and a side wall of the first groove; A word line capping layer, located in the first groove and covering the second sub - part; wherein, an air - gap structure is provided in the word line capping layer at least at the gap; Wherein, the word line capping layer includes a first sub - layer, a second sub - layer located on the first sub - layer, and the air - gap structure sandwiched between the first sub - layer and the second sub - layer; wherein, the first sub - layer covers a side wall and a bottom surface of the first groove, and covers a side wall and an upper surface of the second sub - part.

2. The semiconductor device according to claim 1, wherein A ratio of the preset length to a width of the word line layer is between 1:7 and 1:

4.

3. The semiconductor device according to claim 1, wherein The air - gap structure in the word line capping layer extends from the gap to above the second sub - part, so that the side wall and the upper surface of the second sub - part are surrounded by the air - gap structure.

4. The semiconductor device according to claim 3, wherein, The air - gap structure located at the gap has a uniform first width along a direction in which the word line layer extends, and a ratio of the first width to the width of the word line layer is between 1:10 and 1:

5.

5. The semiconductor device according to claim 3, wherein, The air - gap structure located above the second sub - part has a uniform second width along a direction in which the word line layer extends, and a ratio of the second width to the width of the word line layer is between 5:4 and 3:

2.

6. The semiconductor device according to claim 5, wherein, The air - gap structure located above the second sub - part has a uniform first height along a direction in which the word line layer extends, and a ratio of the first height to a height of the word line layer is between 1:20 and 1:

10.

7. The semiconductor device according to claim 1, wherein The first sub - layer and the second sub - layer are formed of the same material.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: a dielectric layer, the dielectric layer is located in the second groove, and covers a side wall and a bottom surface of the second groove.

9. The semiconductor device according to claim 8, wherein, A thickness of the dielectric layer is less than the preset length.

10. A method for manufacturing a semiconductor device, characterized in that, The method includes: Forming a first groove in a substrate; Etching the substrate downward from a partial bottom surface of the first groove to form a second groove, and a side wall of the second groove is recessed inward by a preset length relative to a side wall of the first groove; Forming a word line layer in the first groove and the second groove, the word line layer including a first sub - part located in the second groove and a second sub - part located in the first groove; wherein, there is a gap between a side wall of the second sub - part and a side wall of the first groove; Forming a word line capping layer in the first groove; wherein, an air - gap structure is formed at least at the gap in the word line capping layer; Wherein, the word line capping layer includes a first sub - layer, a second sub - layer located on the first sub - layer, and the air - gap structure sandwiched between the first sub - layer and the second sub - layer; forming a word line capping layer in the first groove includes: The first sub-layer is formed in the first groove, the first sub-layer covering the sidewall and the bottom surface of the first groove, and covering the sidewall and the upper surface of the second sub-part; A sacrificial layer is formed on the first sub-layer, the sacrificial layer at least filling the gap; The second sub-layer is formed on the sacrificial layer; The sacrificial layer is removed to form the air gap structure.

11. The manufacturing method according to claim 10, characterized in that, Etching the substrate downward from a partial bottom surface of the first groove to form a second groove, including: Filling the first groove with an insulating material; Removing a part of the insulating material to form a first opening exposing the partial bottom surface of the first groove, the distance between the sidewall of the first opening and the sidewall of the first groove being the preset length; Etching the substrate downward from the first opening to form the second groove.

12. The manufacturing method according to claim 11, characterized in that, Forming a word line layer in the first groove and the second groove, including: Depositing a conductive material in the second groove to form the first sub-part of the word line layer; Continuing to deposit the conductive material in the first opening and performing an etch-back process to remove a part of the conductive material in the first opening to form the second sub-part of the word line layer.

13. The manufacturing method according to claim 12, characterized in that, After forming the second sub-part of the word line layer, it further includes: Removing the remaining insulating material in the first groove to form the gap.

14. The manufacturing method according to claim 10, characterized in that, Removing the sacrificial layer, including: Forming at least one second opening on the second sub-layer to expose the sacrificial layer; Removing the sacrificial layer by a wet etching process.

15. The manufacturing method according to claim 14, characterized in that, The substrate includes an isolation region and an active region defined by the isolation region; wherein, the second opening is formed on the second sub-layer located in the isolation region.

16. The manufacturing method according to claim 10, characterized in that, Before forming the word line layer in the first groove and the second groove, the method further includes: forming a dielectric layer in the second groove, the dielectric layer covering the sidewall and the bottom surface of the second groove.

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