Electronic device comprising a transistor

Abstract

Embodiments of the present disclosure relate to electronic devices including transistors. The invention relates to an electronic device comprising a semiconductor substrate and transistors, the gates of which are comprised in trenches extending into the semiconductor substrate, each transistor comprising a first conductivity type doped semiconductor well, which is embedded in the semiconductor substrate and which is in contact with two adjacent ones of said trenches, a first doped semiconductor region of a second conductivity type, which covers the well, which is in contact with the well and which is in contact with the two adjacent trenches, a second doped semiconductor region of the second conductivity type, which is more heavily doped than the first semiconductor region, which extends in the first semiconductor region, and a third doped semiconductor region of the first conductivity type, which is more heavily doped than the well, which covers the well, which is in contact with the first region and which extends in the semiconductor substrate in contact with the well.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. 21 / 11151 entitled “ELECTRONIC DEVICE COMPRISINGTRANSISTORS”, filed on October 20, 2021, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic devices, and more specifically to electronic devices including transistors. Background Technology

[0004] In some electronic devices, field-effect transistors (FETs) are used to block high voltages, typically greater than 10V, such as about 40V, or even greater than 100V, in a non-conductive state. These FETs are generally only used to block high drain-source voltages when the drain-source voltage is positive. To achieve blocking of either positive or negative voltages, two FETs connected in anti-parallel may be required. This can be bulky and expensive. Summary of the Invention

[0005] One embodiment provides an electronic device that overcomes all or some of the shortcomings of existing electronic devices.

[0006] According to one embodiment, the surface area occupied by the field-effect transistor is reduced.

[0007] According to one embodiment, the manufacturing cost of field-effect transistors is reduced.

[0008] One embodiment provides an electronic device comprising a semiconductor substrate having a first surface and transistors, the gates of the transistors being contained in trenches extending in the semiconductor substrate, each transistor including a doped semiconductor well of a first conductivity type in the semiconductor substrate, a transistor channel being formed in the doped semiconductor well pool during operation, the wells being buried in the semiconductor substrate and contacting two adjacent trenches between the trenches, a first doped semiconductor region of a second conductivity type covering and contacting the wells, and contacting two adjacent trenches, the second conductivity type being opposite to the first conductivity type, a second doped semiconductor region of the second conductivity type being more heavily doped than the first semiconductor region, extending into the first semiconductor region and exposed on the first surface, and a third doped semiconductor region of the first conductivity type being more heavily doped than the wells and covering the wells, exposed on the first surface, contacting the first region, and extending in the semiconductor substrate contacting the wells.

[0009] According to one embodiment, the second semiconductor region is in contact with two adjacent trenches.

[0010] According to one embodiment, the third semiconductor region is in contact with two adjacent trenches.

[0011] According to one embodiment, the first semiconductor region includes a first semiconductor sub-region containing a second semiconductor region and at least one second semiconductor sub-region exposed on a first surface and coupled to a third semiconductor region, wherein the maximum depth of the first semiconductor sub-region is greater than the maximum thickness of the second semiconductor region.

[0012] According to one embodiment, each transistor includes, within a trench containing a transistor gate:

[0013] A first electrically insulating layer between the transistor gate (120) and the semiconductor well, thereby forming the gate insulator of the transistor;

[0014] Conductive elements located in the trench;

[0015] A second electrically insulating layer between the conductive element and the semiconductor substrate; and

[0016] A third electrically insulating layer between the conductive element and the gate.

[0017] According to one embodiment, the second semiconductor regions of the transistor are electrically connected together, and the third semiconductor regions of the transistor are electrically connected together.

[0018] According to one embodiment, the semiconductor substrate includes a second surface opposite to the first surface, and each transistor further includes a fourth doped semiconductor region of a second conductivity type in the semiconductor substrate, the fourth doped semiconductor region being covered by and in contact with the well, and a fifth doped semiconductor region of a second conductivity type, which is more heavily doped than the fourth semiconductor region and exposed on the second surface.

[0019] According to one embodiment, the electronic device includes a plurality of transistors for each pair of adjacent trenches, wherein at least some third semiconductor regions of the transistors alternate with second semiconductor regions of the transistors.

[0020] According to one embodiment, the wells of two adjacent transistors intersect.

[0021] One embodiment also provides a method for manufacturing an electronic device as defined above, wherein the formation of a first semiconductor region includes the steps of forming a doped semiconductor layer of a second conductivity type by epitaxy, and implanting a dopant of the second conductivity type into the semiconductor layer. Attached Figure Description

[0022] The above-described features and advantages, as well as other features and advantages, will be described in detail in the following specific embodiments given by way of illustration, and are not limited to the accompanying drawings, wherein:

[0023] Figure 1A This is a partial simplified cross-sectional view of an embodiment of an electronic device containing transistors;

[0024] Figure 1B yes Figure 1A Another simplified cross-sectional view of the device;

[0025] Figure 1C yes Figure 1A Another simplified cross-sectional view of the device;

[0026] Figure 1D yes Figure 1A A simplified top view of part of the device;

[0027] Figure 2 yes Figures 1A to 1D A simplified cross-sectional perspective view of the device;

[0028] Figure 3A Is with Figure 1A A similar simplified cross-sectional view illustrates the connection between the source and the well of the transistor;

[0029] Figure 3B It is another simplified cross-sectional view, similar to Figure 1B This illustrates an embodiment of transistor gate connection;

[0030] Figure 4 This is a simplified top view illustrating a transistor connection embodiment;

[0031] Figure 5 This is a partially simplified top view illustrating another embodiment of transistor interconnection;

[0032] Figure 6 Manufacturing process is shown Figures 1A to 1D The steps of an embodiment of the method using the device shown in Figure 2;

[0033] Figure 7 This explains another step of the method;

[0034] Figure 8 This explains another step of the method;

[0035] Figure 9 This explains another step of the method;

[0036] Figure 10 This explains another step of the method;

[0037] Figure 11 This explains another step of the method;

[0038] Figure 12 Another step of the method is illustrated using three views;

[0039] Figure 13 Another step of the method is illustrated using three views;

[0040] Figure 14 Another step of the method is illustrated using three views;

[0041] Figure 15 yes Figures 1A to 1D The cross-sectional perspective view of the device shown illustrates an example of dopant concentration variation;

[0042] Figure 16 It is similar to another direction. Figure 15 The view;

[0043] Figure 17 It shows how to obtain Figure 15 and Figure 16 The curves showing the change in dopant concentration obtained from manufacturing steps performed with varying dopant concentrations are shown.

[0044] Figure 18 It shows Figures 1A to 1D The curve showing the variation of the transistor on-state resistance Ron of the device is shown.

[0045] Figure 19 yes Figures 1A to 1D The cross-sectional view of the device shown illustrates the change in current density during initial use.

[0046] Figure 20 yes Figures 1A to 1D The cross-sectional perspective view of the device shown illustrates the variation in current density in the first usage configuration;

[0047] Figure 21 It is similar to the second usage configuration. Figure 19 The view;

[0048] Figure 22 It is the same as the second usage configuration. Figure 20 Similar views;

[0049] Figure 23 It is similar to the third type of configuration. Figure 19 The view; and

[0050] Figure 24 It is in the third usage configuration Figure 20 A similar view. Detailed Implementation

[0051] In different figures, similar features are designated by similar reference numerals. In some embodiments, structural and / or functional features common in different embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties. For clarity, only steps and elements that aid in understanding the embodiments described herein are described in detail. In some embodiments, mask fabrication steps, doping steps, and fabrication terminals electrically connected to the doped regions are not described in detail, and the described embodiments are compatible with these common steps.

[0052] Unless otherwise stated, when referring to two elements connected together, it means a direct connection without any intermediate elements (other than conductors); when referring to two elements coupled together, it means that the two elements can be connected or coupled through one or more other elements. Furthermore, the terms "insulating" and "conductive" are considered here to refer to "electrically insulating" and "electrically conducting," respectively.

[0053] In the following description, when referring to terms that define absolute position, such as “front,” “back,” “up,” “down,” “left,” “right,” etc., or terms that define relative position, such as “above,” “below,” “above,” and “below,” etc., or terms that define direction, such as “horizontal,” “vertical,” etc., they shall conform to the orientation shown on the drawing or the normal use position as indicated on the screen, unless otherwise specified.

[0054] Unless otherwise specified, the terms “around,” “approximate,” “substructively,” and “order of” indicate within 10%, and in some embodiments within 5%. Unless otherwise specified, ordinal numbers such as “first,” “second,” etc., are used only to distinguish elements. In some embodiments, these adjectives do not limit the described embodiments to a specific order of these elements.

[0055] Figure 1A , 1B Figures 1C and 1D show the cross-sectional view and top view, respectively, in a partial and schematic manner. Figure 2 This is a perspective view of an embodiment of a device 100 containing multiple transistors T. (Cross-section) Figure 1B and 1C Each of its respective cross-sections has parallel planes 1B-1B and 1C-1C. The transistor T section is as follows... Figures 1A to 1D As shown in Figure 2.

[0056] For example, device 100 is an electronic integrated circuit defined by a semiconductor substrate 102, which includes a front end 104 and a back end 106, not in... Figures 1A to 1D As shown in Figure 2 and described below Figure 3Aand 3B As shown, opposite to the front end 104, transistor T is located inside and on top of substrate 102.

[0057] Transistor T is defined by trench 110, with four parallel trenches 110 as follows: Figures 1B to 1D As shown in Figure 2, each trench 110 extends from the front side 104 of the substrate 102 into a portion of the thickness of the substrate 102.

[0058] Each transistor T specifically includes:

[0059] Gate 120 located in one of the trenches 110;

[0060] A doped semiconductor well 130 of a first conductivity type is buried in the substrate 102, separated from the gate 120 by a gate insulator 124, and the channel of the transistor T is formed therein. The well 130 is coupled to the front side 104 through a semiconductor contact region 132 extending from the front side 104 into the substrate 102.

[0061] Drain / source semiconductor regions 140 and 150 are doped with a second conductivity type, which is opposite to the first conductivity type, and are located on either side of the well 130. Doped region 140, also called the drain region, is not... Figures 1A to 1D and Figure 2 As shown in the figure and described below Figure 3A and 3B As shown, a doped region 150, also known as a source region, contacts the back side 106 of the substrate 102; and a doped region 150, also known as a source region, contacts the front side 104 of the substrate 102; and

[0062] Semiconductor regions 142 and 152 are called drift regions, which are doped with a second conductivity type and have a lower doping degree than doped regions 140 and 150. Drift region 142 is located between doped region 140 and well 130, and semiconductor region 152 is located between doped region 150 and well 130.

[0063] Thus, each transistor T defined by the above-mentioned elements forms a field-effect transistor, that is, according to the control voltage applied between the gate 120 and the source region 150, a conductive channel can be formed in the well 130 to electrically connect the electronic components of the drain and source regions 140 and 150.

[0064] Each transistor T has a gate 120 including at least one conductive region, such as metal and / or doped polysilicon, extending in a trench 110. The sidewalls of the trench 110 form the sides of a well 130 of the transistor T. A gate insulator 124 covers the sides of the trench 110 and contacts the conductive regions of the well 130 and the gate 120. The gate insulator 124 is typically formed of one or more dielectric layers; for example, the gate insulator is formed of a silicon oxide layer. The thickness of the gate insulator 124 is typically less than 15 nm, but in some embodiments ranges from 20 nm to 40 nm.

[0065] The number and size of the trenches 110 depend on the intended application. The depth of each trench 110 can be between 1.7 µm and 2.5 µm, for example, approximately equal to 2 µm. For example, the width of each trench 110 can be between 0.1 µm and 1 µm, for example, equal to 0.6 µm. In some embodiments, the trenches 110 extend at least partially along a direction parallel to the same direction, hereinafter referred to as the longitudinal trench direction, and are regularly spaced. Hereinafter, the transverse trench direction refers to a direction perpendicular to the longitudinal trench direction. The trench pitch along the transverse trench direction can be between 0.9 µm and 1.2 µm. The number of trenches 110 can range from 1000 to 3000. The length of each trench 110 along the longitudinal trench direction may range from 0.5 µm to 3 µm.

[0066] According to one embodiment, such as Figure 1B and Figure 2 As shown, each trench 110 of the parallel adjacent trench 110 assembly (possibly except for trenches 110 located at the two opposite edges of the trench assembly 110) defines a transistor T on both sides of the trench 110. According to a specific embodiment, see... Figure 1D and Figure 2 For each trench 110, the gates 120 contained in the trench 110 are connected to each other and form a common gate 120 shared by the transistors T separated by the trench 110. According to one embodiment, for each trench 110, the semiconductor wells 130 of the transistors T separated by the trench 110 and located on the same side of the trench 110 intersect to form a continuous semiconductor well 130.

[0067] In one example, substrate 102 is formed of a semiconductor wafer, such as a silicon wafer. In another example, the substrate is formed of a layer located on the surface of the semiconductor wafer, such as an epitaxial layer on the semiconductor wafer. In some embodiments, substrate 102 is a single-crystal substrate.

[0068] According to one embodiment, such as Figure 1B and 1CAs shown, each well 130 located between the first and second adjacent trenches 110 extends from the first trench 110, contacting the gate insulator 124 covering the sidewalls of the first trench 110, and extends into the second trench, contacting the gate insulator 124 covering the sidewalls of the second trench 110. The depth of the contact region 132, measured from the front side 104, can range from 0.4 µm to 0.8 µm. The maximum depth of the well 130, measured from the front side 104, can range from 0.8 µm to 1.2 µm. The thickness of the well 130 under the drift region 152, measured in a direction orthogonal to the front side 104, can range from 0.5 µm to 0.8 µm. The maximum thickness of the well 130, measured in a direction orthogonal to the front side 104, can range from 1 µm to 1.3 µm. The dimension of the contact region 132 along the longitudinal trench direction can range from 0.5 µm to 1.5 µm.

[0069] According to one embodiment, such as Figure 1D As shown, each drift region 152 located between the first and second adjacent trenches 110 extends from the first trench 110 to the second trench, contacting the gate insulator 124 covering the sidewalls of the first trench 110 and the gate insulator 124 covering the sidewalls of the second trench 110. The drift region 152 includes a first drift sub-region 154 and two second drift sub-regions 156 connected to the first drift sub-region 154. The first drift sub-region 154 is less doped than the source region 150. The second drift sub-regions 156 are less doped than the source region 150; in some embodiments, the doping degree of the second drift sub-regions 156 is less than that of the first drift region 154. Each trench 110 of the first drift sub-region 154 and the second drift region 156, located between the first and second adjacent regions, extends from the first trench 110, contacts the gate insulator 124 covering the sidewalls of the first trench 110, and extends into the second trench, also contacting the gate insulator 124 covering the sidewalls of the second trench 110. A source region 150 is contained within the first drift sub-region 154. The first drift sub-region 154 completely covers the bottom of the source region 150. The first drift region 154 completely covers the sidewalls of the source region 150 between the first and second trenches 110. A second drift sub-region 156 is located on either side of the first drift region 154 along the longitudinal trench direction. Each second drift sub-region 156 extends from the first drift sub-region 154 along the longitudinal trench direction to an adjacent contact region 132. Each second drift region 156 may be exposed on the front side 104 of the substrate 102. In some embodiments, the source region 150 extends from the first trench 110, contacts the gate insulator 124 covering the sidewall of the first trench 110, extends to the second trench, and contacts the gate insulator 124 covering the sidewall of the second trench 110.

[0070] The depth of the first drift sub-region 154 can range from 0.4 µm to 0.6 µm. The depth of each second drift sub-region 156 can range from 0.3 µm to 0.6 µm. The maximum dimension of the drift region 152 along the longitudinal trench direction can range from 2 µm to 5 µm. The dimension of the first drift region 154 along the longitudinal trench direction can range from 1.5 µm to 4 µm. The dimension of each second drift region 156 along the longitudinal trench direction can range from 0.5 µm to 1 µm. The depth of the source region 150, measured from the first surface 104, can range from 0.2 µm to 0.4 µm.

[0071] For example, transistor T is an N-channel type. Therefore, doped regions 140 and 150 are N-type doped. Well 130 is P-type doped. However, in the described embodiment, the N and P conduction types or doping types can be interchanged. Then, by interchanged, an operation similar to the described operation can be obtained.

[0072] In some embodiments, regions 140 and 150 have high doping levels, i.e., greater than 5. 10 18 atoms / cm 3 In some embodiments, greater than 10 19 atoms / cm 3 The contact surface 132, electrically connected to the well 130, is also a doped region with such a high doping level. In some embodiments, the doping level of the well 130 is less than 10. 18 atoms / cm 3 In some embodiments, less than 5 10 17 atoms / cm 3 The doping level of each drift region 142, 152 is lower than the doping level of doped region 150. In some embodiments, each semiconductor region 142 and 152 has a low doping level, i.e., below 2. 10 17 atoms / cm 3 In some embodiments, the doping level is greater than 5. 10 16 atoms / cm 3 According to one embodiment, the doping level of each first drift sub-region 154 is 2. 10 17 atoms / cm 3 up to 6 10 17 atoms / cm 3 Within the range. According to one embodiment, the doping level of each second drift sub-region 156 is 3. 10 16atoms / cm 3 To 1 10 17 atoms / cm 3 Within the range.

[0073] For each trench 110, device 100 may further include a conductive element 180 located within the trench 110. The conductive element 180 is connected to a terminal, such as... Figures 1A to 1D and Figure 2 As shown. In some embodiments, the terminal is connected to contact region 132. A conductive element 180 is located opposite at least a portion of semiconductor region 142, that is, the conductive element 180 is located opposite an insulator 184 covering at least a portion of the sidewall surface of semiconductor region 142. The insulating layer 184 separates the conductive element 180 from semiconductor region 142, corresponding to the thickness of the insulating layer 184, for example, in the range of 100 nm to 200 nm, and in some embodiments in the range of 120 nm to 180 nm. In some embodiments, the thickness of the insulating layer 184 is greater than the thickness of gate insulator 124. For example, the insulating layer 134 is made of silicon oxide or silicon nitride.

[0074] At the bottom of trench 110, an insulating portion, in some embodiments part of insulating layer 184, lies below conductive element 180. This portion electrically insulates conductive element 180 from the substrate 102 portion beneath conductive element 180. Furthermore, insulating layer 186, in some embodiments made of the same material as gate insulator 124, electrically insulates conductive element 180 from gate 120.

[0075] In some embodiments, the conductive element 180 is formed of a conductive wall located at the center portion of the trench 110. This wall extends in the same direction as the trench. The wall extends perpendicularly to the front side 104 of the substrate 102. For example, in some embodiments, the wall comprises a metallic material, or in some embodiments, it comprises doped polysilicon. For example, the width of the conductive wall, measured laterally along the trench, is between 30 nm and 200 nm.

[0076] Device 100 also includes Figures 1A to 1D and Figure 2 Conductive tracks and conductive vias of at least one metallization layer (not shown) are formed on the front side 104 of the substrate 102 for connecting the source, gate, and well of the transistor T. According to one embodiment, the source regions 150 of the MOS transistor assembly are connected together. According to one embodiment, the gates 120 in the trench 110 are connected together. According to one embodiment, the contact regions 132 of the well 30 are connected together.

[0077] Figure 3A and 3B They are respectively with Figure 1Aand 1B Similar views illustrate connection embodiments of transistor T.

[0078] For example, device 100 Figure 3A and 3B As shown, there are two metallization levels N1 and N2. The first metallization level N1 includes an insulating layer 190 covering the front side 104 of the substrate 102, metal tracks 192 extending on the insulating layer 190, and a conductive via 194 passing through the insulating layer 190 and specifically connecting the metal tracks 192 to the gate 120, the source region 150, and the contact region 132. The second metallization level N2 includes an insulating layer 200 covering the insulating layer 190 between the conductive tracks 192 and 1922, metal tracks 202 extending on the insulating layer 200, and a conductive via 204 passing through the insulating layer 200 and connecting the metal tracks 2022 to at least some of the metal tracks 192.

[0079] The number of transistors T assembled in parallel depends on the target application. According to one embodiment, device 100 includes 3... 10 5 up to 3 10 6 One transistor T.

[0080] Figure 4 This is a top view of an embodiment illustrating the layout of conductive tracks 192 of a first metallization layer, which has the shape of parallel strips and plates. Figure 4 The limitations of trench 110, contact region 132, and source region 150 are further illustrated. The conductive via 194 is further shown as a square that may intersect a horizontal line. In this embodiment, trench 110 is parallel and extends uninterruptedly over the entire area where the transistor is formed. Figure 4 As shown, conductive tracks 192 are distributed in a conductive plate 192_S coupled to the source region 150 through conductive vias 194_S. Conductive track 192_B is coupled to the contact region 132 through vias 194_B, conductive track 192_G is coupled to the gate 120 through vias 194_G, and conductive track 192_M is coupled to the conductive element 180 through vias 194_M. In this embodiment, the plate 192_S and the track 192_B alternate. Figure 4 The conductive track 202 of the second metallization layer (not shown) can be used to connect the conductive plate 192_S.

[0081] Figure 5 This is a top view of an embodiment illustrating the layout of the conductive tracks 192 of the first metallization layer, which has the shape of parallel strips and plates. Figure 4The limitations of trench 110, contact region 132, and source region 150 are further illustrated. In this embodiment, trench 110 extends parallel to each other and is distributed in assemblies 112 of trench 110 over the transistor formation region. Each assembly 112 of trench 110 includes a first group and a second group 114, 116 of trench 110. The trenches of the first group 114 are offset relative to the trenches of the second group 116 by half the trench pitch in the lateral trench direction. The trenches of the first and second groups are coupled at one end to a trench 118 extending in the lateral trench direction. Conductive via 194 is represented by a square that may intersect a horizontal line. Figure 5 As shown, conductive tracks 192 are distributed in a conductive plate 192_S coupled to the source region 150 through conductive vias 194_S, and conductive tracks 192_MB are coupled to the contact region 132 and the conductive element 180 through vias 194_MB. The gate 120 can be connected in... Figure 5 It will be carried out in areas other than those mentioned above.

[0082] For example, in applications involving high-power integrated relays, the drain potential of transistor T operates in the range of 40 V to 45 V. When transistor T is in the on-state, the voltage between the gate and source of each transistor T is approximately 10 V, and the potential at the source is approximately 40 V-45 V. When transistor T is in the off-state, the voltage between the gate and source of each transistor T is approximately 0 V, and the potential at the source is approximately 0 V. The contact region 132 of the well 130 is set to 0 V, and the conductive element 180 is set to 0 V.

[0083] The presence of conductive element 180 advantageously reduces the electric field strength present during operation at the PN junction level. This allows for an increase in the doping concentration of drift regions 142 and 152 while ensuring that the transistor does not deteriorate when maximum voltage is applied.

[0084] Figures 6 to 14 Is Figures 1A to 1D A simplified cross-sectional view of the structural portion obtained in an embodiment of the manufacturing method of device 100. For Figure 12 , Figure 13 and Figure 14 This shows the cross-sectional view. Figure 1A , Figure 1B and Figure 1C Three similar cross-sectional views, A, B, and C.

[0085] Figure 6The diagram illustrates a structure obtained by forming a heavily doped drain region 140 of a second conductivity type (e.g., N-type doping) and a semiconductor layer 210 that is less doped than the drain region 140 in a substrate 102, having a doping concentration substantially corresponding to the doping concentration required for the drift region 142. The substrate 102 can be fabricated, for example, by epitaxially forming a less doped silicon semiconductor layer 210 on a heavily doped silicon wafer corresponding to the drain region 140.

[0086] Figure 7 The structure obtained after forming trench 110 in layer 310 of substrate 102 is shown. Trench 110 can be formed by an etching step.

[0087] Figure 8 The structure obtained after molding on the walls and bottom of each trench 110 is shown, along with the thickness of the insulating layer 212. The method may include conformal deposition of the insulating layer of the overlay structure formed by etching the trench 110. The composition and thickness of the insulating layer 212 correspond to the desired composition and thickness of the insulating layer 184. As a variant, the insulating layer 212 may be formed via a thermal oxidation step.

[0088] Figure 9 The structure obtained after forming a conductive core 214 in each trench 110 is shown. The method may include depositing a conductive layer, for example made of polysilicon, covering an insulating layer 212 and filling the remaining space in each trench 110, and removing portions of the conductive layer located outside the trench 110, for example, by etching. The composition of the conductive core 214 corresponds to the desired composition of the conductive element 180.

[0089] Figure 10 The structure obtained after etching at a portion of the depth of each trench 110, the insulating layer 212, and the conductive core 214 is shown. The conductive element 180 and the insulating layer 184 of the transistor are thus formed.

[0090] Figure 11 The structure obtained after forming an insulating layer 186, a gate insulator 124, and a gate 120 in each trench 110 is shown. The gate insulator 124 can be formed by thermal oxidation. The method may include depositing a conductive layer covering the insulating layer and filling the remaining space of each trench 110, and removing portions of the conductive layer located outside the trench 110 by means of etching or the like.

[0091] Figure 12 A cross-section is shown. Figure 12 In A, 12B, and 12C, the structure obtained after a dopant implantation step of the first conductivity type (e.g., P type) is used to form a well 130 of a transistor buried in the substrate 102.

[0092] Figure 13 In cross section Figure 13A, 13B, and 13C show the structure obtained after a first step of implanting a dopant of the second conductivity type to form a first drift subregion 154 in each transistor T, and a second step of implanting impurities of the second conductivity type to form a source region 150 in each transistor T.

[0093] Figure 14 A cross-section is shown. Figure 14 In A, 14B, and 14C, the structures obtained after the first conductivity dopant implantation step form contact region 132. This further defines a second drift sub-region 156 of the drift region 152 of each transistor T, thereby forming transistor T.

[0094] This method is carried out as the degree of metallization develops.

[0095] Figure 15 and 16 It is a cross-sectional perspective view along two different directions, as shown in the figure. Figures 1A to 1D The grayscale change of dopant concentration in device 100, which is based on a previous... Figures 6 to 14 The dopant concentration distribution is as described in the embodiments of the manufacturing method. Figure 17 As shown. In Figure 15 and 16 In the image, the gray shading becomes darker as the concentration of N-type or P-type dopant increases. Figure 15 and 16 The image shows only the semiconductor substrate 102 and a portion of the elements of a single transistor T. The outlines of the gate 120, conductive element 180, and the via 194 connected to the source region 150 and the contact region 132 of the transistor T are also partially shown.

[0096] exist Figure 17 In the figure, curves C1, C2, C3, and C4 represent the distribution of dopant concentration in substrate 102, expressed as atoms / cm². 3 This indicates the depth measured from the front side 104 of the source region 150 layer. For example, the substrate 102 can be fabricated on a heavily arsenic-doped (N-type dopant) silicon wafer corresponding to the drain region 140, for example, by epitaxy, where the semiconductor silicon layer 210 is more lightly doped with phosphorus (N-type dopant). Curve C1 is the curve showing the change in arsenic concentration in the substrate 102, and curve C2 is the curve showing the change in phosphorus concentration generated during the formation of layer 210. Curve C3 is the curve showing the change in boron concentration (P-type dopant) obtained after the implantation step when forming well 130. Curve C4 is the curve showing the change in boron concentration during the formation of well 130 and the phosphorus concentration obtained after the implantation step for forming the first drift sub-region 154. Figure 5 The curves not shown represent the changes in phosphorus concentration obtained after step 150, where phosphorus is injected to form the source region, including approximately 2 × 10⁻⁶.19 atoms / cm 3 The peak value is at a depth of approximately 50 nm, and the value is less than 1 × 10⁻⁶. 15 atoms / cm 3 The depth of the drop exceeds 350nm. For example... Figure 15 and 16 As shown, the N-type dopant concentration varies continuously between the first drift subregions 154 and 156 and the source region 150.

[0097] right Figures 1A to 1D The device 100 shown was simulated to highlight the characteristics of transistor T. For the simulation, device 100 has the characteristics previously described. Figures 15 to 17 The doping concentrations described are relevant. The simulations correspond to the normal operation of transistor T and the unfavorable potential conditions of the PN junction of transistor T. The simulations were performed at a temperature of 25°C.

[0098] Figure 18 The curve showing the variation of current density CD is presented in A / cm. 2 It indicates that the leakage voltage Vd flowing through the drain region 140 of transistor T in the on state is expressed in volts. Figure 19 , 21 23 is a cross-sectional view of a portion of transistor T. Figure 20 , 22 24 is a cross-sectional perspective view of the T section of transistor, with current density CD in A / cm². 2 This indicates that when the current density reaches extremely high or low values, the gray shading will be darker. For Figure 20 , 22 And 24, the current density CD is expressed in A / cm2. Figure 21 and 23 The equipotential lines of transistor T under different usage configurations are shown. Figure 21 and Figure 23 In this model, the dopant concentration is also expressed in grayscale, with the gray shades becoming darker as the concentration of N-type or P-type dopant increases.

[0099] Figures 18 to 20 The first simulation illustrates transistor T in the on-state. The drain voltage of transistor T is approximately 40 V, the voltage between the gate and source of transistor T is approximately 10 V, and the voltage at the source of transistor T is approximately 40 V. The on-resistance Ron is approximately equal to 6.3 mohms·mm², which has been determined. The presence of contact region 132 does not cause excessive degradation of the on-resistance Ron in the structure extending along the trench in the source region.

[0100] Figure 21 and 22A second simulation is shown, in which transistor T is in a non-conductive state, and the bias conditions of the PN junction between well 130 and drift region 142 are most unfavorable. The drain voltage of transistor T is approximately 40 V, the voltage between the gate and source of transistor T is approximately 0 V, and the voltage at the source of transistor T is approximately 0 V. The PN junction formed between well 130 and drift region 142 is reverse biased and can withstand the applied potential.

[0101] Figure 23 and Figure 24 The third simulation is illustrated, where transistor T is in a non-conductive state, and the bias conditions of the junction between well 130 and drift region 152 are the most unfavorable. The drain voltage of each transistor T is approximately 0V, the voltage between the gate and source of each transistor T is approximately 0V, and the voltage at the source of each transistor T is approximately 17V. The PN junction formed between well 130 and drift region 152 is reverse biased and can withstand the applied potential.

[0102] The transistor T described earlier is advantageously able to withstand the positive drain-source voltage and the negative drain-source voltage in a non-conductive state.

[0103] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and other variations will emerge. In some embodiments, transistor T is described as a drain region 140 located on the back side. As a variation, drift region 142 may contact a more heavily doped contact region located on the front side.

[0104] Finally, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional indications described above.

[0105] The electronic device (100) can be summarized as including a semiconductor substrate (102) having a first surface (104) and a transistor (T) having a gate (120) contained in a trench extending in a trench (110) of the semiconductor substrate. Each transistor includes a doped semiconductor well (130) of a first conductivity type in the semiconductor substrate, having a transistor channel formed therein, the well being buried in the semiconductor substrate and contacting two adjacent channels between the channels. A first doped semiconductor region (152) of a second conductivity type covers the well, contacts the well, and contacts two adjacent channels. The second conductivity type is opposite to the first conductivity type. The second doped semiconductor region (150) of the second conductivity type is more heavily doped than the first semiconductor region. The second doped semiconductor region extends in the first semiconductor region and is exposed on the first surface. A third doped semiconductor region (132) of the first conductivity type is more heavily doped than the well, covers the well, is exposed on the first surface, and contacts the first region and extends in the semiconductor substrate in contact with the well.

[0106] The second semiconductor region (150) can contact two adjacent trenches.

[0107] The third semiconductor region (132) can contact two adjacent trenches.

[0108] The first semiconductor region (152) may include a first semiconductor sub-region (154), the first semiconductor sub-region including the second semiconductor region (152) and at least one second semiconductor sub-region (156) exposed on the first surface (104) and coupled to the third semiconductor region (132), the maximum depth of the first semiconductor sub-region being greater than the maximum thickness of the second semiconductor sub-region.

[0109] In a trench (110) containing a transistor gate (120), each transistor (T) may include: a first electrically insulating layer (124) between the transistor gate (120) and a semiconductor well (130), and the first electrically insulating layer forms the gate insulator of the transistor; a conductive element (180) located in the trench (110); a second electrically insulating layer (184) between the conductive element and the semiconductor substrate; and a third electrically insulating layer (186) between the conductive element and the gate.

[0110] The second semiconductor region (150) of the transistor (T) can be electrically connected together, and the third semiconductor region (132) of the transistor (T) can be electrically connected together.

[0111] The semiconductor substrate (102) may include a second surface (106) opposite to the first surface (104), and each transistor may also include a fourth doped semiconductor region (142) of the second conductivity type in the semiconductor substrate, which is covered by the well (130) and in contact with the well, and a fifth doped semiconductor region of the second conductivity type, which is more heavily doped than the fourth semiconductor region and exposed on the second surface.

[0112] The electronic device may include a plurality of transistors (T) for each pair of adjacent trenches (110), at least some of the third semiconductor regions (132) of the transistors alternating with the second semiconductor regions (150) of the transistors.

[0113] The wells (130) of two adjacent transistors (T) can intersect.

[0114] A method for manufacturing an electronic device (100), wherein the formation of a first semiconductor region (152) can be summarized as including the steps of forming a doped semiconductor layer (210) of a second conductivity type by epitaxy, and implanting a dopant of the second conductivity type into the semiconductor layer.

[0115] The various embodiments described above can be combined to provide further embodiments. If necessary, aspects of the embodiments can be modified to employ the concepts of various embodiments to provide further embodiments.

[0116] Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, claims are not limited by disclosure.

Claims

1. An electronic device, comprising: A semiconductor substrate having a first surface; as well as transistor Its gate is contained in a trench extending in the semiconductor substrate, and each transistor includes: A first conductivity type of doped semiconductor well, having transistor channels, wherein the doped semiconductor well is buried in the semiconductor substrate and contacts two adjacent trenches between the trenches. The first doped semiconductor region of the second conductivity type, wherein the second conductivity type is opposite to the first conductivity type, and the first doped semiconductor region of the second conductivity type... The body region is in contact with the doped semiconductor well and with the two adjacent trenches. The second doped semiconductor region of the second conductivity type, having a heavier doping degree than the first doped semiconductor region, extends within the first doped semiconductor region and is exposed on the first surface. The third doped semiconductor region of the first conductivity type, having a heavier doping degree than the doped semiconductor well, is located within the doped semiconductor well and exposed on the first surface. The third doped semiconductor region of the first conductivity type is in contact with the first doped semiconductor region, and the third doped semiconductor region is in contact with the doped semiconductor well and extends within the semiconductor substrate. The first doped semiconductor region includes a first semiconductor sub-region and at least one second semiconductor sub-region, the first semiconductor sub-region containing the second doped semiconductor region, and the at least one second semiconductor sub-region being exposed on the first surface and coupling the first semiconductor sub-region to the third doped semiconductor region.

2. The electronic device of claim 1, wherein the second doped semiconductor region is in contact with the two adjacent trenches.

3. The electronic device according to claim 1, wherein the third doped semiconductor region is in contact with the two adjacent trenches.

4. The electronic device according to claim 1, wherein the maximum depth of the first semiconductor sub-region is greater than the maximum depth of the second semiconductor sub-region.

5. The electronic device of claim 1, wherein each transistor comprises, in a trench including the gate of the transistor: A first electrically insulating layer is located between the gate of the transistor and the doped semiconductor well. The conductive element is located in the trench; A second electrically insulating layer is disposed between the conductive element and the semiconductor substrate; as well as A third electrical insulating layer is located between the conductive element and the gate.

6. The electronic device of claim 1, wherein the second doped semiconductor regions of the transistor are electrically coupled together, and wherein the third doped semiconductor regions of the transistor are electrically coupled together.

7. The electronic device according to claim 1, wherein the semiconductor substrate comprises: A second surface, opposite to the first surface, and each transistor further includes a fourth doped semiconductor region of the second conductivity type in the semiconductor substrate, the fourth doped semiconductor region being located on and in contact with the doped semiconductor well, and The fifth doped semiconductor region of the second conductivity type is more heavily doped than the fourth semiconductor region and is exposed on the second surface.

8. The electronic device of claim 1, wherein for each pair of adjacent trenches, at least some of the third doped semiconductor regions of the transistor alternate with the second doped semiconductor regions of the transistor.

9. The electronic device of claim 8, wherein the doped semiconductor wells of two adjacent transistors of the transistor intersect.

10. A method for manufacturing an electronic device, comprising: Trenches are formed in a semiconductor substrate; A first insulating layer is formed on the sidewalls and bottom of the trench; A first conductive layer is formed on the first insulating layer and the trench is filled; Remove the upper portion of the first insulating layer and the first conductive layer; After removing the upper portion of the first insulating layer and the first conductive layer, a second insulating layer is formed on the first conductive layer and in the trench; A second conductive layer is formed on the second insulating layer; A first doped semiconductor region and a second doped semiconductor region are formed, each laterally adjacent to the trench. The first doped semiconductor region is at least partially within the second doped semiconductor region. The second doped semiconductor region includes a first portion in contact with the first doped semiconductor region and a second portion away from the first doped semiconductor region. The first portion extends deeper into the semiconductor substrate than the second portion. as well as A doped semiconductor well is formed laterally adjacent to the trench, wherein the first doped semiconductor region and the second doped semiconductor region are each at least partially within the doped semiconductor well.

11. The method for manufacturing an electronic device according to claim 10, comprising: A doped semiconductor layer of the first conductivity type is formed by epitaxy, and A dopant of the first conductivity type is implanted in the semiconductor substrate.

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