A semiconductor device and a manufacturing method thereof

Abstract

The embodiment of the present application provides a kind of semiconductor device and its manufacturing method, semiconductor device includes substrate, source electrode, drain electrode and channel structure being arranged in one side of substrate, channel structure is between source electrode and drain electrode, channel structure includes the stack of multiple nanometer sheet formation, gate, gate surrounds nanometer sheet, cavity, cavity is respectively arranged between gate and source electrode or drain electrode, cavity is formed by gate, source electrode or drain electrode and nanometer sheet around, that is to say, form cavity between gate and source electrode or drain electrode, that is, form air inner side wall in the side wall of gate, avoid the influence of forming inner side wall by other materials in the side wall of gate, can avoid the problem of parasitic capacitance increase due to inner side wall is other material, greatly reduce the parasitic capacitance of device, improve the working speed of semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate Fin Field-Effect Transistors (FinFETs) are limited below the 3-nanometer (nm) node. Since the Nanosheet-Gate all-round Fin Field-Effect Transistor (Nanosheet-GAAFET) breaks through the 3nm node limitation, it has received widespread attention and research.

[0003] Nanosheet-GAAFET is a novel device featuring a gate-around structure and horizontal nanosheets (NS) as the conductive channel. In terms of gate control, the gate-around structure offers superior gate control compared to FinFET devices, effectively suppressing short-channel effects. Regarding current drive, Nanosheet-GAAFET exhibits bulk-inverting inversion carriers, and the increased effective gate width and vertical nanosheet stacking design significantly enhance the device's current drive performance.

[0004] However, the current Nanosheet-GAAFET has a large parasitic capacitance, which slows down the device and circuit speed and increases power consumption. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a semiconductor device and a method for manufacturing the same, which can reduce the parasitic capacitance of the semiconductor device and improve the performance of the final manufactured semiconductor device.

[0006] This application provides a semiconductor device, the semiconductor device comprising:

[0007] Substrate;

[0008] A source, a drain, and a channel structure are disposed on one side of the substrate, the channel structure being located between the source and the drain, and the channel structure comprising a stack of multiple nanosheets.

[0009] A gate, the gate surrounding the nanosheet;

[0010] A cavity is disposed between the gate and the source or the drain, and the cavity is formed by the gate, the source or the drain and the nanosheet surrounding it.

[0011] Optionally, the cavity is formed by a chemical reaction of a mixture of materials with the molecular formula CHOS disposed between the gate and the source or the drain.

[0012] Optionally, the cavity can be formed by a high-temperature process to allow the mixture to undergo a self-reaction or by a chemical reaction between the mixture and the nanosheets.

[0013] Optionally, a high-k dielectric layer may be disposed between the gate and the nanosheet, and the cavity is formed by the high-k dielectric layer, the source or the drain, and the nanosheet.

[0014] Optionally, the nanosheets are made of silicon-germanium.

[0015] This application provides a method for manufacturing a semiconductor device, the method comprising:

[0016] A substrate is provided, and a stacked structure consisting of alternating layers of a first semiconductor layer and a second semiconductor layer is formed on one side of the substrate;

[0017] The stacked structure is etched to form a source region and a drain region, and a channel region is formed between the source region and the drain region;

[0018] The first semiconductor layer located in the channel region is etched along the first direction, and the first semiconductor layer and the second semiconductor layer form a concave structure along the sidewalls of the first direction, wherein the line connecting the source region and the drain region is the first direction;

[0019] The concave structure is filled with a mixture of substances with the molecular formula CHOS;

[0020] A source and a drain are formed in the source region and the drain region, respectively.

[0021] The first semiconductor layer is replaced with a gate, the gate surrounds the second semiconductor layer, and a stack of multiple second semiconductor layers forms a channel structure;

[0022] The mixed material in the concave structure undergoes a chemical reaction to form a cavity, which is respectively disposed between the gate and the source or the drain. The cavity is formed by the gate, the source or the drain and the second semiconductor layer surrounding it.

[0023] Optionally, the chemical reaction of the mixture in the concave structure to form a cavity includes:

[0024] The cavity is formed by the self-reaction of the mixed material or the chemical reaction between the mixed material and the second semiconductor layer using an annealing process.

[0025] Optionally, before the mixture in the concave structure undergoes a chemical reaction to form a cavity, the method further includes:

[0026] A top dielectric layer is formed on the gate.

[0027] Optionally, replacing the first semiconductor layer with a gate includes:

[0028] The first semiconductor layer is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers.

[0029] The gate is filled in one of the multiple gaps to be filled.

[0030] Optionally, before filling the gate in the plurality of said gaps to be filled, the method further includes:

[0031] A high-k dielectric layer is formed on the surface of the second semiconductor layer.

[0032] This application provides a semiconductor device including a substrate, a source electrode, a drain electrode, and a channel structure disposed on one side of the substrate. The channel structure is located between the source electrode and the drain electrode and includes a stack of multiple nanosheets, a gate electrode surrounding the nanosheets, and cavities disposed between the gate electrode and the source electrode or drain electrode. The cavities are formed by the gate electrode, the source electrode or drain electrode, and the nanosheets surrounding them. In other words, an air inner wall is formed between the gate electrode and the source electrode or drain electrode, which avoids the influence of forming an inner wall made of other materials on the sidewall of the gate electrode. This avoids the problem of increased parasitic capacitance caused by the inner wall being made of other materials, significantly reduces the parasitic capacitance of the device, and improves the operating speed of the semiconductor device. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1A A three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application is shown;

[0035] Figure 1B and Figure 2 Provided for the embodiments of this application Figure 1A The diagram shows cross-sectional structures of a semiconductor device in various directions.

[0036] Figure 3A and Figure 3B Provided for the embodiments of this application Figure 1AThe diagram shows cross-sectional structures of a semiconductor device in various directions.

[0037] Figure 4 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown;

[0038] Figures 5-20 show schematic diagrams of the structure of a semiconductor device manufactured according to the manufacturing method of the semiconductor device provided in the embodiments of this application. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0040] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0041] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0042] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate Fin Field-Effect Transistors (FinFETs) are limited below the 3-nanometer (nm) node. Since the Nanosheet-Gate all-round Fin Field-Effect Transistor (Nanosheet-GAAFET) breaks through the 3nm node limitation, it has received widespread attention and research.

[0043] Nanosheet-GAAFET is a novel device featuring a gate-around structure and horizontal nanosheets (NS) as the conductive channel. In terms of gate control, the gate-around structure offers superior gate control compared to FinFET devices, effectively suppressing short-channel effects. Regarding current drive, Nanosheet-GAAFET exhibits bulk-inverting inversion carriers, and the increased effective gate width and vertical nanosheet stacking design significantly enhance the device's current drive performance.

[0044] However, current Nanosheet-GAAFETs have relatively large parasitic capacitances, resulting in slower device and circuit speeds and increased power consumption. This is because the inner walls of Nanosheet-GAAFETs are typically made of silicon nitride (Si3N4) material (k=9), which is one of the important factors contributing to the increased parasitic capacitance of Nanosheet-GAAFETs. In other words, the inner walls formed by silicon nitride cause slower device and circuit speeds and increased power consumption.

[0045] Based on this, embodiments of this application provide a semiconductor device including a substrate, a source electrode, a drain electrode, and a channel structure disposed on one side of the substrate. The channel structure is located between the source electrode and the drain electrode and includes a stack of multiple nanosheets, a gate electrode surrounding the nanosheets, and cavities. The cavities are respectively disposed between the gate electrode and the source electrode or drain electrode. The cavities are formed by the gate electrode, the source electrode or drain electrode, and the nanosheets surrounding them. That is, a cavity is formed between the gate electrode and the source electrode or drain electrode, i.e., an air inner wall is formed on the sidewall of the gate electrode. This avoids the influence of forming an inner wall made of other materials on the sidewall of the gate electrode, and can avoid the problem of increased parasitic capacitance caused by the inner wall being made of other materials. This significantly reduces the parasitic capacitance of the device and improves the operating speed of the semiconductor device.

[0046] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0047] See Figure 1A The figure is a three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application.

[0048] The semiconductor device provided in this embodiment includes a substrate 110, a source 131, a drain 132, a channel structure, and a gate 160.

[0049] In the embodiments of this application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, or the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0050] In the embodiments of this application, a source 131, a drain 132, and a channel structure are disposed on one side of the substrate 110. The channel structure is disposed between the source 131 and the drain 132, and includes a stack of multiple nanosheets. The channel structure is obtained by removing the first semiconductor layer 121 from the stacked structure. The stacked structure is composed of alternating layers of the first semiconductor layer 121 and the second semiconductor layer 122. That is, the nanosheets in the channel structure are the second semiconductor layer 122 in the stacked structure. (Refer to...) Figure 1B and Figure 2 As shown, where, Figure 1B Provided for the embodiments of this application Figure 1A The diagram shows a cross-sectional view of the semiconductor device in the YY direction. Figure 2 Provided for the embodiments of this application Figure 1A The diagram shows a cross-sectional structure of the semiconductor device in the XX direction. The cross-sectional structure in the YY direction is parallel to the gate line of the gate, and the cross-sectional structure in the XX direction is parallel to the fin line of the fin.

[0051] Specifically, the width of the nanosheets can be 5-50 nm, and the thickness of the nanosheets can be 3-20 nm.

[0052] In the embodiments of this application, there is a gap between the multiple nanosheets in the channel structure, and the gap is filled with a gate 160, that is, the gate 160 surrounds the nanosheets to form a ring gate structure.

[0053] In embodiments of this application, a cavity 200 is provided between the source 131 or drain 132 and the gate 160 along a first direction, wherein the first direction is the direction of the line connecting the source 131 and drain 132, i.e., the first direction is the XX direction. The cavity 200 is formed by the source 131 or drain 132, the gate 160, and the nanosheet surrounding it.

[0054] Specifically, cavities 200 are formed on both sides of the gate 160 along the first direction, respectively, with the source 131 and the drain 132, that is, cavities 200 are present on both sides of the gate 160.

[0055] In the embodiments of this application, an air inner wall is formed on the sidewall of the gate 160 to avoid the influence of forming an inner wall made of other materials on the sidewall of the gate 160. This avoids the problem of increased parasitic capacitance caused by the inner wall being made of other materials, especially avoiding the problem of a large increase in parasitic capacitance caused by an inner wall made of silicon nitride. The presence of the cavity 200 can significantly reduce the parasitic capacitance of the device and improve the operating speed of the semiconductor device.

[0056] In the embodiments of this application, the cavity 200 is formed by a chemical reaction of a mixed substance with the molecular formula CHOS disposed between the gate 160 and the source 131 or the drain 132. That is, when manufacturing a semiconductor device, a mixed substance can be formed in advance between the gate 160 and the source 131 or the drain 132, and then the mixed substance undergoes a chemical reaction to form the cavity 200.

[0057] Specifically, high-temperature processes can be used to perform self-reaction of the mixed materials or to perform chemical reactions between the mixed materials and nanosheets to form cavities 200. The mixed materials exhibit a stable structure at low temperatures.

[0058] As an example, when the nanosheet material is silicon-germanium, the mixture undergoes a self-reaction at high temperature or reacts with silicon-germanium at high temperature to form a cavity 200. Silicon-germanium can also absorb material from the mixture, further aiding in the formation of the cavity 200.

[0059] In embodiments of this application, a high-k dielectric layer 150 may also be disposed between the gate 160 and the nanosheet, that is, the high-k dielectric layer 150 is disposed around the nanosheet, as shown in the reference. Figure 3A and Figure 3B As shown, the cavity 200 is formed by a high-K dielectric layer 150, a source electrode 131 or a drain electrode 132, and nanosheets.

[0060] In embodiments of this application, the semiconductor device further includes a trench isolation 203, a second sidewall 205, an isolation layer 207, a top dielectric layer 170, and a contact electrode 180.

[0061] Shallow trench isolation 203 is disposed between different fins. The surface of the shallow trench isolation 203 away from the substrate 110 can be flush with, or higher than or lower than, the surface of the stacked structure in the fins near the substrate 110. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fins.

[0062] The second sidewall 205 is disposed on the side of the channel structure away from the substrate 110, and the gate 160 is located between the second sidewalls 205. The isolation layer 207 is disposed on the side of the source 131 or drain 132 away from the substrate 110, and the second sidewall 205 and the gate 160 are located between the isolation layers 207.

[0063] The top dielectric layer 170 covers the isolation layer 207, the second sidewall 205 and the gate 160. The top dielectric layer 170 has a contact electrode 180 for electrically leading out the source 131 or the drain 132.

[0064] Therefore, the embodiments of this application provide a semiconductor device including a substrate, a source electrode, a drain electrode, and a channel structure disposed on one side of the substrate. The channel structure is located between the source electrode and the drain electrode and includes a stack of multiple nanosheets, a gate electrode, the gate electrode surrounding the nanosheets, and cavities. The cavities are respectively disposed between the gate electrode and the source electrode or the drain electrode. The cavities are formed by the gate electrode, the source electrode or the drain electrode, and the nanosheets surrounding them. That is, a cavity is formed between the gate electrode and the source electrode or the drain electrode, i.e., an air inner wall is formed on the sidewall of the gate electrode. This avoids the influence of forming an inner wall made of other materials on the sidewall of the gate electrode, and can avoid the problem of increased parasitic capacitance caused by the inner wall being made of other materials. This significantly reduces the parasitic capacitance of the device and improves the operating speed of the semiconductor device.

[0065] Based on the semiconductor device provided in the above embodiments, this application also provides a method for manufacturing a semiconductor device, and its working principle will be described in detail below with reference to the accompanying drawings.

[0066] See Figure 4 The figure is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of this application.

[0067] The method for manufacturing a semiconductor device provided in this application includes the following steps:

[0068] S101, a substrate 110 is provided, and a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 is formed on one side of the substrate 110, with reference to... Figure 5A and Figure 5B As shown.

[0069] In the embodiments of this application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, or the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0070] As an example, the desired well depth can be achieved by implanting impurities into a bulk silicon substrate and then annealing it to form a highly doped well region. The doping type of the substrate 110 varies depending on the device type. For P-type semiconductor devices, the highly doped well region is an N-well, and the implanted impurities are n-type impurity ions, such as phosphorus (P) ions. For N-type semiconductor devices, the highly doped well region is a p-well, and the implanted impurities are p-type impurity ions, such as boron (B) ions.

[0071] In embodiments of this application, a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 can be formed on one side of the substrate 110, as shown in the reference. Figure 5A and Figure 5B As shown, where, Figure 5A Provided for the embodiments of this application Figure 1AThe diagram shows a cross-sectional view of the semiconductor device in the YY direction. Figure 5B Provided for the embodiments of this application Figure 1A The diagram shows a cross-sectional structure of the semiconductor device in the XX direction. The cross-sectional structure in the YY direction is parallel to the gate line of the gate, and the cross-sectional structure in the XX direction is parallel to the fin line of the fin.

[0072] Specifically, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be the same. For example, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon or germanium. Alternatively, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be different. For example, for a P-type semiconductor device, the material of the first semiconductor layer 121 can be silicon, and the material of the second semiconductor layer 122 can be silicon-germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon.

[0073] In practical applications, silicon oxide may be formed on the substrate 110. The stacked structure can be formed after the silicon oxide on the substrate 110 is removed and the substrate 110 is cleaned.

[0074] S102, etching is performed on the stacked structure to form the source region 101 and the drain region 102, reference. Figure 11A and Figure 11B As shown.

[0075] In embodiments of this application, the stacked structure can be etched to form a source region 101 and a drain region 102, wherein a channel region 103 is formed between the source region 101 and the drain region 102. (Refer to...) Figure 11A and Figure 11B As shown.

[0076] The specific process flow for forming the source region 101 and the drain region 102 is as follows:

[0077] S1021, Sidewall Transfer Process, Reference Figure 6A and Figure 6B As shown.

[0078] In the embodiments of this application, a self-aligned sidewall transfer process is used to form the first sidewall 201. The material of the first sidewall 201 is silicon nitride. The specific formation process is as follows: a sacrificial layer 202 is covered on the stacked structure. The material of the sacrificial layer 202 can be polycrystalline silicon or amorphous silicon. Part of the sacrificial layer 202 is etched away using photolithography to form a pattern. Silicon nitride material is deposited. Then, anisotropic etching is used to etch away the remaining sacrificial layer 202, so that only the first sidewall 201 on the stacked structure remains. The first sidewall 201 plays the role of a hard mask in the subsequent photolithography for forming fins.

[0079] S1022, forming fins, see reference. Figure 7A and Figure 7B As shown.

[0080] In the embodiments of this application, the stacked structure can be etched using an etching process to form multiple periodically distributed fins, as shown in the reference. Figure 7A and Figure 7B As shown, etching is performed using the first sidewall 201 as a mask to form a fin with a stacked structure. The upper part of the fin is the channel region 103 formed by the stacked structure, and the lower part of the fin is the substrate 110, forming a structure as shown. Figure 7A The fin shown is not only a stacked structure but also includes a single-crystal silicon structure extending into the substrate 110. The etching process can be dry etching or wet etching, and in one embodiment, reactive ion etching can be used. The fin will be used to form nanosheets for semiconductor devices. Although Figure 7A A fin is shown, and it should be understood that any suitable number and shape of fins can be used in practical applications.

[0081] S1022, forming shallow trench isolation 203 (STI), see reference. Figure 8A and Figure 8B As shown.

[0082] In embodiments of this application, shallow trench isolation 203 can be formed between different fins. Specifically, a dielectric insulating material can be deposited first, followed by a planarization process, such as CMP, and then a selective etch-back process of the dielectric insulating material to expose the three-dimensional fins, thereby forming shallow trench isolation 203 between adjacent fins. The surface of the shallow trench isolation 203 away from the substrate 110 can be flush with, or higher than, the surface of the stacked structure in the fins near the substrate 110. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fins.

[0083] In practical applications, when forming shallow trench isolation 203, the first sidewall 201 can also be removed.

[0084] S1023, forming a dummy gate 204, reference. Figure 9A and Figure 9B As shown.

[0085] In the embodiments of this application, a dummy gate stack is formed on the exposed fin in a direction perpendicular to the fin lines, i.e., in the YY direction. The dummy gate stack is a multilayer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204, and a hard mask layer (not shown). The dummy gate stack can be formed using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The dummy gate stack spans the stack structure above the fin, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 204 can be polycrystalline silicon or amorphous silicon. The material of the hard mask layer can be oxides, carbides, organic materials, etc.

[0086] S1024, forming the second sidewall 205, see reference. Figure 10A and Figure 10B As shown.

[0087] In the embodiments of this application, second sidewalls 205 can be provided on both sides of the dummy gate stack along the fin direction, i.e., the XX direction, and the thickness of the second sidewalls 205 on both sides is the same. The material of the second sidewalls 205 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0088] In the embodiments of this application, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source and drain etching on the stacked structure through an etching process, specifically source and drain etching on the fins. The source region 101 and the drain region 102 no longer have a stacked structure after etching. (Refer to...) Figure 11B As shown.

[0089] S103, etch the first semiconductor layer 121 located in the channel region 103 along the first direction, reference Figure 12A and Figure 12B As shown.

[0090] In the embodiments of this application, along a first direction, i.e., the XX direction, selective etching is performed on the first semiconductor layer 121 in the stacked structure located in the channel region 103, i.e., only the first semiconductor layer 121 is etched, without damaging the second semiconductor layer 122. Along the XX direction, the portion of the first semiconductor layer 121 that is missing from the second semiconductor layer 122 forms a concave structure 401, that is, pull-back etching is performed, etching away a portion of the first semiconductor layer 121 from the source region 101 and the drain region 102 toward the channel region 103, as referenced. Figure 12A and Figure 12B As shown.

[0091] S104, a mixture of substances with the molecular formula CHOS 206 is filled into the concave structure 401, reference. Figure 13A and Figure 13B As shown.

[0092] In the embodiments of this application, after the first semiconductor layer 121 is etched, a mixed material 206 is deposited on the periphery of the stacked structure located in the channel region 103, i.e., the fin. That is, the mixed material 206 is used to fill the concave structure 401. The mixed material 206 is flush with the second semiconductor layer 122 in a direction perpendicular to the plane of the substrate 110. In other words, the concave structure 401 caused by etching in S103 is filled by the mixed material 206. Specifically, the mixed material 206 can be formed by selective atomic layer growth.

[0093] S105, source 131 and drain 132 are formed in source region 101 and drain region 102, respectively, for reference. Figure 14A and Figure 14B As shown.

[0094] In embodiments of this application, after etching the stacked structure to form source region 101 and drain region 102, source 131 and drain 132 can be formed in source region 101 and drain region 102, respectively. (Refer to...) Figure 14A and Figure 14B As shown.

[0095] Specifically, the source and drain materials may differ for different types of semiconductor devices. For P-type semiconductor devices, the source and drain materials are boron-doped germanium silicon, i.e., SiGe:B. For N-type semiconductor devices, the source and drain materials are phosphorus-doped silicon, i.e., Si:P.

[0096] In embodiments of this application, after forming the source 131 and drain 132, the dummy gate 204 can be removed, see reference. Figure 15A and Figure 15B As shown.

[0097] In embodiments of this application, an isolation layer 207 can be deposited on the surfaces of the dummy gate 204, source 131, and drain 132 to prevent short circuits between the dummy gate 204 and the source 131 or drain 132 in subsequent steps. The isolation layer 207 is then subjected to a chemical mechanical polishing process to planarize it. Then, as... Figure 15A and Figure 15B As shown, the dummy gate 204 formed by the aforementioned polycrystalline silicon or amorphous silicon is etched or etched away by selective etching or etching processes, that is, the dummy gate 204 is removed.

[0098] S106, replace the first semiconductor layer 121 with the gate 160, as shown in Figures 16-18.

[0099] In embodiments of this application, the first semiconductor layer 121 can be replaced with the gate 160, as shown in Figures 16-18.

[0100] The specific process flow is as follows:

[0101] S1061, Remove the first semiconductor layer 121 of the channel region 103, refer to Figure 16A and Figure 16B As shown.

[0102] In embodiments of this application, the first semiconductor layer 121 of the channel region 103 can be removed, i.e., a nanosheet channel release process can be performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layers 122, see reference. Figure 16A and Figure 16B As shown.

[0103] Specifically, the first semiconductor layer 121 in the stacked structure located in the channel region 103 can be selectively etched to release the nanosheet channel. That is, the stacked structure exposed by the fins is processed to remove the first semiconductor layer 121 of each layer, which is the sacrificial layer, to release the nanosheets formed by the second semiconductor layer 122.

[0104] In the embodiments of this application, there are several possible ways to achieve nanosheet channel release for different types of devices:

[0105] In a first possible implementation, for both P-type and N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-laminated nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.

[0106] In a second possible implementation, for a P-type semiconductor device, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon. Silicon is selectively removed, leaving the second semiconductor layer 122, i.e., silicon-germanium, to form a silicon-germanium stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon at a faster rate than silicon-germanium can be used.

[0107] In a third possible implementation, for N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.

[0108] S1062, a high-k dielectric layer 150 is formed on the surface of the second semiconductor layer 122, reference. Figure 17A and Figure 17B As shown.

[0109] In embodiments of this application, after removing the first semiconductor layer 121, a high-k dielectric layer 150 can be formed on the surface of the second semiconductor layer 122. The high-k dielectric layer 150 surrounds the surface of the second semiconductor layer 122. (Refer to...) Figure 17A and Figure 17B As shown. Specifically, the material of the high-k dielectric layer 150 can be HfO2 or HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.

[0110] S1063, fill the gate 160 in multiple gaps 402 to be filled, reference Figure 18A and Figure 18B As shown.

[0111] In the embodiments of this application, after the nanosheet channel is released, there are multiple gaps 402 to be filled between the multiple second semiconductor layers 122. A gate 160 can be filled into these gaps 402, and the gate 160 surrounds the second semiconductor layers 122, forming a gate-ring structure. The stack of multiple second semiconductor layers 122 forms a channel structure, i.e., a nanosheet channel for a semiconductor device. (Refer to...) Figure 18A and Figure 18B As shown.

[0112] In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 also covers the space after the isolation layer 207 and the dummy gate 204 is removed. The gate 160 covered by the isolation layer 207 can be chemically mechanically polished to perform planarization.

[0113] S107, the mixed substance 206 in the concave structure 401 undergoes a chemical reaction to form a cavity 200. (Reference) Figure 20A and Figure 20B As shown.

[0114] In the embodiments of this application, the mixed substance 206 in the concave structure 401 can be processed so that the mixed substance 206 undergoes a chemical reaction to form a cavity 200.

[0115] Specifically, the cavity can be formed by the self-reaction of the mixed material 206 or by the chemical reaction of the mixed material 206 and the second semiconductor layer 122 using an annealing process. In other words, the cavity 200 is formed by the chemical reaction of a mixed material with the molecular formula CHOS disposed between the gate 160 and the source 131 or drain 132.

[0116] As an example, when the material of the second semiconductor layer 122 is silicon-germanium, the mixed material 206 undergoes a self-reaction at high temperature or reacts with silicon-germanium at high temperature to form a cavity 200. Silicon-germanium can also absorb the material of the mixed material, further aiding in the formation of the cavity 200.

[0117] In embodiments of this application, after forming the gate 160, dielectric deposition can be performed on the top of the semiconductor device away from the substrate 110 to form a top dielectric layer 170, as shown in the reference. Figure 19A and Figure 19B As shown, after forming the top dielectric layer 170, an annealing process can be performed to form the cavity 200. This allows the top dielectric layer 170 to protect the gate 160, preventing the gate 160 from being exposed to air and affected during the annealing process, thus improving the performance of the semiconductor device.

[0118] In the embodiments of this application, contact hole etching is performed in the top dielectric layer 170, etching down to the surface of the source 131 or drain 132, and metal material is deposited in the contact holes to form the contact electrodes 180 of the source 131 or drain 132. (Refer to...) Figure 3A and Figure 3B As shown, subsequent processes include multi-layer back-end interconnection and passivation protection.

[0119] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, structural embodiments are generally similar to method embodiments and are therefore described simply; relevant details can be found in the descriptions of the method embodiments.

[0120] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Substrate; A source, a drain, and a channel structure are disposed on one side of the substrate, the channel structure being located between the source and the drain, and the channel structure comprising a stack of multiple nanosheets. A gate, the gate surrounding the nanosheet; A cavity is disposed between the gate and the source or the drain, and the cavity is formed by the gate, the source or the drain and the nanosheet surrounding it; The cavity is formed by a chemical reaction of a mixture of substances with the molecular formula CHOS disposed between the gate and the source or the drain.

2. The semiconductor device according to claim 1, characterized in that, The cavity is formed by the self-reaction of the mixed material or the chemical reaction of the mixed material and nanosheets using a high-temperature process.

3. The semiconductor device according to claim 2, characterized in that, A high-k dielectric layer is further disposed between the gate and the nanosheet, and the cavity is formed by the high-k dielectric layer, the source or the drain, and the nanosheet.

4. The semiconductor device according to claim 2, characterized in that, The nanosheets are made of silicon-germanium.

5. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided, and a stacked structure consisting of alternating layers of a first semiconductor layer and a second semiconductor layer is formed on one side of the substrate; The stacked structure is etched to form a source region and a drain region, and a channel region is formed between the source region and the drain region; The first semiconductor layer located in the channel region is etched along the first direction, and the first semiconductor layer and the second semiconductor layer form a concave structure along the sidewalls of the first direction, wherein the line connecting the source region and the drain region is the first direction; The concave structure is filled with a mixture of substances with the molecular formula CHOS; A source and a drain are formed in the source region and the drain region, respectively. The first semiconductor layer is replaced with a gate, the gate surrounds the second semiconductor layer, and a stack of multiple second semiconductor layers forms a channel structure; The mixed material in the concave structure undergoes a chemical reaction to form a cavity, which is respectively disposed between the gate and the source or the drain. The cavity is formed by the gate, the source or the drain and the second semiconductor layer surrounding it.

6. The manufacturing method according to claim 5, characterized in that, The chemical reaction of the mixed material in the concave structure to form a cavity includes: The cavity is formed by the self-reaction of the mixed material or the chemical reaction between the mixed material and the second semiconductor layer using an annealing process.

7. The manufacturing method according to claim 6, characterized in that, Before the mixture in the concave structure undergoes a chemical reaction to form a cavity, the method further includes: A top dielectric layer is formed on the gate.

8. The manufacturing method according to claim 5, characterized in that, The step of replacing the first semiconductor layer with a gate includes: The first semiconductor layer is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers. The gate is filled in one of the multiple gaps to be filled.

9. The manufacturing method according to claim 8, characterized in that, Before filling the gate in the plurality of said gaps to be filled, the method further includes: A high-k dielectric layer is formed on the surface of the second semiconductor layer.

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