Silicon wafer device with gallium oxide nanostructure and preparation method thereof, and semiconductor device

Abstract

The present invention relates to a silicon wafer device having a gallium oxide nanostructure, a preparation method thereof, and a semiconductor device. The preparation method comprises: providing a silicon wafer, the silicon wafer comprising a silicon top layer, a buried oxide layer, and a silicon base layer stacked in sequence; etching the silicon wafer in a direction perpendicular to the buried oxide layer from the silicon top layer to obtain a structured composite substrate having grooves, the grooves comprising a first groove extending through the silicon top layer and a second groove extending from the first groove into the buried oxide layer, the depth of the second groove being less than the thickness of the buried oxide layer; subjecting the structured composite substrate to chemical vapor deposition in an environment containing a carbon nanomaterial, a gallium source, and an oxygen source, causing the gallium source to deposit and grow within the first groove, thereby obtaining a silicon wafer device having a gallium oxide nanostructure. The preparation method enables the gallium oxide nanostructure in the silicon wafer device to form an efficient electron transmission channel, while reducing the generation of a crystalline layer and preventing electron transmission in the crystalline layer.

Description

Technical Field

[0001] The present invention relates to the technical field of nano device manufacturing, and in particular to a silicon wafer device with a gallium oxide nanostructure, a preparation method thereof, and a semiconductor device. Background Art

[0002] Gallium oxide (Ga2O3), as a new wide-bandgap semiconductor material, has attracted widespread attention. Ga2O3 materials have a wider bandgap than third-generation semiconductor materials such as gallium nitride (GaN) and silicon carbide (SiC), reaching a bandgap of 4.2eV-4.9eV. They also exhibit higher breakdown field strength and radiation resistance, as well as excellent thermal and chemical stability. They also have very high transmittance in the visible and ultraviolet regions. These excellent properties hold great promise for applications in solar-blind UV detectors, sensors, light-emitting devices, and high-power devices such as MOSFETs.

[0003] Nanomaterials exhibit surface, small, and quantum size effects, resulting in high photoresponsivity and low current, resulting in excellent performance in light, sound, heat, electricity, and magnetism. These materials hold broad application prospects in a wide range of fields, including catalysis, optoelectronics, magnetic media, and energy. Therefore, Ga2O3 nanomaterials have a wide range of potential applications in micro- and nano-photoelectric devices, photodetectors, electronics, environmental research, and medicine.

[0004] The preparation of Ga2O3 nanostructures mainly includes thermal evaporation, hydrothermal method, thermal oxidation method and chemical vapor deposition (CVD), among which CVD method mainly includes metal organic compound chemical vapor deposition (MOCVD) and low pressure chemical vapor deposition (LPCVD). The CVD method is simple to operate and cost-effective, and is the most widely used method for growing Ga2O3 nanostructures. However, there is a crystalline layer of a certain thickness between the Ga2O3 nanostructure prepared by the CVD method and the substrate. This crystalline layer will affect the electrical performance of the device prepared by the nanostructure, thereby reducing the advantages brought by the Ga2]3 nanostructure to the device performance. Summary of the Invention

[0005] Based on this, it is necessary to provide a silicon wafer device with a gallium oxide nanostructure, a preparation method thereof, and a semiconductor device to address the above problems; the preparation method enables the gallium oxide nanostructure in the silicon wafer device to form an efficient electron transmission channel, while reducing the generation of a crystal layer, thereby effectively avoiding the transmission of electrons in the crystal layer, which is conducive to obtaining a semiconductor device with excellent performance and high quality.

[0006] A method for preparing a silicon wafer device having a gallium oxide nanostructure comprises the following steps:

[0007] Providing a silicon wafer, the silicon wafer comprising a silicon top layer, a buried oxide layer, and a silicon base layer stacked in sequence;

[0008] Etching the silicon wafer in a direction perpendicular to the buried oxide layer from the silicon top layer to obtain a structured composite substrate having grooves, wherein the grooves include a first groove penetrating the silicon top layer and a second groove extending from the first groove to the interior of the buried oxide layer, and the depth of the second groove is less than the thickness of the buried oxide layer;

[0009] The structured composite substrate is subjected to chemical vapor deposition in the presence of carbon nanomaterials, a gallium source, and an oxygen source, so that the gallium source is deposited and grown in the first groove to obtain a silicon wafer device having a gallium oxide nanostructure.

[0010] In one embodiment, the thickness of the silicon top layer is 10 nm to 50 nm;

[0011] and / or, the buried oxide layer has a thickness of 30 nm to 200 nm;

[0012] And / or, the thickness of the silicon base layer is 500 μm-700 μm.

[0013] In one embodiment, the material of the buried oxide layer is selected from at least one of silicon dioxide, aluminum oxide, and quartz.

[0014] In one embodiment, the size of the carbon nanomaterial is 30nm-100nm;

[0015] And / or, the carbon nanomaterial is at least one selected from nanodiamonds and carbon nanotubes.

[0016] In one embodiment, the gallium source is selected from gallium oxide powder.

[0017] In one embodiment, the flow rate of the oxygen source is 0.5 sccm-3 sccm;

[0018] And / or, the oxygen source is selected from oxygen gas.

[0019] In one embodiment, the chemical vapor deposition temperature is 900° C.-1100° C., and the time is 3 min-10 min.

[0020] A silicon wafer device having a gallium oxide nanostructure prepared by the preparation method described above comprises the structured composite substrate and the gallium oxide nanostructure grown in the first groove, wherein the gallium oxide nanostructure is composed of overlapping gallium oxide nanomaterials.

[0021] In one embodiment, when the gallium oxide nanomaterial is selected from gallium oxide nanowires, the aspect ratio of the gallium oxide nanowires is greater than 10 4 .

[0022] A semiconductor device comprises the silicon wafer device with the gallium oxide nanostructure as described above, wherein the main current transmission direction of the semiconductor device is horizontal.

[0023] The preparation method described in the present invention constructs an insulating patterned structured composite substrate, uses the rough inner wall of the first groove to provide crystallization nuclei, and uses chemical vapor deposition to nucleate and grow gallium oxide nanomaterials in the first groove without a catalyst. Carbon nanomaterials are used as a reducing agent to effectively regulate the structural distribution of the gallium oxide nanomaterials. Then, on the insulating patterned structured composite substrate, the gallium oxide nanomaterials are overlapped to form nanojunctions, forming a connected gallium oxide nanostructure, while retaining the blocking structure formed by the second groove. Therefore, electrons are efficiently transmitted only through the gallium oxide nanostructure, significantly improving the electron transmission efficiency.

[0024] Therefore, based on chemical vapor deposition, this preparation method can construct an efficient electron transmission channel in a silicon wafer device through only a simple and easy-to-operate structural design. At the same time, it effectively reduces the generation of a crystallization layer and eliminates the influence of the crystallization layer on the electrical properties of the nanostructure. As a result, the semiconductor device prepared based on the silicon wafer device with the gallium oxide nanostructure has excellent electrical performance and can be widely used in semiconductor device fields such as detectors and sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a flow chart of a method for preparing a silicon wafer device having a gallium oxide nanostructure according to one embodiment of the present invention;

[0026] Figure 2 This is a scanning electron microscope image of the gallium oxide nanostructure prepared in Example 1 of the present invention;

[0027] Figure 3 This is a scanning electron microscope image of the nanojunction in the gallium oxide nanostructure prepared in Example 1 of the present invention;

[0028] Figure 4 This is a scanning electron microscope image of the gallium oxide nanostructure prepared in Comparative Example 4 of the present invention.

[0029] Among them, 10, silicon wafer; 101, silicon top layer; 102, buried oxide layer; 103, silicon base layer; 104, groove; 1041, first groove; 1042, second groove; 20, gallium oxide nanostructure; 201, nanojunction; 202, gallium oxide nanomaterial. DETAILED DESCRIPTION

[0030] To facilitate understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments or embodiments and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, including any two related listed items, any more related listed items, or the combination of all related listed items.

[0032] Combine Figure 1 FIG. 1 is a method for preparing a silicon wafer device having a gallium oxide nanostructure according to an embodiment of the present invention, comprising the following steps:

[0033] S1, providing a silicon wafer 10, wherein the silicon wafer 10 includes a silicon top layer 101, a buried oxide layer 102, and a silicon base layer 103 stacked in sequence;

[0034] S2, etching the silicon wafer 10 in a direction perpendicular to the buried oxide layer 102 from the silicon top layer 101 to obtain a structured composite substrate having a groove 104, wherein the groove 104 includes a first groove 1041 penetrating the silicon top layer and a second groove 1042 extending from the first groove 1041 to the interior of the buried oxide layer 102, and the depth of the second groove 1042 is less than the thickness of the buried oxide layer 102;

[0035] S3, performing chemical vapor deposition on the structured composite substrate in an environment of carbon nanomaterial, gallium source, and oxygen source, so that the gallium source is deposited and grown in the first groove 1041 to obtain a silicon wafer device having a gallium oxide nanostructure 20.

[0036] Different from the traditional single-layer silicon substrate, in step S1, a silicon wafer 10 with a stacked structure is designed to be used as the substrate, wherein the silicon top layer 101 and the silicon base layer 103 serve as the conductive substrate layer, and the buried oxide layer 102 serves as the insulating substrate layer. The buried oxide layer 102 is used to separate the silicon top layer 101 and the silicon base layer 103 to form a vertical non-path silicon wafer 10.

[0037] Optionally, the buried oxide layer 102 is made of at least one material selected from silicon dioxide, aluminum oxide, and quartz.

[0038] In order to facilitate the subsequent construction of an insulating patterned structure and form a nanomaterial electron transmission channel, the thickness of the buried oxide layer 102 is 30 nm-200 nm, preferably 30 nm-100 nm.

[0039] Considering that the silicon base layer 103 in the silicon wafer 10 has a structural support function, if the thickness of the silicon base layer 103 is not enough, the silicon wafer 10 will easily generate cracks due to stress and strain during the process of growing and preparing the gallium oxide nanostructure 20, and may even cause the silicon wafer 10 to break. Preferably, the thickness of the silicon base layer 103 is 500μm-700μm.

[0040] Preferably, in the silicon wafer 10 , the thickness of the silicon top layer 101 is 10 nm-50 nm, the thickness of the buried oxide layer 102 is 30 nm-200 nm, and the thickness of the silicon base layer 103 is 500 μm-700 μm.

[0041] More preferably, in the silicon wafer 10 , the thickness of the silicon top layer 101 is 10 nm-50 nm, the thickness of the buried oxide layer 102 is 30 nm-100 nm, and the thickness of the silicon base layer 103 is 500 μm-700 μm.

[0042] In order to remove the pollutants remaining on the surface of the silicon wafer 10 , the silicon wafer 10 is cleaned, specifically including: ultrasonically cleaning the silicon wafer 10 in deionized water, ethanol, and deionized water in sequence, and drying it with nitrogen.

[0043] In order to be applicable to different patterned semiconductor device structures, in step S2, a mask etching preparation method is preferably adopted. The specific preparation steps include: masking the surface of the silicon top layer 101 of the cleaned silicon wafer 10, and etching under the mask condition to form a groove 104, and then using organic matter to remove the mask to obtain a structured composite substrate.

[0044] Because the groove 104 penetrates the silicon top layer 101, the silicon top layer 101 is patterned into multiple independent silicon dots, and because the buried oxide layer 102 connecting the various silicon dots is an insulating substrate layer, the various silicon dots are insulated from each other. This can not only effectively reduce the generation of crystallization layers, but also help eliminate the influence of inefficient electron transmission channels.

[0045] It should be noted that the present invention does not specifically limit the etching pattern. Those skilled in the art can make their own choices based on the actual preparation requirements of the semiconductor device structure, and the etching method includes but is not limited to the mask method. Other methods that can achieve structured etching of the silicon wafer 10 are also applicable to the present invention, and the present invention does not list them one by one.

[0046] Considering the influence of impurities introduced during the etching process on the electrical properties of the product, it is preferred to perform the structured etching of the silicon wafer 10 in the yellow light area of a clean room.

[0047] In step S3, compared with conventional chemical vapor deposition (CVD) methods for preparing nanostructures, the present invention does not require a catalyst. Instead, it utilizes a simple, easy-to-operate structural design, utilizes an insulating, patterned structured composite substrate, and uses the rough inner wall of the first groove 1041 to provide crystallization nuclei. Chemical vapor deposition is performed without a catalyst to nucleate and grow the gallium oxide nanomaterial 202 within the first groove 1041. Furthermore, the carbon nanomaterial is used as a reducing agent to effectively regulate the structural distribution of the gallium oxide nanomaterial 202. Furthermore, on the insulating, patterned structured composite substrate, the gallium oxide nanomaterial 202 overlaps within the first groove 1041 to form a nanojunction 201, and / or the gallium oxide nanomaterial 202 extending from the first groove 1041 overlaps to form a nanojunction 201, thereby forming a connected gallium oxide nanostructure 20. Meanwhile, the blocking structure formed by the second groove is retained, thereby enabling electrons to be efficiently transmitted only through the gallium oxide nanostructure 20, significantly improving electron transmission efficiency.

[0048] It should be noted that, depending on the specific adjustment of the preparation conditions such as the amount of carbon nanomaterial used and the amount of gallium source used, the gallium oxide nanomaterial 202 can be one or a mixture of three-dimensional structures such as nanowires, nanorods or nanosheets. The present invention does not specifically limit this. As long as the gallium oxide nanostructure 20 prepared according to the preparation method provided by the present invention falls within the scope of protection of the present invention.

[0049] In order to more accurately control the growth of the gallium oxide nanomaterial 202 and obtain a more efficient electron transmission channel, the size of the carbon nanomaterial is preferably 30 nm-100 nm.

[0050] Optionally, the carbon nanomaterial is selected from at least one of nanodiamond and carbon nanotube, preferably nanodiamond.

[0051] Taking into account the safety and convenience of the preparation process, as well as the diversification of the prepared nanostructures, the gallium source in the present invention is preferably gallium oxide powder.

[0052] Optionally, the oxygen source is selected from oxygen gas, and the flow rate of the oxygen source is 0.5 sccm-3 sccm, preferably 1.5 sccm-2 sccm.

[0053] Based on the preparation method of the present invention, no catalyst is required. The preparation principle of the gallium oxide nanomaterial 202 is to use the etched first groove 1041 to provide crystal nuclei for growth. Compared with the preparation conditions of traditional chemical vapor deposition for preparing nanostructures, the growth temperature required for chemical vapor deposition is lower, preferably 900°C-1100°C, more preferably 950°C-1000°C, and the time is 3min-10min, preferably 5min-10min.

[0054] In one embodiment, chemical vapor deposition for preparing gallium oxide nanostructures 20 specifically includes the following steps: placing carbon nanomaterials, gallium sources, and structured composite substrates into a deposition apparatus, first evacuating the deposition apparatus to a vacuum state and preheating the apparatus; then, using high-purity argon as a carrier gas to purge the apparatus to remove impurity gases such as air, and continuously introducing argon to fill the deposition apparatus with protective gas, while adjusting the pressure to maintain it at a certain constant value; continuously raising the temperature from the preheating temperature, and introducing oxygen when the critical growth temperature is reached, maintaining a constant temperature at a growth temperature of 900°C-1100°C for 3 minutes-10 minutes, and cooling the apparatus after the growth is completed to obtain a silicon wafer device having gallium oxide nanostructures 20.

[0055] Therefore, the preparation method provided by the present invention has a simple process and low cost, and can construct an efficient electron transmission channel in the silicon wafer device, while effectively reducing the generation of the crystallization layer and eliminating the influence of the crystallization layer on the electrical properties of the nanostructure, so that the silicon wafer device with the gallium oxide nanostructure 20 has excellent electrical performance.

[0056] It should be noted that when the thickness of the silicon top layer 101 is zero, that is, the silicon wafer 10 includes only the buried oxide layer 102 and the silicon base layer 103 stacked in sequence, the formation of the crystalline layer during the preparation of the gallium oxide nanostructure 20 only affects the growth time of the nanostructure and does not affect the formation of efficient electron transmission channels. By delaying the preparation time to a certain extent, the prepared gallium oxide nanostructure 20 can also provide an efficient electron transmission channel and avoid electron transmission in the crystalline layer.

[0057] The present invention also provides a silicon wafer device having a gallium oxide nanostructure 20 prepared by the preparation method described above, wherein the silicon wafer device includes the structured composite substrate and the gallium oxide nanostructure 20 grown in the first groove 1041, wherein the gallium oxide nanostructure 20 is composed of overlapping gallium oxide nanomaterials 202.

[0058] The gallium oxide nanomaterials 202 overlap with each other to form a nanojunction 201 , and the gallium oxide nanostructure 20 has at least one nanojunction 201 .

[0059] It should be noted that the gallium oxide nanostructures 20 formed in all first grooves 1041 can be located in the same horizontal direction or in different horizontal directions. When all gallium oxide nanostructures 20 formed in the first grooves 1041 are located in the same horizontal direction, the electron transmission efficiency is better.

[0060] In one embodiment, when the gallium oxide nanomaterial 202 is preferably a gallium oxide nanowire, the diameter of the gallium oxide nanowire can reach tens of nanometers and the length can reach micrometer level, that is, the aspect ratio of the gallium oxide nanowire is greater than 10. 4 This aspect ratio advantage can meet the structural requirements of the gallium oxide nanomaterial 202 in semiconductor devices.

[0061] The present invention further provides a semiconductor device, comprising the silicon wafer device having the gallium oxide nanostructure 20 as described above, wherein the main current transmission direction of the semiconductor device is lateral.

[0062] The semiconductor device has excellent electrical properties, can meet the performance requirements of various electronic devices such as micro-nano optoelectronic devices and photoelectric detection devices, and has a wider range of applications and stronger adaptability.

[0063] Hereinafter, the silicon wafer device with gallium oxide nanostructure, the preparation method thereof, and the semiconductor device will be further described through the following specific embodiments.

[0064] Example 1

[0065] A silicon wafer was selected, comprising a stacked silicon top layer, a silicon dioxide layer, and a silicon base layer. The top layer had a thickness of 30 nm, the silicon dioxide layer had a thickness of 50 nm, and the silicon base layer had a thickness of 500 μm. The silicon wafer was ultrasonically cleaned in deionized water, ethanol, and deionized water to remove any residual contaminants, and then dried with nitrogen.

[0066] In the yellow light area of the clean room, a mask is attached to the silicon top surface of the cleaned silicon wafer and photoetched to a vertical depth of 50nm. The mask is then removed using organic matter to obtain a structured composite substrate.

[0067] Nanodiamonds (30nm), gallium oxide powder (99.8%), and a structured composite substrate were placed in a tube furnace. The furnace was first evacuated to a vacuum and preheated. High-purity argon was then used as a carrier gas to purge the chamber to remove impurities such as air. Argon was continuously introduced at a flow rate of 100sccm to fill the deposition apparatus with protective gas. The pressure was also adjusted to maintain a constant value. The temperature was continuously raised from the preheating temperature, and oxygen was introduced at a flow rate of 1.5sccm when the critical value of 960°C was reached. The temperature was maintained at 960°C for 10 minutes. After the growth was completed, the temperature was lowered to room temperature to obtain a silicon wafer device with a gallium oxide nanostructure.

[0068] Photoelectric tests conducted after the electrodes were prepared showed that the current of the silicon wafer device was four times that of the unstructured silicon wafer device in Comparative Example 1.

[0069] Combine Figure 2 It can be seen that the gallium oxide nanomaterial is a nanowire with a diameter of about 50nm and a length of up to hundreds of microns. Figure 3 It can be seen that the nanowires are stacked and interlaced to form multiple nanojunctions.

[0070] Example 2

[0071] A silicon wafer was selected, comprising a stacked silicon top layer, a silicon dioxide layer, and a silicon base layer. The top layer had a thickness of 30 nm, the silicon dioxide layer had a thickness of 50 nm, and the silicon base layer had a thickness of 450 μm. The silicon wafer was ultrasonically cleaned in deionized water, ethanol, and deionized water to remove any residual contaminants, and then dried with nitrogen.

[0072] In the yellow light area of the clean room, a mask is attached to the silicon top surface of the cleaned silicon wafer and photoetched to a vertical depth of 50nm. The mask is then removed using organic matter to obtain a structured composite substrate.

[0073] Nanodiamonds (45nm), gallium oxide powder (99.8%), and a structured composite substrate were placed in a tube furnace. The furnace was first evacuated to a vacuum and preheated. High-purity argon was then used as a carrier gas to purge the chamber to remove impurities such as air. Argon was continuously introduced at a flow rate of 100 sccm to fill the deposition apparatus with protective gas. The pressure was also adjusted to maintain a constant value. The temperature was continuously raised from the preheating temperature, and oxygen was introduced at a flow rate of 1.2 sccm when the critical value of 1000°C was reached. The temperature was maintained at 1000°C for 8 minutes. After the growth was completed, the temperature was lowered to room temperature to obtain a silicon wafer device with a gallium oxide nanostructure.

[0074] Example 3

[0075] A silicon wafer was selected. The wafer comprised a stacked silicon top layer, an aluminum oxide layer, and a silicon base layer. The thickness of the silicon top layer was 30 nm, the thickness of the aluminum oxide layer was 250 nm, and the thickness of the silicon base layer was 500 μm. The silicon wafer was ultrasonically cleaned in deionized water, ethanol, and deionized water to remove any residual contaminants, and then dried with nitrogen.

[0076] In the yellow light area of the clean room, a mask is attached to the silicon top surface of the cleaned silicon wafer and photoetched to a vertical depth of 100nm. The mask is then removed using organic matter to obtain a structured composite substrate.

[0077] Nanodiamonds (60nm), gallium oxide powder (99.8%), and a structured composite substrate were placed in a tube furnace. The furnace was first evacuated to a vacuum and preheated. High-purity argon was then used as a carrier gas to purge the chamber to remove impurities such as air. Argon was continuously introduced at a flow rate of 100 sccm to fill the deposition apparatus with protective gas. The pressure was also adjusted to maintain a constant value. The temperature was continuously raised from the preheating temperature, and oxygen was introduced at a flow rate of 1.5 sccm when the critical value of 960°C was reached. The temperature was maintained at 960°C for 10 minutes. After the growth was completed, the temperature was lowered to room temperature to obtain a silicon wafer device with a gallium oxide nanostructure.

[0078] Example 4

[0079] A silicon wafer was selected, comprising a stacked silicon top layer, a silicon dioxide layer, and a silicon base layer. The top layer had a thickness of 100 nm, the silicon dioxide layer had a thickness of 100 nm, and the silicon base layer had a thickness of 500 μm. The silicon wafer was ultrasonically cleaned in deionized water, ethanol, and deionized water to remove any residual contaminants, and then dried with nitrogen.

[0080] In the yellow light area of the clean room, a mask is attached to the silicon top surface of the cleaned silicon wafer and photoetched to a vertical depth of 150nm. The mask is then removed using organic matter to obtain a structured composite substrate.

[0081] Nanodiamonds (75nm), gallium oxide powder (99.8%), and a structured composite substrate were placed in a tube furnace. The furnace was first evacuated to a vacuum and preheated. High-purity argon was then used as a carrier gas to purge the chamber to remove impurities such as air. Argon was continuously introduced at a flow rate of 100 sccm to fill the deposition apparatus with protective gas. The pressure was also adjusted to maintain a constant value. The temperature was continuously raised from the preheating temperature, and oxygen was introduced at a flow rate of 1.6 sccm when the critical value of 980°C was reached. The temperature was maintained at 980°C for 10 minutes. After the growth was completed, the temperature was lowered to room temperature to obtain a silicon wafer device with a gallium oxide nanostructure.

[0082] Example 5

[0083] A silicon wafer was selected, comprising a stacked silicon top layer, a silicon dioxide layer, and a silicon base layer. The top layer had a thickness of 100 nm, the silicon dioxide layer had a thickness of 300 nm, and the silicon base layer had a thickness of 450 μm. The silicon wafer was ultrasonically cleaned in deionized water, ethanol, and deionized water to remove any residual surface contaminants, and then dried with nitrogen.

[0084] In the yellow light area of the clean room, a mask is attached to the silicon top surface of the cleaned silicon wafer and photoetched to a vertical depth of 150nm. The mask is then removed using organic matter to obtain a structured composite substrate.

[0085] Nanodiamonds (100nm), gallium oxide powder (99.8%), and a structured composite substrate were placed in a tube furnace. The furnace was first evacuated to a vacuum and preheated. High-purity argon was then used as a carrier gas to purge the chamber to remove impurities such as air. Argon was continuously introduced at a flow rate of 100sccm to fill the deposition apparatus with protective gas. The pressure was also adjusted to maintain a constant value. The temperature was continuously raised from the preheating temperature, and oxygen was introduced at a flow rate of 1.5sccm when the critical value of 960°C was reached. The temperature was maintained at 960°C for 10 minutes. After the growth was completed, the temperature was lowered to room temperature to obtain a silicon wafer device with a gallium oxide nanostructure.

[0086] Comparative Example 1

[0087] A silicon wafer was selected, comprising a stacked silicon top layer, a silicon dioxide layer, and a silicon base layer. The top layer had a thickness of 30 nm, the silicon dioxide layer had a thickness of 50 nm, and the silicon base layer had a thickness of 500 μm. The silicon wafer was ultrasonically cleaned in deionized water, ethanol, and deionized water to remove any residual contaminants, and then dried with nitrogen.

[0088] Nanodiamonds (30nm), gallium oxide powder (99.8%), metal Au catalyst, and structured composite substrate are placed in a tube furnace. The tube furnace is first evacuated to a vacuum and preheated. High-purity argon is then used as a carrier gas to purge to remove impurities such as air. Argon is continuously introduced at a flow rate of 100sccm to fill the deposition device with protective gas. The pressure is adjusted to maintain a certain constant value. The temperature is continuously increased from the preheating temperature, and when it reaches the critical value of 1100℃, oxygen is introduced at a flow rate of 1.5sccm. The temperature is maintained at 1100℃ for 10 minutes. After the growth is completed, the temperature is cooled to room temperature to obtain a silicon wafer device with a gallium oxide nanostructure on the surface.

[0089] Comparative Example 2

[0090] The only difference between Comparative Example 2 and Example 1 is that the vertical depth of etching is 10 nm.

[0091] Because the etching depth is too small, the etched grooves fail to penetrate the silicon top layer. The nanomaterials are connected through the conductive silicon top layer, making the nanostructures interconnected. Electrons are preferentially transmitted through the silicon top layer, which fails to fully utilize the unique advantages of nanomaterials. In addition, in the process of preparing gallium oxide nanostructures, based on the material growth mechanism, more crystal layers are generated between the nanostructures and the silicon top layer, which blocks the electron transmission channel and reduces the conductive efficiency. As a result, the prepared silicon wafer device with gallium oxide nanostructures has poor electrical performance.

[0092] Comparative Example 3

[0093] The only difference between Comparative Example 3 and Example 1 is that the vertical depth of etching is 100 nm.

[0094] Because the etching depth is too great, the etched grooves sequentially penetrate the silicon top layer and the silicon dioxide layer and extend into the interior of the silicon base layer. Based on the silicon dioxide layer, the silicon dots are insulated from each other. However, in the process of preparing gallium oxide nanostructures, the nanomaterials require a longer growth time to reach a length that can cross the blocking structure and form a nanojunction conductive channel. However, nanomaterials that are too long will reduce the efficiency of electron transmission and are not conducive to the formation of efficient electron transmission channels. Therefore, the prepared silicon wafer device with gallium oxide nanostructures has poor electrical performance.

[0095] Comparative Example 4

[0096] The only difference between Comparative Example 4 and Example 1 is that diamond powder (1 μm) is used as the reducing agent.

[0097] Due to the large size of the reducing agent, precise control of gallium oxide materials cannot be achieved. Figure 4 It can be seen that the prepared gallium oxide material is a short nanorod with a larger diameter, which loses the advantage of high specific surface area of the nanostructure, and thus the electrical performance of the silicon wafer device with the gallium oxide structure is poor.

[0098] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for preparing a silicon wafer device having a gallium oxide nanostructure, characterized in that: The preparation method comprises the following steps: Providing a silicon wafer, the silicon wafer comprising a silicon top layer, a buried oxide layer, and a silicon base layer stacked in sequence; Etching the silicon wafer in a direction perpendicular to the buried oxide layer from the silicon top layer to obtain a structured composite substrate having grooves, wherein the grooves include a first groove penetrating the silicon top layer and a second groove extending from the first groove to the interior of the buried oxide layer, and the depth of the second groove is less than the thickness of the buried oxide layer; The structured composite substrate is subjected to chemical vapor deposition in an environment of carbon nanomaterial, gallium source, and oxygen source, so that the gallium source is deposited and grown in the first groove to obtain a silicon wafer device having a gallium oxide nanostructure, wherein the carbon nanomaterial is selected from at least one of nanodiamonds and carbon nanotubes, and the gallium source is selected from gallium oxide powder.

2. The method for preparing a silicon wafer device having a gallium oxide nanostructure according to claim 1, wherein: The thickness of the silicon top layer is 10nm-50nm; and / or, the buried oxide layer has a thickness of 30 nm to 200 nm; And / or, the thickness of the silicon base layer is 500 μm-700 μm.

3. The method for preparing a silicon wafer device having a gallium oxide nanostructure according to claim 1, wherein: The material of the buried oxide layer is selected from at least one of silicon dioxide, aluminum oxide, and quartz.

4. The method for preparing a silicon wafer device having a gallium oxide nanostructure according to claim 1, wherein: The size of the carbon nanomaterial is 30nm-100nm.

5. The method for preparing a silicon wafer device having a gallium oxide nanostructure according to claim 1, wherein: The flow rate of the oxygen source is 0.5 sccm-3 sccm; And / or, the oxygen source is selected from oxygen gas.

6. The method for preparing a silicon wafer device having a gallium oxide nanostructure according to claim 1, wherein: The chemical vapor deposition temperature is 900° C.-1100° C., and the time is 3 min-10 min.

7. A silicon wafer device having a gallium oxide nanostructure prepared by the preparation method according to any one of claims 1 to 6, characterized in that: The silicon wafer device with gallium oxide nanostructure includes the structured composite substrate and the gallium oxide nanostructure grown in the first groove, wherein the gallium oxide nanostructure is composed of overlapping gallium oxide nanomaterials.

8. The silicon wafer device with gallium oxide nanostructure according to claim 7, characterized in that: When the gallium oxide nanomaterial is selected from gallium oxide nanowires, the aspect ratio of the gallium oxide nanowires is greater than 10 4 .

9. A semiconductor device, characterized in that: The semiconductor device includes the silicon wafer device with gallium oxide nanostructure according to claim 7 or 8, and the main current transmission direction of the semiconductor device is horizontal.

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