Gradual-approach register-based analog-to-digital converter and signal conversion method

Abstract

The present disclosure relates to a successive approximation register analog-to-digital converter and a signal conversion method. The successive approximation register analog-to-digital converter includes a charge injection digital-to-analog converter circuit, a comparator circuit, and a control logic circuitry. The charge injection digital-to-analog converter circuit includes a plurality of capacitors to sample a plurality of input signals to generate a first signal and a second signal, and a plurality of charge injection circuits to selectively adjust the first signal or the second signal according to a plurality of enable signals and a plurality of decision signals. The comparator circuit compares the first signal and the second signal to generate the decision signals. The control logic circuitry controls a circuit of the plurality of charge injection circuits to adjust the first signal and the second signal during an initial period, to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial period, and to generate the plurality of enable signals according to the decision signals and the adjusted switching sequence to generate a digital output during a conversion period.

Description

Technical Field

[0001] This application relates to analog-to-digital converters, specifically to a successive approximation register-type analog-to-digital converter and signal conversion method using a charge-injection digital-to-analog converter circuit. Background Technology

[0002] In approximation register-based analog-to-digital converters (ADCs), the ADC circuitry can be switched sequentially during the analog-to-digital conversion process to complete the operations related to the approximation algorithm. In some technologies, the ADC circuitry can be implemented using a current-source ADC. However, in these technologies, to mitigate the effects of mismatches between multiple current source circuits in the current-source ADC, an additional ADC is required to calibrate (or compensate) these current source circuits. To ensure the accuracy of this additional ADC, it will utilize a larger circuit area. This significantly increases the overall circuit area and device cost. Summary of the Invention

[0003] In some implementations, a progressive approximation register analog-to-digital converter includes a charge-injection digital-to-analog converter circuit, a comparator circuit, and a control logic circuit system. The charge-injection digital-to-analog converter circuit includes multiple capacitors and multiple charge-injection circuits. These capacitors are used to sample multiple input signals to generate a first signal and a second signal. These charge-injection circuits are used to selectively adjust at least one of the first signal or the second signal based on multiple enable signals and multiple decision signals. The comparator circuit is used to compare the first signal and the second signal to generate these decision signals. The control logic circuit system is used to control a first charge-injection circuit to adjust the first signal and the second signal during an initial period, to adjust the switching sequence of one of the first charge-injection circuits according to the decision signals corresponding to the initial period, and to generate the enable signals according to the decision signals and the adjusted switching sequence during an analog-to-digital conversion to produce a digital output.

[0004] In some embodiments, the signal conversion method includes the following operations: sampling multiple input signals using multiple capacitors to generate a first signal and a second signal; selectively adjusting at least one of the first signal or the second signal using multiple charge injection circuits based on multiple enable signals and multiple decision signals; comparing the first signal and the second signal to generate the decision signals; controlling a first charge injection circuit among the charge injection circuits to adjust the first signal and the second signal during an initial period to adjust a switching sequence of the first charge injection circuit based on the decision signals corresponding to the initial period; and generating the enable signals based on the decision signals and the adjusted switching sequence during an analog-to-digital conversion to generate a digital output.

[0005] The features, practical operation and effects of this application are described in detail below with reference to the drawings, showing preferred embodiments. Attached Figure Description

[0006] Figure 1 A schematic diagram of a successive approximation register-type analog-to-digital converter is shown according to some embodiments of this application;

[0007] Figure 2 Drawings based on some embodiments of this application Figure 1 A schematic diagram of the charge injection circuit in the diagram;

[0008] Figure 3A Drawings based on some embodiments of this application Figure 1 A flowchart of the multiple operations performed by the control logic circuit system during initialization;

[0009] Figure 3B Drawings based on some embodiments of this application Figure 3A A conceptual diagram illustrating some of the operations in the diagram; and

[0010] Figure 4 This is a flowchart illustrating a signal conversion method according to some embodiments of this application. Detailed Implementation

[0011] All terms used herein have their ordinary meanings. The definitions of the above terms in commonly used dictionaries, and the examples of any term used in this application, are merely illustrative and should not be construed as limiting the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0012] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit system” can be a single system formed by at least one circuit, and the term “circuit” can be a device that connects at least one transistor and / or at least one active or passive component in a certain manner to process signals.

[0013] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, and third, etc., are used herein to describe and distinguish individual elements. Therefore, a first element herein may also be referred to as a second element without departing from the intent of this application. For ease of understanding, similar elements in the various figures will be designated with the same reference numerals.

[0014] Figure 1 A schematic diagram of a successive approximation register analog-to-digital converter 100 is shown for some embodiments of this application. The successive approximation register analog-to-digital converter 100 includes switches SW1 and SW2, a comparator circuit 120, a charge injection digital-to-analog converter circuit 140, and a control logic circuit system 160.

[0015] Under the control of the control logic circuit system 160, switches SW1 and SW2 are turned on during sampling to transmit input signals VIP and VIN to the charge-injection digital-to-analog converter circuit 140. Under the control of the control logic circuit system 160, switches SW1 and SW2 are turned off during the analog-to-digital conversion operation of the approximation register-type analog-to-digital converter 100.

[0016] The charge-injection digital-to-analog converter circuit 140 includes capacitors C1 and C2 and multiple charge injection circuits 141[1] to 141[4]. During the sampling period of the approximation register type analog-to-digital converter 100, capacitors C1 and C2 can sample the input signal VIP and the input signal VIN respectively to generate signals VP and VN. During the analog-to-digital conversion period of the approximation register type analog-to-digital converter 100, multiple charge injection circuits 141[1] to 141[4] can selectively adjust the charge stored in at least one of capacitors C1 or C2 according to multiple enable signals EN1[1] to EN1[8], EN2[1] to EN2[4], EN3[1] to EN3[2] and EN4[1], decision signal VOP and decision signal VON, thereby adjusting the level of signal VP and / or the level of signal VN.

[0017] In this embodiment, multiple charge injection circuits 141[1] to 141[4] are configured to draw current from capacitor C1 or capacitor C2. For example, charge injection circuit 141[1] can be enabled according to multiple enable signals EN1[1] to EN1[8], and decides whether to draw current from capacitor C1 or capacitor C2 or not according to decision signal VOP and decision signal VON. Charge injection circuit 141[2] can be enabled according to multiple enable signals EN2[1] to EN2[4], and decide whether to draw current from capacitor C1 or capacitor C2 or not according to decision signal VOP and decision signal VON. Charge injection circuit 141[3] can be enabled according to multiple enable signals EN3[1] to EN3[2], and decide whether to draw current from capacitor C1 or capacitor C2 or not according to decision signal VOP and decision signal VON. The charge injection circuit 141[4] can be enabled according to multiple enable signals EN4[1], and decides whether to draw current from capacitor C1 or capacitor C2, or not to draw current from capacitor C1 and capacitor C2, according to decision signals VOP and VON. For ease of understanding, the current values ​​drawn by the multiple charge injection circuits 141[1] to 141[4] can be set sequentially as 8I, 4I, 2I and 1I based on binary encoding, where I is the unit current, but this application is not limited to this. The configuration of the multiple charge injection circuits 141[1] to 141[4] will be referred to later. Figure 2 illustrate.

[0018] In some embodiments, the control logic circuit system 160 can control the timing of switches SW1 and SW2, comparator circuit 120, and charge-injection digital-to-analog converter circuit 140. The control logic circuit system 160 can control at least one of the multiple charge-injection circuits 141[1] to 141[4] (hereinafter referred to as the first charge-injection circuit) to adjust signals VP and VN during an initial period, and the comparator circuit 120 can compare signals VP and VN during this initial period to generate decision signals VON and VOP corresponding to the initial period. The control logic circuit system 160 can adjust the switching sequence of the first charge-injection circuit according to the decision signals VON and VOP corresponding to the initial period. This can improve the linearity of the first charge-injection circuit, thereby improving the resolution of the digital output DOUT. In some embodiments, the control logic circuit system 160 can, during the initial period, adjust the timing based on multiple current source circuits (e.g., current source circuits in the first charge-injection circuit) in the first charge-injection circuit. Figure 3A The current adjustment switching sequence of multiple current source circuits 203[1]~203[8] in the circuit. The operation here will be discussed later. Figure 3A and Figure 3B illustrate.

[0019] In some embodiments, the aforementioned initial period may be (but is not limited to) a predetermined period that gradually approaches the initial startup of the register-type analog-to-digital converter 100. In some embodiments, the first charge injection circuit may be the charge injection circuit corresponding to the most significant bit in the charge injection digital-to-analog converter circuit 140 (e.g., charge injection circuit 141[1]). In other embodiments, the first charge injection circuit may be all the charge injection circuits with multiple current source circuits in the charge injection digital-to-analog converter circuit 140 (e.g., charge injection circuits 141[1] to 141[3]).

[0020] During analog-to-digital conversion, comparator circuit 120 compares signal VP and signal VN to generate decision signal VON and decision signal VOP. Control logic circuit system 160 generates the aforementioned multiple enable signals EN1[1]~EN1[8], EN2[1]~EN2[4], EN3[1]~EN3[2] and EN4[1] according to the decision signal VON and decision signal VOP corresponding to the analog-to-digital conversion and the adjusted switching order, and generates digital output DOUT. For example, control logic circuit system 160 can execute a successive approximation algorithm (e.g., but not limited to, a binary search algorithm) according to the decision signal VON and decision signal VOP corresponding to the analog-to-digital conversion and generate multiple enable signals EN1[1]~EN1[8], EN2[1]~EN2[4], EN3[1]~EN3[2] and EN4[1] according to the adjusted switching order.

[0021] In the above process, the control logic circuit system 160 can execute an approximation algorithm based on the decision signals VON and VOP generated at each comparison to determine one bit of the digital output DOUT. In some embodiments, the control logic circuit system 160 may be implemented by one or more digital signal processing circuits, wherein the one or more digital signal processing circuits can be used to execute the approximation algorithm, control the timing of other circuits in the approximation register analog-to-digital converter 100, and correct the first charge injection circuit during the initial period (i.e., ... Figure 3A (Multiple operations within).

[0022] Figure 2 Drawings based on some embodiments of this application Figure 1A schematic diagram of the charge injection circuit 141[1] is shown. In this example, the charge injection circuit 141[1] includes multiple control circuits 201[1] to 201[8], multiple switching circuits 202[1] to 202[8], and multiple current source circuits 203[1] to 203[8]. For the sake of simplicity, some of the above circuits are omitted in the figure.

[0023] Each of the multiple control circuits 201[1] to 201[8] generates one of a plurality of switching signals E1[1] to E1[8] based on a corresponding enable signal EN1[1] to EN1[8], a decision signal VOP, and a decision signal VON. Specifically, control circuit 201[1] generates switching signal E1[1] based on enable signal EN1[1], decision signal VOP, and decision signal VON. Control circuit 201[2] generates switching signal E1[2] based on enable signal EN1[2], decision signal VOP, and decision signal VON. Similarly, control circuit 201[8] generates switching signal E1[8] based on enable signal EN1[8], decision signal VOP, and decision signal VON. In some embodiments, each of the multiple control circuits 201[1] to 201[8] may be implemented by several logic gates to generate multiple control bits corresponding to a plurality of switching signals E1[1] to E1[8].

[0024] Each of the multiple switching circuits 202[1] to 202[8] is selectively connected to one of the capacitors C1 and C2 or not connected to the capacitors C1 and C2 according to a corresponding bit of a multiple switching signal E1[1] to E1[8]. For example, each of the multiple switching circuits 202[1] to 202[8] may be implemented by several switches. These switches may be selectively turned on to connect to the capacitors C1 or C2 according to multiple bits of a corresponding bit of a multiple switching signal E1[1] to E1[8], or may be turned off to not connect to the capacitors C1 and C2 according to all of these bits. Each of the multiple current source circuits 203[1] to 203[8] may be connected to the capacitors C1 or C2 via a corresponding bit of these multiple switching circuits 202[1] to 202[8] to discharge the capacitors C1 or C2 (i.e., draw current from the capacitors C1 or C2). For example, switching circuit 202[1] can be connected to capacitor C1 according to switching signal E1[1], and current source circuit 203[1] can be connected to capacitor C1 via switching circuit 202[1] to discharge capacitor C1. In this way, the level of signal VP will become low. Alternatively, if one of the corresponding switching circuits of these multiple switching circuits 202[1] to 202[8] (e.g., switching circuit 202[1]) is not connected to capacitors C1 and C2, one of the corresponding current source circuits 203[1] to 203[8] (e.g., current source circuit 203[1]) cannot discharge capacitors C1 or C2 via the corresponding switching circuit (i.e., does not draw current from capacitors C1 and C2). By analogy, the arrangement of the remaining switching circuits 202[2] to 202[8] and the remaining current source circuits 203[2] to 203[8] should be understood.

[0025] As previously stated, the charge injection circuit 141[1] draws a current of 8I. In this example, the multiple current source circuits 203[1] to 203[8] are set up in a thermometer-like manner. In other words, each of the multiple current source circuits 203[1] to 203[8] draws a unit current I. When all the current source circuits 203[1] to 203[8] are enabled (i.e., the corresponding multiple switching circuits 202[1] to 202[8] are turned on to connect to capacitor C1 or capacitor C2), the total current that the charge injection circuit 141[1] can draw from capacitor C1 or capacitor C2 is 8I.

[0026] The arrangement of the multiple charge injection circuits 141[2] to 141[4] is similar to that of charge injection circuit 141[1], so it will not be repeated here. It should be understood that Figure 1 as well as Figure 2The number of circuits and the aforementioned current values ​​are for illustrative purposes only and are not intended to limit this application. Adjustments may be made according to different practical application requirements. Figure 1 as well as Figure 2 The number of circuits and / or current values ​​in the circuit.

[0027] Figure 3A Drawings based on some embodiments of this application Figure 1 A flowchart of multiple operations performed by the control logic circuit system 160 during the initial period. Figure 3B Drawings based on some embodiments of this application Figure 3A A schematic diagram illustrating some of the operations. To facilitate understanding of the operations related to adjusting the switching sequence of the current injection circuit 141[1], please refer to the diagram. Figure 3A and Figure 3B .

[0028] like Figure 3B As shown, the currents of the multiple current source circuits 203[1] to 203[8] are I1 to I8 in sequence. Ideally, each of the multiple currents I1 to I8 is a unit current I (i.e., the weights of each of the multiple current source circuits 203[1] to 203[8] are equal), and the control logic circuit system 160 can switch at least one corresponding current source circuit 203[1] to 203[8] according to a digital code and a predetermined sequence to generate a corresponding analog output. The predetermined sequence can be to enable the corresponding number of current source circuits in sequence according to their numbers in the multiple current source circuits 203[1] to 203[8]. For example, if the value corresponding to the digital code is 1, the control logic circuit system 160 can enable the current source circuit 203[1] to generate the corresponding analog output (i.e., a unit current I). If the value corresponding to the digital code is 2, the control logic circuit system 160 can enable the current source circuit 203[1] and the current source circuit 203[2] to generate the corresponding analog output (i.e., twice the unit current I). However, due to the influence of actual process variations, there may be mismatches between the multiple current source circuits 203[1] to 203[8], causing the multiple currents I1 to I8 to deviate (i.e., the weights of the multiple current source circuits 203[1] to 203[8] to have errors). Under this condition, if the control logic circuit system 160 enables the multiple current source circuits 203[1] to 203[8] in the predetermined order, it will produce an analog output with poor linearity. In order to improve linearity, the control logic circuit system 160 can perform the following during the initial period: Figure 3A Multiple operations are performed to adjust the switching order of multiple current source circuits 203[1] to 203[8] (equivalent to correcting the weights between multiple current source circuits 203[1] to 203[8]).

[0029] Reference Figure 3ADuring operation S310, the first current source circuit (e.g., a) among multiple current source circuits is controlled during the initial period. Figure 2 The current source circuit 203[4] adjusts the charge stored in the first capacitor (e.g., capacitor C1) among the multiple capacitors to adjust the first signal (e.g., signal VP) output by the first capacitor. During operation S320, the second current source circuit (e.g., the current source circuit of the multiple current source circuits) is controlled during the initial period. Figure 2 The current source circuit 203[1] adjusts the charge stored in the second capacitor (e.g., capacitor C2) among the multiple capacitors to adjust the second signal (e.g., signal VN) output by the second capacitor.

[0030] For example, during the initial period, capacitors C1 and C2 can be reset by a predetermined voltage (e.g., but not limited to, common-mode voltage) to store a predetermined amount of charge. Taking the current I4 of the current source circuit 203 [4] as a reference value, the control logic circuit system 160 can output an enable signal EN1 [4] to control the current source circuit 203 [4] to draw current I4 from capacitor C1. In this way, the charge stored in capacitor C1 will decrease to adjust the level of signal VP. Similarly, during the initial period, the control logic circuit system 160 can output an enable signal EN1 [1] to control the current source circuit 203 [1] to draw current I1 from capacitor C2. In this way, the amount of charge stored in capacitor C2 will decrease to adjust the level of signal VN.

[0031] Continue to refer to Figure 3A In operation S330, the first signal and the second signal are repeatedly compared to generate multiple decision signals corresponding to the initial period (e.g., decision signal VON and decision signal VOP). In operation S340, the difference between the current value of the first current source circuit and the current value of the second current source circuit is confirmed based on the multiple decision signals corresponding to the initial period.

[0032] In the previous example, if signal VP is lower than signal VN, comparator circuit 120 outputs a decision signal VON with a first logic value (e.g., logic value 1) and a decision signal VOP with a second logic value (e.g., logic value 0). Under this condition, it means that the amount of charge stored in capacitor C1 is less than the amount of charge stored in capacitor C2. In other words, current source circuit 203 [4] can draw more charge in the same period compared to current source circuit 203 [1]. Therefore, control logic circuit system 160 can infer that the current I4 of current source circuit 203 [4] is higher than the current I1 of current source circuit 203 [1]. Alternatively, if signal VP is higher than signal VN, comparator circuit 120 outputs a decision signal VON with a second logic value (e.g., logic value 0) and a decision signal VOP with a first logic value (e.g., logic value 1). Under this condition, it means that the amount of charge stored in capacitor C1 is more than the amount of charge stored in capacitor C2. In other words, compared to current source circuit 203[1], current source circuit 203[4] can draw less charge in the same period. Therefore, control logic circuit system 160 can infer that the current I4 of current source circuit 203[4] is lower than the current I1 of current source circuit 203[1].

[0033] Based on the above operations, comparator circuit 120 can repeatedly compare signal VP and signal VN to obtain multiple sets (e.g., but not limited to, 1000 sets) of decision signals VON and VOP. Comparator circuit 120 can record these decision signals VON and VOP to determine the difference between the value of current I4 of current source circuit 203 [4] and the value of current I1 of current source circuit 203 [1].

[0034] Continue to refer to Figure 3A In operation S350, operations S310 to S340 are repeated to confirm the difference between the current value of each of the remaining current source circuits and the current value of the first current source circuit (e.g., the value of current I4). For example, the control logic circuit system 160 can reset capacitors C1 and C2 again and control current source circuit 203[4] to draw current I4 from capacitor C1 (as mentioned above, assuming current I4 is a reference value) and control current source circuit 203[2] to draw current I2 from capacitor C2. Then, comparator circuit 120 can repeatedly compare signal VP and signal VN to obtain multiple sets of decision signals VON and VOP. Comparator circuit 120 can record these decision signals VON and VOP to determine the difference between current I4 of current source circuit 203[4] and current I2 of current source circuit 203[2]. Similarly, the control logic circuit system 160 can obtain multiple sets of decision signals VOP and VON to determine the differences between the values ​​of multiple currents I1 to I8.

[0035] For example, in 1000 comparison results between current source circuit 203[4] and current source circuit 203[1], 700 comparison results (e.g., the number of times the decision signal VON has a logic value of 1 and the decision signal VOP has a logic value of 0) indicate that current I4 is greater than current I1. In 1000 comparison results between current source circuit 203[4] and current source circuit 203[2], 800 comparison results (e.g., the number of times the decision signal VON has a logic value of 0 and the decision signal VOP has a logic value of 1) indicate that current I4 is less than current I2. In 1000 comparison results between current source circuit 203[4] and current source circuit 203[3], 990 comparison results (e.g., the number of times the decision signal VON has a logic value of 0 and the decision signal VOP has a logic value of 1) indicate that current I4 is less than current I3. Based on the aforementioned multiple sets of decision signals VOP and VON, the control logic circuit system 160 can confirm that the value of current I4 is greater than the value of current I1, and the value of current I3 is greater than the value of current I2 and greater than the value of current I4, which can be expressed as I3 > I2 > I4 > I1. And so on, as... Figure 3B As shown, the control logic circuit system 160 can sort the values ​​of multiple currents I1 to I8 according to the above-mentioned multiple sets of decision signals VOP and decision signal VON.

[0036] The above description illustrates only one implementation of operation S350 using multiple decision-making methods, but this application is not limited thereto. In other embodiments, the control logic circuit system 160 may perform a statistical operation based on multiple sets of decision signals VOP and VON to determine the differences between the values ​​of multiple currents I1 to I8. Furthermore, the values ​​mentioned in the above examples are merely illustrative, and this application is not limited thereto.

[0037] Continue to refer to Figure 3A In operation S360, the currents of these current source circuits are gradually summed in an increasing order to adjust the switching sequence of the multiple current source circuits.

[0038] For example, such as Figure 3BAs shown, the control logic circuit system 160 can switch multiple current source circuits 203[1] to 203[8] according to the incrementing order of the digital codes. For example, in response to digital code D1, the current source circuit 203[1] with the minimum current I1 is selected (i.e. enabled) to generate the corresponding analog output (i.e., current I1). In response to digital code D2, the current source circuit 203[1] and the current source circuit 203[3] with the highest current I3 are selected to generate the corresponding analog output (i.e., the sum of current I1 and current I3). In response to digital code D3, the current source circuit 203[1], the current source circuit 203[3], and the current source circuit 203[8] with the second lowest current I8 are selected to generate the corresponding analog output (i.e., the sum of current I1, current I3, and current I8). In response to digital code D4, current source circuits 203[1], 203[3], 203[8], and 203[2] with the second highest current I2 are selected to generate corresponding analog outputs (i.e., the sum of currents I1, I3, I8, and I2). Similarly, the control logic circuit system 160 can adjust the switching order by progressively summing the currents of these current source circuits 203[1] to 203[8] according to the remaining digital codes D5 to D8. In this way, a more linear (e.g., ...) analog output can be generated. Figure 3B The simulated output (shown by the dashed line in the image).

[0039] In some embodiments, the control logic circuit system 160 further includes a register circuit (not shown) that can record the correspondence between multiple enable signals EN1[1] to EN1[8] and the adjusted switching order. For example, after recording the correspondence, during analog-to-digital conversion, if the control logic circuit system 160 determines that a digital code in the digital output DOUT is digital code D1 in response to the decision signal VOP and the decision signal VON, the control logic circuit system 160 can output an enable signal EN1[1] with the corresponding logic value to enable the current source circuit 203[1]. Alternatively, if the control logic circuit system 160 determines that the digital code in the digital output DOUT is digital code D2 in response to the decision signal VOP and the decision signal VON, the control logic circuit system 160 can output an enable signal EN1[1] and an enable signal EN1[3] with the corresponding logic values ​​to enable the current source circuit 203[1] and the current source circuit 203[3].

[0040] Through the above operations, the control logic circuit system 160 can correct the charge-injection digital-to-analog converter circuit 140 without using additional digital-to-analog converters or current source circuits. In this way, the linearity of the charge-injection digital-to-analog converter circuit 140 can be improved without significantly increasing the circuit area.

[0041] Figure 4This is a flowchart of a signal conversion method 400 according to some embodiments of this application. In operation S410, multiple input signals (e.g., input signal VIP and input signal VIN) are sampled by multiple capacitors (e.g., capacitor C1 and capacitor C2) to generate a first signal and a second signal (e.g., signal VP and signal VN). In operation S420, at least one of the first signal or the second signal is selectively adjusted by multiple charge injection circuits (e.g., charge injection circuits 141[1] to 141[4]) according to multiple enable signals and multiple decision signals. In operation S430, the first signal and the second signal are compared to generate these decision signals. In operation S440, during an initial period, the first charge injection circuit in these charge injection circuits is controlled to adjust the first signal and the second signal to adjust the switching order of the first charge injection circuit according to the decision signals corresponding to the initial period. In operation S450, during analog-to-digital conversion, these enable signals are generated based on these decision signals and the adjusted switching sequence to produce a digital output (e.g., digital output DOUT).

[0042] The above-described operations can be understood by referring to the foregoing embodiments, and therefore will not be repeated here. The multiple operations of the signal conversion method 400 described above are merely examples and are not limited to being executed in the order shown in this example. Without departing from the operation mode and scope of the embodiments of this application, various operations in the signal conversion method 400 may be appropriately added, replaced, omitted, or executed in a different order (for example, they may be executed simultaneously or partially simultaneously). For example, operation S440 may be executed during the initial period after the approximation register type analog-to-digital converter 100 is powered on, and multiple operations S410, S420, S430, and S450 may be executed during the period when the approximation register type analog-to-digital converter 100 performs analog-to-digital conversion.

[0043] In summary, the approximation register-based analog-to-digital converter and signal conversion method provided in some embodiments of this application can reorder the switching sequence of multiple current source circuits in the charge injection circuit during the initial period after the device is powered on. This reduces the effects of mismatch and improves linearity without using an additional digital-to-analog converter.

[0044] Although the embodiments of this application are described above, these embodiments are not intended to limit this application. Those skilled in the art can make changes to the technical features of this application based on the express or implied content of this application. All such changes may fall within the scope of patent protection sought by this application. In other words, the scope of patent protection of this application shall be determined by the scope of the claims in this specification.

[0045] [Symbol Explanation]

[0046] 100: Gradually Approaching Register-Based Analog-to-Digital Converter

[0047] 120: Comparator Circuit

[0048] 140: Charge-injection digital-to-analog converter circuit

[0049] 141[1]~141[4]: Charge injection circuit

[0050] 160: Control logic circuit system

[0051] 201[1]~201[8]: Control circuit

[0052] 202[1]~202[8]: Switching circuit

[0053] 203[1]~203[8]: Current source circuit

[0054] 400: Signal Conversion Methods

[0055] C1, C2: Capacitors

[0056] D1~D8: Numeric code

[0057] DOUT: Digital Output

[0058] E1[1]~E1[8]: Switching signal

[0059] EN1[1]~EN1[8],EN2[1]~EN2[4],EN3[1]~EN3[2],EN4[1]: Enable signal

[0060] I: Unit current

[0061] I1~I8: Current

[0062] S310, S320, S330, S340, S350, S360: Operation

[0063] S410, S420, S430, S440, S450: Operation

[0064] SW1, SW2: Switches

[0065] VIN, VIP: Input signal

[0066] VN,VP: Signals

[0067] VON, VOP: Decision signals.

Claims

1. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising: a charge injection digital-to-analog converter (DAC) circuit including a plurality of capacitors to sample a plurality of input signals to generate a first signal and a second signal, and a plurality of charge injection circuits to selectively adjust at least one of the first signal and the second signal according to a plurality of enable signals and a plurality of decision signals; a comparator circuit to compare the first signal and the second signal to generate the plurality of decision signals; and a control logic circuit system to control a first charge injection circuit of the plurality of charge injection circuits to adjust the first signal and the second signal during an initialization period, to adjust a switching sequence of the first charge injection circuit according to the plurality of decision signals corresponding to the initialization period, and to generate the plurality of enable signals according to the plurality of decision signals and the adjusted switching sequence during an analog-to-digital conversion period to generate a digital output.

2. The SAR ADC of claim 1, wherein the control logic circuit system is to adjust the switching sequence based on currents of a plurality of current source circuits in the first charge injection circuit during the initialization period.

3. The SAR ADC of claim 1, wherein during the initialization period, the control logic circuit system is to control a first current source circuit of the first charge injection circuit to adjust the first signal and a second current source circuit of the first charge injection circuit to adjust the second signal, the comparator circuit is further to repeatedly compare the first signal and the second signal to generate the plurality of decision signals corresponding to the initialization period, and the control logic circuit system is further to confirm a difference between a current value of the first current source circuit and a current value of the second current source circuit according to the plurality of decision signals corresponding to the initialization period to adjust the switching sequence.

4. The SAR ADC of claim 1, wherein the first charge injection circuit includes a plurality of current source circuits, and the control logic circuit system is to progressively sum currents of the plurality of current source circuits based on an increasing order to adjust the switching sequence.

5. The SAR ADC of claim 1, wherein the control logic circuit system is further to record a correspondence between the plurality of enable signals and the adjusted switching sequence.

6. The SAR ADC of claim 1, wherein the plurality of charge injection circuits is to selectively adjust charges stored in at least one of the plurality of capacitors according to the plurality of enable signals and the plurality of decision signals to adjust at least one corresponding one of the first signal and the second signal.

7. The SAR ADC of claim 1, wherein the first charge injection circuit includes: a plurality of control circuits, wherein each of the plurality of control circuits is to generate one of a plurality of switching signals according to a corresponding one of the plurality of enable signals and the plurality of decision signals. ​ ​ ​ ​ a plurality of switching circuits, wherein each of the plurality of switching circuits is configured to selectively connect to one of the plurality of capacitors or not connect to the plurality of capacitors according to a corresponding one of the plurality of switching signals; and a plurality of current source circuits, wherein each of the plurality of current source circuits is configured to discharge the one of the plurality of capacitors via a corresponding one of the plurality of switching circuits.

8. A signal conversion method, comprising: sampling a plurality of input signals by a plurality of capacitors to generate a first signal and a second signal; selectively adjusting at least one of the first signal and the second signal by a plurality of charge injection circuits according to a plurality of enable signals and a plurality of decision signals; comparing the first signal and the second signal to generate the plurality of decision signals; controlling a first charge injection circuit of the plurality of charge injection circuits to adjust the first signal and the second signal according to a switching sequence of the first charge injection circuit adjusted according to the plurality of decision signals corresponding to an initial period during an initial period; and generating the plurality of enable signals according to the plurality of decision signals and the adjusted switching sequence during an analog-to-digital conversion period to generate a digital output.

9. The signal conversion method of claim 8, wherein controlling the first charge injection circuit to adjust the first signal and the second signal according to the switching sequence adjusted according to the plurality of decision signals corresponding to the initial period during the initial period comprises: adjusting the switching sequence based on currents of a plurality of current source circuits in the first charge injection circuit during the initial period.

10. The signal conversion method of claim 8, wherein controlling the first charge injection circuit to adjust the first signal and the second signal according to the switching sequence adjusted according to the plurality of decision signals corresponding to the initial period during the initial period comprises: adjusting the first signal by a first current source circuit in the first charge injection circuit during the initial period; adjusting the second signal by a second current source circuit in the first charge injection circuit during the initial period; repeating comparing the first signal and the second signal to generate the plurality of decision signals corresponding to the initial period; and identifying a difference between a current value of the first current source circuit and a current value of the second current source circuit according to the plurality of decision signals corresponding to the initial period to adjust the switching sequence.

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